HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · boards/LFR-EM/Makefile.inc

Few updates....

Few updates. Added LFR filter random ram init test.

Alexis Jeandet - - Load All Authors

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r662:f19abbf47ea7 SOLO_LFR_01-5B (LFR-EM) default


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             Makefile.inc
        
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        Alexis Jeandet
    
Sync

              r181
            
      PACKAGE=\"\"

      SPEED=Std

      SYNFREQ=50

        Alexis Jeandet
    
Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...

              r662
            
      TECHNOLOGY=ProASIC3E

      LIBERO_DIE=IT14X14M4

      PART=A3PE3000

      DESIGNER_VOLTAGE=COM

      DESIGNER_TEMP=COM

        Alexis Jeandet
    
Sync

              r181
            
      DESIGNER_PACKAGE=FBGA

      DESIGNER_PINS=324

      MANUFACTURER=Actel

        Alexis Jeandet
    
Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...

              r662
            
      MGCTECHNOLOGY=Proasic3

        Alexis Jeandet
    
Sync

              r181
            
      MGCPART=$(PART)

      MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}

      LIBERO_PACKAGE=fg$(DESIGNER_PINS)

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Alexis Jeandet Sync	r181	PACKAGE=\"\"
		SPEED=Std
		SYNFREQ=50

Alexis Jeandet Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...	r662	TECHNOLOGY=ProASIC3E
		LIBERO_DIE=IT14X14M4
		PART=A3PE3000

		DESIGNER_VOLTAGE=COM
		DESIGNER_TEMP=COM
Alexis Jeandet Sync	r181	DESIGNER_PACKAGE=FBGA
		DESIGNER_PINS=324

		MANUFACTURER=Actel
Alexis Jeandet Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...	r662	MGCTECHNOLOGY=Proasic3
Alexis Jeandet Sync	r181	MGCPART=$(PART)
		MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
		LIBERO_PACKAGE=fg$(DESIGNER_PINS)