leon3mp.srr
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TextLexer
martin
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r100 | #Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 | ||
#install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1 | ||||
#OS: 6.1 | ||||
#Hostname: PC-SOLAR2 | ||||
#Implementation: synthesis | ||||
#Thu Oct 25 15:23:30 2012 | ||||
$ Start of Compile | ||||
#Thu Oct 25 15:23:30 2012 | ||||
Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 | ||||
@N|Running in 32-bit mode | ||||
Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved | ||||
@N: CD720 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns | ||||
@N:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":49:7:49:13|Top entity is set to leon3mp. | ||||
@W: CD433 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\sparc\sparc_disas.vhd":720:24:720:24|No design units in file | ||||
VHDL syntax check successful! | ||||
@N: CD231 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vhd\std_logic_textio.vhd":79:15:79:16|Using onehot encoding for type mvl9plus ('U'="1000000000") | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":49:7:49:13|Synthesizing work.leon3mp.behavioral | ||||
@W: CD729 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":337:4:337:8|Component declaration has 2 generics but entity declares only 1 generics | ||||
@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":404:2:404:8|Port lock of entity techmap.clkpad is unconnected | ||||
@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":406:2:406:8|Port clkc of entity techmap.clkgen is unconnected | ||||
@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":406:2:406:8|Port clkb of entity techmap.clkgen is unconnected | ||||
@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":406:2:406:8|Port clk2xu of entity techmap.clkgen is unconnected | ||||
@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":406:2:406:8|Port clk1xu of entity techmap.clkgen is unconnected | ||||
@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":406:2:406:8|Port clk4x of entity techmap.clkgen is unconnected | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":124:7:124:13|Signal resetnl is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":133:7:133:9|Signal cgi.clksel is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":133:7:133:9|Signal cgi.pllref is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_8.pindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_8.pconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_8.pconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_8.pirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_8.prdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_10.pindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_10.pconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_10.pconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_10.pirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_10.prdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_12.pindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_12.pconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_12.pconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_12.pirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_12.prdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_13.pindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_13.pconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_13.pconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_13.pirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_13.prdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_14.pindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_14.pconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_14.pconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_14.pirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":137:7:137:10|Signal apbo_14.prdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_15.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_14.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_13.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_12.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_11.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_10.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_9.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_8.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_7.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_6.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_5.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_4.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hcache is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hsplit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hrdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hresp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":139:7:139:11|Signal ahbso_3.hready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_15.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_14.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_13.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_12.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_11.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_10.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_9.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_8.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_7.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_6.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_5.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_4.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_3.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hconfig_0 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hconfig_1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hconfig_2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hconfig_3 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hconfig_4 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hconfig_5 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hconfig_6 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hconfig_7 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hirq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hprot is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.haddr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":141:7:141:11|Signal ahbmo_2.hbusreq is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":143:7:143:14|Signal ahbuarti.extclk is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":143:7:143:14|Signal ahbuarti.ctsn is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Signal memi.edac is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Signal memi.scb is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Signal memi.cb is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Signal memi.sd is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":150:7:150:9|Signal wpo.wprothit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":156:7:156:10|Signal gpti.wdogen is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Signal gpioi.sig_en is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Signal gpioi.sig_in is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 7 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 8 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 9 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 10 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 11 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 12 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 13 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 14 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 15 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 16 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 17 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 18 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 19 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 20 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 21 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 22 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 23 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 24 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 25 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 26 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 27 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 28 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 29 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 30 of signal gpioi.din is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 31 of signal gpioi.din is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":171:7:171:17|Signal fifoin_full is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":172:7:172:18|Signal fifoin_empty is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":173:7:173:17|Signal fifoin_data is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":220:7:220:11|Signal s_out is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":223:7:223:12|Signal reader is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":224:7:224:9|Signal try is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":225:7:225:12|Signal txdint is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":228:7:228:20|Signal sample_clk_out is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\iopad.vhd":32:7:32:11|Synthesizing techmap.iopad.rtl | ||||
Post processing for techmap.iopad.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":45:7:45:12|Synthesizing gaisler.grgpio.rtl | ||||
Post processing for gaisler.grgpio.rtl | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_6(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_5(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_4(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_3(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_2(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_1(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_0(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.bypass(6 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.ilat(6 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.edge(6 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.level(6 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.imask(6 downto 0) | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":47:7:47:13|Synthesizing gaisler.apbuart.rtl | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":77:15:77:16|Using sequential encoding for type txfsmtype | ||||
@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":76:15:76:16|Using onehot encoding for type rxfsmtype (idle="10000") | ||||
Post processing for gaisler.apbuart.rtl | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.rwaddr(0) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.tshift(10) is always 1, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.tcnt(1) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.rcnt(1) is always 0, optimizing ... | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Pruning Register bit 1 of r.tcnt(1 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Pruning Register bit 10 of r.tshift(10 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Pruning Register bit 1 of r.rcnt(1 downto 0) | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":47:7:47:13|Synthesizing gaisler.gptimer.rtl | ||||
Post processing for gaisler.gptimer.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":43:7:43:13|Synthesizing grlib.apbctrl.rtl | ||||
Post processing for grlib.apbctrl.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\outpad.vhd":32:7:32:12|Synthesizing techmap.outpad.rtl | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\outpad.vhd":39:7:39:10|Signal padx is undriven | ||||
Post processing for techmap.outpad.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\inpad.vhd":32:7:32:11|Synthesizing techmap.inpad.rtl | ||||
Post processing for techmap.inpad.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\ahbuart.vhd":45:7:45:13|Synthesizing gaisler.ahbuart.struct | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":35:7:35:10|Synthesizing gaisler.dcom.struct | ||||
@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":49:21:49:22|Using onehot encoding for type dcom_state_type (idle="100000") | ||||
Post processing for gaisler.dcom.struct | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":147:8:147:9|Pruning Register r.hresp(1 downto 0) | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":39:7:39:15|Synthesizing gaisler.dcom_uart.rtl | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":66:15:66:16|Using sequential encoding for type txfsmtype | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":65:15:65:16|Using sequential encoding for type rxfsmtype | ||||
Post processing for gaisler.dcom_uart.rtl | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":49:4:49:5|uo.flow is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":49:4:49:5|uo.txen is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Register bit r.tshift(10) is always 1, optimizing ... | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Pruning Register bit 10 of r.tshift(10 downto 0) | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\ahbmst.vhd":35:7:35:12|Synthesizing gaisler.ahbmst.rtl | ||||
Post processing for gaisler.ahbmst.rtl | ||||
Post processing for gaisler.ahbuart.struct | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":37:7:37:13|Synthesizing grlib.ahbctrl.rtl | ||||
Post processing for grlib.ahbctrl.rtl | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register r.lsplmst(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register reg0.r.defmst_3 | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register r.beat(3 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register r.hsize(2 downto 0) | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Register bit r.ldefmst is always 0, optimizing ... | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 0 of r.htrans(1 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 15 of r.haddr(15 downto 2) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 14 of r.haddr(15 downto 2) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 13 of r.haddr(15 downto 2) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 12 of r.haddr(15 downto 2) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 11 of r.haddr(15 downto 2) | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":34:7:34:18|Synthesizing lpp.ssram_plugin.ar_ssram_plugin | ||||
@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":80:12:80:13|Using onehot encoding for type statet (idle="10000") | ||||
Post processing for lpp.ssram_plugin.ar_ssram_plugin | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":169:4:169:5|Pruning Register OEreg | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":137:4:137:5|Pruning Register RAMSN_reg | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\outpad.vhd":115:7:115:13|Synthesizing techmap.outpadv.rtl | ||||
Post processing for techmap.outpadv.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\iopad.vhd":137:7:137:12|Synthesizing techmap.iopadv.rtl | ||||
Post processing for techmap.iopadv.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":46:7:46:11|Synthesizing esa.mctrl.rtl | ||||
@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":120:18:120:19|Using onehot encoding for type memcycletype (idle="10000000") | ||||
@W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":740:4:740:17|OTHERS clause is not synthesized | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|Signal sdmo.vhready is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|Signal sdmo.bsel is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|Signal sdmo.hsel is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":199:7:199:9|Signal sdi.merror is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.dqm is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.casn is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.rasn is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.sdwen is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.sdcsn is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.sdcke is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Signal rrsbdrive is undriven | ||||
Post processing for esa.mctrl.rtl | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 0 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 1 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 2 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 3 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 4 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 5 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 6 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 7 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 8 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 9 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 10 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 11 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 12 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 13 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 14 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 15 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 16 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 17 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 18 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 19 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 20 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 21 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 22 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 23 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 24 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 25 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 26 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 27 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 28 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 29 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 30 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 31 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 32 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 33 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 34 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 35 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 36 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 37 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 38 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 39 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 40 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 41 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 42 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 43 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 44 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 45 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 46 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 47 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 48 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 49 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 50 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 51 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 52 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 53 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 54 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 55 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 56 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 57 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 58 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 59 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 60 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 61 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 62 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 63 of signal rrsbdrive is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 0 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 1 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 2 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 3 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 4 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 5 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 6 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 7 of signal lsdo.dqm is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|lsdo.casn is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|lsdo.rasn is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|lsdo.sdwen is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 0 of signal lsdo.sdcsn is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 1 of signal lsdo.sdcsn is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 0 of signal lsdo.sdcke is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 1 of signal lsdo.sdcke is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":199:7:199:9|sdi.merror is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":199:7:199:9|sdi.idle is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|sdmo.vhready is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|sdmo.bsel is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|sdmo.hsel is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|memo.rs_edac_en is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|memo.sdram_en is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|memo.ce is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 0 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 1 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 2 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 3 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 4 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 5 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 6 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 7 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 8 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 9 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 10 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 11 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 12 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 13 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 14 of signal memo.sa is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 0 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 1 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 2 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 3 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 4 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 5 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 6 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 7 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 8 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 9 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 10 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 11 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 12 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 13 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 14 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 15 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 16 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 17 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 18 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 19 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 20 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 21 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 22 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 23 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 24 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 25 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 26 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 27 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 28 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 29 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 30 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 31 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 32 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 33 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 34 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 35 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 36 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 37 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 38 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 39 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 40 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 41 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 42 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 43 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 44 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 45 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 46 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 47 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 48 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 49 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 50 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 51 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 52 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 53 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 54 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 55 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 56 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 57 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 58 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 59 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 60 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 61 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 62 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 63 of signal memo.sddata is floating - a simulation mismatch is possible | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register stdregs.rsbdrive_3(63 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sd(63 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sa(14 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.htrans(1 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sdhsel | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.hsel | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.haddr(31 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.mcfg2.sdren | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.mcfg2.srdis | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.mcfg2.brdyen | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register stdregs.r.nbdrive_3(3 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.ready8 | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.readdata(31 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sdwritedata(63 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.writedata8(15 downto 0) | ||||
@W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Optimizing register bit r.ramsn(4) to a constant 1 | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Pruning Register bit 4 of r.ramsn(4 downto 0) | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":43:7:43:11|Synthesizing gaisler.irqmp.rtl | ||||
Post processing for gaisler.irqmp.rtl | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":316:8:316:9|Pruning Register r.ibroadcast(15 downto 1) | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3.vhd":44:7:44:10|Synthesizing gaisler.dsu3.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":37:7:37:11|Synthesizing gaisler.dsu3x.rtl | ||||
@W: CD434 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":164:79:164:86|Signal hrdata2x in the sensitivity list is not used in the process | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Signal tbo.data is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.break is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbwr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.write is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.read is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.mask is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.addr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.write is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.read is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.mask is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.addr is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.delaycnt is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.dcnten is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.bphit2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.bphit is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.enable is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.aindex is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.ahbactive is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hsel is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hmastlock is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hmaster is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hwdata is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hburst is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hsize is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.htrans is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hwrite is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.haddr is undriven | ||||
Post processing for gaisler.dsu3x.rtl | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":158:13:158:16|rhin.irq is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.break is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbwr is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg2.write is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg2.read is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg1.write is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg1.read is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.delaycnt is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.dcnten is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.bphit2 is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.bphit is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.enable is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.aindex is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.ahbactive is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.hsel is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.hmastlock is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hmaster is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hmaster is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hmaster is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.hmaster is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 30 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 31 of signal tr.hwdata is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hburst is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hburst is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hburst is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hsize is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hsize is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hsize is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.htrans is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.htrans is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.hwrite is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 30 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 31 of signal tr.haddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 0 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 1 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 2 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 3 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 4 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 5 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 6 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 7 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 8 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 9 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 10 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 11 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 12 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 13 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 14 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 15 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 16 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 17 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 18 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 19 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 20 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 21 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 22 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 23 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 24 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 25 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 26 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 27 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 28 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 29 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 30 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 31 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 32 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 33 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 34 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 35 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 36 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 37 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 38 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 39 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 40 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 41 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 42 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 43 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 44 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 45 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 46 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 47 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 48 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 49 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 50 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 51 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 52 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 53 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 54 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 55 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 56 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 57 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 58 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 59 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 60 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 61 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 62 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 63 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 64 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 65 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 66 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 67 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 68 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 69 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 70 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 71 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 72 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 73 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 74 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 75 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 76 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 77 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 78 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 79 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 80 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 81 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 82 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 83 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 84 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 85 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 86 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 87 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 88 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 89 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 90 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 91 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 92 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 93 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 94 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 95 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 96 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 97 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 98 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 99 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 100 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 101 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 102 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 103 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 104 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 105 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 106 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 107 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 108 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 109 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 110 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 111 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 112 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 113 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 114 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 115 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 116 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 117 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 118 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 119 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 120 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 121 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 122 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 123 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 124 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 125 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 126 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 127 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Pruning Register bit 1 of r.slv.haddr(24 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Pruning Register bit 0 of r.slv.haddr(24 downto 0) | ||||
Post processing for gaisler.dsu3.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":158:7:158:12|Synthesizing gaisler.leon3s.rtl | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Signal tbo.data is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":241:7:241:9|Signal rd1 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":241:12:241:14|Signal rd2 is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":241:17:241:18|Signal wd is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":37:7:37:14|Synthesizing gaisler.cachemem.rtl | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":127:9:127:17|Signal ildataout is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":148:19:148:26|Signal ldataout is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":34:7:34:13|Synthesizing techmap.syncram.rtl | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":49:9:49:12|Signal rena is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":49:15:49:18|Signal wena is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":50:19:50:24|Signal databp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":50:27:50:34|Signal testdata is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":380:7:380:22|Synthesizing techmap.proasic3_syncram.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":178:7:178:25|Synthesizing techmap.proasic3_syncram_dp.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":33:7:33:21|Synthesizing techmap.proasic3_ram4k9.rtl | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":77:7:77:8|Bit 9 of signal qa is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":77:11:77:12|Bit 9 of signal qb is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":46:12:46:17|Synthesizing techmap.ram4k9.syn_black_box | ||||
Post processing for techmap.ram4k9.syn_black_box | ||||
Post processing for techmap.proasic3_ram4k9.rtl | ||||
Post processing for techmap.proasic3_syncram_dp.rtl | ||||
Post processing for techmap.proasic3_syncram.rtl | ||||
Post processing for techmap.syncram.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":34:7:34:13|Synthesizing techmap.syncram.rtl | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":49:9:49:12|Signal rena is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":49:15:49:18|Signal wena is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":50:19:50:24|Signal databp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":50:27:50:34|Signal testdata is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":380:7:380:22|Synthesizing techmap.proasic3_syncram.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":274:7:274:25|Synthesizing techmap.proasic3_syncram_2p.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":120:7:120:24|Synthesizing techmap.proasic3_ram512x18.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":132:12:132:20|Synthesizing techmap.ram512x18.syn_black_box | ||||
Post processing for techmap.ram512x18.syn_black_box | ||||
Post processing for techmap.proasic3_ram512x18.rtl | ||||
Post processing for techmap.proasic3_syncram_2p.rtl | ||||
Post processing for techmap.proasic3_syncram.rtl | ||||
Post processing for techmap.syncram.rtl | ||||
Post processing for gaisler.cachemem.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\regfile_3p.vhd":32:7:32:16|Synthesizing techmap.regfile_3p.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":35:7:35:16|Synthesizing techmap.syncram_2p.rtl | ||||
@W: CD434 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":107:36:107:41|Signal testin in the sensitivity list is not used in the process | ||||
@W: CD729 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":199:4:199:5|Component declaration has 3 generics but entity declares only 2 generics | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:7:58:12|Signal databp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:15:58:22|Signal testdata is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":274:7:274:25|Synthesizing techmap.proasic3_syncram_2p.rtl | ||||
Post processing for techmap.proasic3_syncram_2p.rtl | ||||
Post processing for techmap.syncram_2p.rtl | ||||
Post processing for techmap.regfile_3p.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\proc3.vhd":43:7:43:11|Synthesizing gaisler.proc3.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_cache.vhd":39:7:39:15|Synthesizing gaisler.mmu_cache.rtl | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":40:7:40:16|Synthesizing gaisler.mmu_acache.rtl | ||||
@W: CD434 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":100:57:100:62|Signal hclken in the sensitivity list is not used in the process | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":96:7:96:8|Signal r2.hclken2 is undriven | ||||
Post processing for gaisler.mmu_acache.rtl | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":96:7:96:8|r2.hclken2 is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 0 of signal mcdo.par is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 1 of signal mcdo.par is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 2 of signal mcdo.par is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 3 of signal mcdo.par is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 0 of signal mcio.par is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 1 of signal mcio.par is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 2 of signal mcio.par is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 3 of signal mcio.par is floating - a simulation mismatch is possible | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":41:7:41:16|Synthesizing gaisler.mmu_dcache.rtl | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache | ||||
@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":131:16:131:17|Using onehot encoding for type dstatetype (idle="100000000") | ||||
@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":118:15:118:16|Using onehot encoding for type rdatatype (dtag="100000000") | ||||
@W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1061:4:1061:17|OTHERS clause is not synthesized | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Signal rh.snmiss is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Signal rh.hitaddr is undriven | ||||
Post processing for gaisler.mmu_dcache.rtl | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|rh.snmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 0 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 1 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 2 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 3 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 4 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 5 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 6 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 7 of signal rh.hitaddr is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.sdiag is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.sdiag is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.sdiag is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.sdiag is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|dcrami.spar is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 4 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 5 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 6 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 7 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 8 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 9 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 10 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 11 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 12 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 13 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 14 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 15 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 16 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 17 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 18 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 19 of signal dcrami.faddress is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|dco.cache is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 0 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 1 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 2 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 3 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.cache is always 1, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.cctrl.dsnoop is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.e is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.nf is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.pso is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.tlbdis is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.bar(0) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.bar(1) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.pagesize(0) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.pagesize(1) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(0) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(1) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(2) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(3) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(4) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(5) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(6) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(7) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(0) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(1) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(2) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(3) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(4) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(5) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(6) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(7) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(8) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(9) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(10) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(11) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(12) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(13) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(14) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(15) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(16) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(17) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(18) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(19) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(20) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(21) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(22) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(23) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(24) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(25) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(26) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(27) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(28) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(29) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.lock is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.flush_op is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.trans_op is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.dsuset(0) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.lrr is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.ilramen is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.ready is always 0, optimizing ... | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":37:7:37:16|Synthesizing gaisler.mmu_icache.rtl | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":162:16:162:17|Using sequential encoding for type istatetype | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":94:15:94:16|Using sequential encoding for type rdatatype | ||||
@W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":474:4:474:17|OTHERS clause is not synthesized | ||||
Post processing for gaisler.mmu_icache.rtl | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.dpar is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.dpar is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.dpar is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.dpar is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_0 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_1 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_2 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_3 is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.mhold is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.chold is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.tmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.cmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflushtyp | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflushaddr(31 downto 12) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflushr | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflush | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.diagset(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.setrepl(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.rndcnt(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.flush3 | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.lock is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.trans_op is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.lrr is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.cache is always 1, optimizing ... | ||||
Post processing for gaisler.mmu_cache.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":42:7:42:9|Synthesizing gaisler.iu3.rtl | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":242:23:242:24|Using sequential encoding for type exception_state | ||||
@N: CD364 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2808:4:2808:4|Removed redundant assignment | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2349:9:2349:17|Signal cpu_index is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2350:9:2350:15|Signal disasen is undriven | ||||
Post processing for gaisler.iu3.rtl | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.su is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.wbhold is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.mhold is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.chold is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.tmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.cmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.mhold is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.chold is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.tmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.cmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.bpmiss is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 0 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 1 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 2 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 3 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 4 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 5 of signal dbgo.optype is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.fcnt is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":78:4:78:7|irqo.fpen is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":73:4:73:6|dci.flushl is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":71:4:71:6|ici.pnull is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":3026:6:3026:7|Pruning Register dsur.tbufcnt(5 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.w.except | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.w.wreg | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.w.wa(6 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.mac | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.asi(7 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.dsuen | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.lock | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.write | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.read | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.enaddr | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.m.casaz | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.m.mul | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.m.divz | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.e.mul | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldchkex | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldchkra | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldcheck2 | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldcheck1 | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.d.divrdy | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.divstart is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.mulstart is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.w.s.ec is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.w.s.ef is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(0) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(1) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(2) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(3) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(4) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(5) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.x.npc(2) is always 0, optimizing ... | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register bit 2 of r.x.npc(2 downto 0) | ||||
Post processing for gaisler.proc3.rtl | ||||
Post processing for gaisler.leon3s.rtl | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 0 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 1 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 2 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 3 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 4 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 5 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 6 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 7 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 8 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 9 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 10 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 11 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 12 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 13 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 14 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 15 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 16 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 17 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 18 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 19 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 20 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 21 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 22 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 23 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 24 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 25 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 26 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 27 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 28 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 29 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 30 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 31 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 32 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 33 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 34 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 35 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 36 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 37 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 38 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 39 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 40 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 41 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 42 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 43 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 44 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 45 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 46 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 47 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 48 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 49 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 50 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 51 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 52 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 53 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 54 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 55 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 56 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 57 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 58 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 59 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 60 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 61 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 62 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 63 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 64 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 65 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 66 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 67 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 68 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 69 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 70 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 71 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 72 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 73 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 74 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 75 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 76 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 77 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 78 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 79 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 80 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 81 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 82 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 83 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 84 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 85 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 86 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 87 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 88 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 89 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 90 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 91 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 92 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 93 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 94 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 95 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 96 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 97 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 98 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 99 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 100 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 101 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 102 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 103 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 104 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 105 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 106 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 107 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 108 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 109 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 110 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 111 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 112 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 113 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 114 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 115 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 116 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 117 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 118 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 119 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 120 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 121 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 122 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 123 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 124 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 125 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 126 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 127 of signal tbo.data is floating - a simulation mismatch is possible | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 0 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 1 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 2 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 3 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 4 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 5 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 6 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 7 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 8 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 9 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 10 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 11 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 12 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 13 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 14 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 15 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 16 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 17 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 18 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 19 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 20 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 21 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 22 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 23 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 24 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 25 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 26 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 27 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 28 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 29 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 30 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 31 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 32 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 33 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 34 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 35 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 36 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 37 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 38 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 39 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 40 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 41 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 42 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 43 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 44 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 45 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 46 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 47 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 48 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 49 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 50 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 51 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 52 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 53 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 54 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 55 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 56 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 57 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 58 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 59 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 60 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 61 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 62 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 63 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 64 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 65 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 66 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 67 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 68 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 69 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 70 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 71 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 72 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 73 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 74 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 75 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 76 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 77 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 78 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 79 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 80 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 81 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 82 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 83 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 84 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 85 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 86 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 87 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 88 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 89 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 90 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 91 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 92 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 93 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 94 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 95 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 96 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 97 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 98 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 99 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 100 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 101 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 102 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 103 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 104 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 105 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 106 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 107 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 108 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 109 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 110 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 111 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 112 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 113 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 114 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 115 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 116 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 117 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 118 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 119 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 120 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 121 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 122 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 123 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 124 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 125 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 126 of input tbo of instance p0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 127 of input tbo of instance p0 is floating | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":32:7:32:12|Synthesizing techmap.clkgen.struct | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":67:7:67:10|Signal lock is undriven | ||||
Post processing for techmap.clkgen.struct | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":62:4:62:7|clkc is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":61:4:61:7|clkb is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":60:4:60:9|clk2xu is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":58:4:58:8|clk4x is not assigned a value (floating) - a simulation mismatch is possible | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\clkpad.vhd":32:7:32:12|Synthesizing techmap.clkpad.rtl | ||||
Post processing for techmap.clkpad.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\rstgen.vhd":29:7:29:12|Synthesizing gaisler.rstgen.rtl | ||||
Post processing for gaisler.rstgen.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":35:7:35:15|Synthesizing lpp.apb_delay.ar_apb_delay | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\TimerDelay.vhd":6:7:6:16|Synthesizing lpp.timerdelay.ar_timerdelay | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\TimerDelay.vhd":20:11:20:12|Using sequential encoding for type state | ||||
Post processing for lpp.timerdelay.ar_timerdelay | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\TimerDelay.vhd":37:8:37:9|Feedback mux created for signal compt[25:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
Post processing for lpp.apb_delay.ar_apb_delay | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 0 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 1 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 2 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 3 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 4 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 5 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 6 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 7 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 8 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 9 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 10 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 11 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 12 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 13 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 14 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 15 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 16 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 17 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 18 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 19 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 20 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 21 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 22 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 23 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 24 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 25 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 26 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 27 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 28 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 29 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 30 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":46:4:46:7|Bit 31 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Feedback mux created for signal Rdata[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":36:7:36:14|Synthesizing lpp.apb_uart.ar_apb_uart | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":78:7:78:13|Signal temp_nd is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\UART.vhd":32:7:32:10|Synthesizing lpp.uart.ar_uart | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\Shift_REG.vhd":31:7:31:15|Synthesizing lpp.shift_reg.ar_shift_reg | ||||
Post processing for lpp.shift_reg.ar_shift_reg | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\BaudGen.vhd":30:7:30:13|Synthesizing lpp.baudgen.ar_baudgen | ||||
Post processing for lpp.baudgen.ar_baudgen | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\BaudGen.vhd":58:4:58:5|Feedback mux created for signal RX_reg. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
Post processing for lpp.uart.ar_uart | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\UART.vhd":81:4:81:5|Feedback mux created for signal RDATA[7:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\UART.vhd":81:4:81:5|Feedback mux created for signal Taken_reg. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
Post processing for lpp.apb_uart.ar_apb_uart | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 0 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 1 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 2 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 3 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 4 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 5 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 6 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 7 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 8 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 9 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 10 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 11 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 12 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 13 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 14 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 15 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 16 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 17 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 18 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 19 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 20 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 21 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 22 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 23 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 24 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 25 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 26 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 27 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 28 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 29 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 30 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":48:4:48:7|Bit 31 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Feedback mux created for signal Rdata[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Feedback mux created for signal Rec.UART_Cfg[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Feedback mux created for signal ACK. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Register bit Rdata(12) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Register bit Rdata(16) is always 0, optimizing ... | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 16 of Rdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 12 of Rdata(31 downto 0) | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":38:7:38:14|Synthesizing lpp.apb_fifo.ar_apb_fifo | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":110:13:110:14|Using sequential encoding for type state_t | ||||
@W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":255:16:255:29|OTHERS clause is not synthesized | ||||
@W: CG296 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":225:0:225:6|Incomplete sensitivity list - assuming completeness | ||||
@W: CG290 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":232:39:232:44|Referenced variable sempty is not in sensitivity list | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 12 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 13 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 14 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 15 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 28 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 29 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 30 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 31 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 6 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 7 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 24 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 25 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 26 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 27 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 28 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 29 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 30 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 31 of signal fifo_id is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":30:7:30:14|Synthesizing lpp.lpp_fifo.ar_lpp_fifo | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":35:7:35:16|Synthesizing techmap.syncram_2p.rtl | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:7:58:12|Signal databp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:15:58:22|Signal testdata is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":274:7:274:25|Synthesizing techmap.proasic3_syncram_2p.rtl | ||||
Post processing for techmap.proasic3_syncram_2p.rtl | ||||
Post processing for techmap.syncram_2p.rtl | ||||
Post processing for lpp.lpp_fifo.ar_lpp_fifo | ||||
Post processing for lpp.apb_fifo.ar_apb_fifo | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 0 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 1 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 2 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 3 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 4 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 5 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 6 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 7 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 8 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 9 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 10 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 11 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 12 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 13 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 14 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 15 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 16 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 17 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 18 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 19 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 20 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 21 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 22 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 23 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 24 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 25 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 26 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 27 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 28 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 29 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 30 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 31 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 0 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 1 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 2 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 3 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 4 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 5 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 6 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 7 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 8 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 9 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 10 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 11 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 12 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 13 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 14 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 15 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(31) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(30) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(29) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(28) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(27) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(26) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(25) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(24) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(15) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(14) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(13) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(12) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(7) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(6) | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":236:12:236:15|Feedback mux created for signal sEmpty_d[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[1:1]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[2:2]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[3:3]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[4:4]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[5:5]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[8:8]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[9:9]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[10:10]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[11:11]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[16:16]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[17:17]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[18:18]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[19:19]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[20:20]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[21:21]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[22:22]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[23:23]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[6:6]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[7:7]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[12:12]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[13:13]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[14:14]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[15:15]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[24:24]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[25:25]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[26:26]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[27:27]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[28:28]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[29:29]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[30:30]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(6), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(7), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(12), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(13), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(14), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(15), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(24), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(25), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(26), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(27), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(28), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(29), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(30), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(31), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Register bit PRdata_cl(31) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Register bit PRdata(18) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Register bit PRdata(17) is always 0, optimizing ... | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":38:7:38:14|Synthesizing lpp.apb_fifo.ar_apb_fifo | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":110:13:110:14|Using sequential encoding for type state_t | ||||
@W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":255:16:255:29|OTHERS clause is not synthesized | ||||
@W: CG296 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":225:0:225:6|Incomplete sensitivity list - assuming completeness | ||||
@W: CG290 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":232:39:232:44|Referenced variable sempty is not in sensitivity list | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 12 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 13 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 14 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 15 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 28 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 29 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 30 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 31 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 6 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 7 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 24 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 25 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 26 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 27 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 28 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 29 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 30 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 31 of signal fifo_id is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":30:7:30:14|Synthesizing lpp.lpp_fifo.ar_lpp_fifo | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":35:7:35:16|Synthesizing techmap.syncram_2p.rtl | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:7:58:12|Signal databp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:15:58:22|Signal testdata is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":274:7:274:25|Synthesizing techmap.proasic3_syncram_2p.rtl | ||||
Post processing for techmap.proasic3_syncram_2p.rtl | ||||
Post processing for techmap.syncram_2p.rtl | ||||
Post processing for lpp.lpp_fifo.ar_lpp_fifo | ||||
Post processing for lpp.apb_fifo.ar_apb_fifo | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 0 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 1 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 2 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 3 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 4 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 5 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 6 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 7 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 8 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 9 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 10 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 11 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 12 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 13 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 14 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 15 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 16 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 17 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 18 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 19 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 20 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 21 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 22 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 23 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 24 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 25 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 26 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 27 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 28 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 29 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 30 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 31 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 0 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 1 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 2 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 3 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 4 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 5 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 6 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 7 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 8 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 9 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 10 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 11 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 12 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 13 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 14 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 15 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 16 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 17 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 18 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 19 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 20 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 21 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 22 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 23 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 24 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 25 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 26 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 27 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 28 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 29 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 30 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 31 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Pruning Register sWen_APB(0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":182:8:182:9|Pruning Register Rec_0.FIFO_Wdata(31 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(31) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(30) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(29) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(28) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(27) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(26) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(25) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(24) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(15) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(14) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(13) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(12) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(7) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(6) | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":236:12:236:15|Feedback mux created for signal sEmpty_d[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[1:1]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[2:2]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[3:3]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[4:4]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[5:5]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[8:8]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[9:9]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[10:10]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[11:11]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[16:16]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[17:17]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[18:18]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[19:19]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[20:20]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[21:21]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[22:22]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[23:23]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[6:6]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[7:7]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[12:12]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[13:13]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[14:14]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[15:15]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[24:24]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[25:25]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[26:26]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[27:27]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[28:28]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[29:29]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[30:30]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Feedback mux created for signal PRdata[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(6), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(7), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(12), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(13), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(14), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(15), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(24), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(25), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(26), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(27), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(28), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(29), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(30), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(31), probably caused by a missing assignment in an if or case stmt | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd":27:7:27:20|Synthesizing lpp.spectralmatrix.ar_spectralmatrix | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\GetResult.vhd":26:7:26:15|Synthesizing lpp.getresult.ar_getresult | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\GetResult.vhd":47:11:47:12|Using sequential encoding for type state | ||||
Post processing for lpp.getresult.ar_getresult | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\Matrix.vhd":29:7:29:12|Synthesizing lpp.matrix.ar_matrix | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\ALU_v2.vhd":29:7:29:12|Synthesizing lpp.alu_v2.ar_alu_v2 | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\MAC_v2.vhd":30:7:30:12|Synthesizing lpp.mac_v2.ar_mac_v2 | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\MAC_v2.vhd":74:7:74:22|Bit 2 of signal mac_mul_add_2c_d is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\MAC_v2.vhd":74:7:74:22|Bit 3 of signal mac_mul_add_2c_d is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\MAC_MUX2.vhd":30:7:30:14|Synthesizing lpp.mac_mux2.ar_mac_mux2 | ||||
Post processing for lpp.mac_mux2.ar_mac_mux2 | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\MAC_MUX.vhd":30:7:30:13|Synthesizing lpp.mac_mux.ar_mac_mux | ||||
Post processing for lpp.mac_mux.ar_mac_mux | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\MAC_REG.vhd":30:7:30:13|Synthesizing lpp.mac_reg.ar_mac_reg | ||||
Post processing for lpp.mac_reg.ar_mac_reg | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\MAC_REG.vhd":30:7:30:13|Synthesizing lpp.mac_reg.ar_mac_reg | ||||
Post processing for lpp.mac_reg.ar_mac_reg | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\MAC_REG.vhd":30:7:30:13|Synthesizing lpp.mac_reg.ar_mac_reg | ||||
Post processing for lpp.mac_reg.ar_mac_reg | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\MAC_REG.vhd":30:7:30:13|Synthesizing lpp.mac_reg.ar_mac_reg | ||||
Post processing for lpp.mac_reg.ar_mac_reg | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\TwoComplementer.vhd":28:7:28:21|Synthesizing lpp.twocomplementer.ar_twocomplementer | ||||
Post processing for lpp.twocomplementer.ar_twocomplementer | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\Adder.vhd":30:7:30:11|Synthesizing lpp.adder.ar_adder | ||||
Post processing for lpp.adder.ar_adder | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\Multiplier.vhd":31:7:31:16|Synthesizing lpp.multiplier.ar_multiplier | ||||
Post processing for lpp.multiplier.ar_multiplier | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd":32:7:32:19|Synthesizing lpp.mac_controler.ar_mac_controler | ||||
Post processing for lpp.mac_controler.ar_mac_controler | ||||
Post processing for lpp.mac_v2.ar_mac_v2 | ||||
Post processing for lpp.alu_v2.ar_alu_v2 | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":28:7:28:16|Synthesizing lpp.alu_driver.ar_alu_driver | ||||
@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":61:10:61:11|Using onehot encoding for type etat (ex="1000000000") | ||||
Post processing for lpp.alu_driver.ar_alu_driver | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":69:8:69:9|Feedback mux created for signal OP2[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":69:8:69:9|Feedback mux created for signal OP1[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":69:8:69:9|Feedback mux created for signal OP2re[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":69:8:69:9|Feedback mux created for signal OP2im[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":69:8:69:9|Feedback mux created for signal OP1re[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":69:8:69:9|Feedback mux created for signal OP1im[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
Post processing for lpp.matrix.ar_matrix | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\DriveInputs.vhd":26:7:26:17|Synthesizing lpp.driveinputs.ar_driveinputs | ||||
@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\DriveInputs.vhd":43:11:43:12|Using onehot encoding for type state (stx="1000000") | ||||
Post processing for lpp.driveinputs.ar_driveinputs | ||||
Post processing for lpp.spectralmatrix.ar_spectralmatrix | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\TopMatrix_PDR.vhd":26:7:26:19|Synthesizing lpp.topmatrix_pdr.ar_topmatrix_pdr | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\TopMatrix_PDR.vhd":46:11:46:12|Using sequential encoding for type state | ||||
Post processing for lpp.topmatrix_pdr.ar_topmatrix_pdr | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\lppFIFOxN.vhd":30:7:30:15|Synthesizing lpp.lppfifoxn.ar_lppfifoxn | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":30:7:30:14|Synthesizing lpp.lpp_fifo.ar_lpp_fifo | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":35:7:35:16|Synthesizing techmap.syncram_2p.rtl | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:7:58:12|Signal databp is undriven | ||||
@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":58:15:58:22|Signal testdata is undriven | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":113:7:113:24|Synthesizing techmap.generic_syncram_2p.behav | ||||
Post processing for techmap.generic_syncram_2p.behav | ||||
@N: CL134 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Found RAM rfd, depth=256, width=16 | ||||
Post processing for techmap.syncram_2p.rtl | ||||
Post processing for lpp.lpp_fifo.ar_lpp_fifo | ||||
Post processing for lpp.lppfifoxn.ar_lppfifoxn | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd":26:7:26:16|Synthesizing lpp.linker_fft.ar_linker | ||||
@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd":48:10:48:11|Using onehot encoding for type etat (ex="10000") | ||||
Post processing for lpp.linker_fft.ar_linker | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd":62:8:62:9|Feedback mux created for signal DataTmp[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd":62:8:62:9|Feedback mux created for signal sReady. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd":33:7:33:13|Synthesizing lpp.corefft.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":592:7:592:15|Synthesizing lpp.autoscale.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":100:7:100:16|Synthesizing lpp.edgedetect.translated | ||||
Post processing for lpp.edgedetect.translated | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":127:4:127:5|Pruning Register in_pipe | ||||
Post processing for lpp.autoscale.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":450:7:450:13|Synthesizing lpp.outbuff.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":561:7:561:13|Synthesizing lpp.wrapram.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actram.vhd":8:7:8:12|Synthesizing lpp.actram.def_arch | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2967:10:2967:18|Synthesizing proasic3.ram512x18.syn_black_box | ||||
Post processing for proasic3.ram512x18.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":1782:10:1782:12|Synthesizing proasic3.gnd.syn_black_box | ||||
Post processing for proasic3.gnd.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2722:10:2722:12|Synthesizing proasic3.vcc.syn_black_box | ||||
Post processing for proasic3.vcc.syn_black_box | ||||
Post processing for lpp.actram.def_arch | ||||
Post processing for lpp.wrapram.rtl | ||||
Post processing for lpp.outbuff.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":21:7:21:12|Synthesizing lpp.switch.translated | ||||
Post processing for lpp.switch.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":517:7:517:13|Synthesizing lpp.twidlut.translated | ||||
Post processing for lpp.twidlut.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\twiddle.vhd":22:7:22:13|Synthesizing lpp.twiddle.translated | ||||
Post processing for lpp.twiddle.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":183:7:183:11|Synthesizing lpp.bfly2.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":118:7:118:10|Synthesizing lpp.agen.rtl | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":72:7:72:14|Synthesizing lpp.kitrndup.rtl | ||||
Post processing for lpp.kitrndup.rtl | ||||
@W: CL265 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":94:4:94:5|Pruning bit 0 of int_outp(16 downto 0) - not in use ... | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":8:7:8:11|Synthesizing lpp.actar.def_arch | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":14:10:14:13|Synthesizing proasic3.and2.syn_black_box | ||||
Post processing for proasic3.and2.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2825:10:2825:13|Synthesizing proasic3.xor3.syn_black_box | ||||
Post processing for proasic3.xor3.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2093:10:2093:13|Synthesizing proasic3.nor2.syn_black_box | ||||
Post processing for proasic3.nor2.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":137:10:137:12|Synthesizing proasic3.ao1.syn_black_box | ||||
Post processing for proasic3.ao1.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":1996:10:1996:12|Synthesizing proasic3.mx2.syn_black_box | ||||
Post processing for proasic3.mx2.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2817:10:2817:13|Synthesizing proasic3.xor2.syn_black_box | ||||
Post processing for proasic3.xor2.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":1374:10:1374:13|Synthesizing proasic3.dfn1.syn_black_box | ||||
Post processing for proasic3.dfn1.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":38:10:38:13|Synthesizing proasic3.and3.syn_black_box | ||||
Post processing for proasic3.and3.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":191:10:191:13|Synthesizing proasic3.aoi1.syn_black_box | ||||
Post processing for proasic3.aoi1.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":1942:10:1942:13|Synthesizing proasic3.maj3.syn_black_box | ||||
Post processing for proasic3.maj3.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2852:10:2852:13|Synthesizing proasic3.buff.syn_black_box | ||||
Post processing for proasic3.buff.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2222:10:2222:12|Synthesizing proasic3.or3.syn_black_box | ||||
Post processing for proasic3.or3.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":2782:10:2782:14|Synthesizing proasic3.xnor2.syn_black_box | ||||
Post processing for proasic3.xnor2.syn_black_box | ||||
@N: CD630 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd":22:10:22:14|Synthesizing proasic3.and2a.syn_black_box | ||||
Post processing for proasic3.and2a.syn_black_box | ||||
Post processing for lpp.actar.def_arch | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":3405:4:3405:10|Pruning instance AND2_97 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":3322:4:3322:10|Pruning instance AND2_84 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":3270:4:3270:10|Pruning instance XOR2_77 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":3198:4:3198:10|Pruning instance AND2_41 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":3019:4:3019:11|Pruning instance AND2_152 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2971:4:2971:9|Pruning instance AO1_49 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2926:4:2926:11|Pruning instance AND2_200 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2885:4:2885:11|Pruning instance AND2_242 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2856:4:2856:11|Pruning instance AND2_130 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2837:4:2837:11|Pruning instance AND2_234 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2806:4:2806:11|Pruning instance AND2_117 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2750:4:2750:11|Pruning instance AND2_159 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2696:4:2696:10|Pruning instance AND2_89 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2539:4:2539:11|Pruning instance AND2_235 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2526:4:2526:10|Pruning instance AND2_59 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2421:4:2421:9|Pruning instance AO1_81 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2329:4:2329:10|Pruning instance AND2_15 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2304:4:2304:11|Pruning instance AND2_213 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2247:4:2247:9|Pruning instance AO1_32 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2122:4:2122:10|Pruning instance AND2_34 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2070:4:2070:11|Pruning instance XOR2_111 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2066:4:2066:11|Pruning instance AND2_228 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1976:4:1976:11|Pruning instance AND2_220 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1875:4:1875:10|Pruning instance AND2_58 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1830:4:1830:10|Pruning instance AND2_95 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1759:4:1759:11|Pruning instance AND2_231 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1704:4:1704:11|Pruning instance AND2_100 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1687:4:1687:9|Pruning instance AND2_7 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1678:4:1678:9|Pruning instance AND2_1 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1651:4:1651:11|Pruning instance AND2_105 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1525:4:1525:11|Pruning instance AND2_172 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1489:4:1489:11|Pruning instance AND2_195 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1430:4:1430:10|Pruning instance AND2_39 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":1367:4:1367:11|Pruning instance AND2_160 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":829:4:829:9|Pruning instance AO1_56 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":765:4:765:11|Pruning instance AND2_250 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":709:4:709:10|Pruning instance AND2_99 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":686:4:686:11|Pruning instance AND2_125 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":684:4:684:11|Pruning instance AND2_174 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":670:4:670:10|Pruning instance AND2_53 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":624:4:624:10|Pruning instance AND2_60 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":606:4:606:11|Pruning instance AND2_153 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":479:4:479:10|Pruning instance AND2_69 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":435:4:435:11|Pruning instance AND2_248 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":411:4:411:10|Pruning instance AND2_49 - not in use ... | ||||
@W: CL168 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":380:4:380:11|Pruning instance AND2_225 - not in use ... | ||||
Post processing for lpp.agen.rtl | ||||
Post processing for lpp.bfly2.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":383:7:383:16|Synthesizing lpp.pipobuffer.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":308:7:308:14|Synthesizing lpp.inbuffer.translated | ||||
Post processing for lpp.inbuffer.translated | ||||
Post processing for lpp.pipobuffer.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":503:7:503:12|Synthesizing lpp.sm_top.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":410:7:410:13|Synthesizing lpp.outbufa.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":23:7:23:13|Synthesizing lpp.counter.translated | ||||
Post processing for lpp.counter.translated | ||||
Post processing for lpp.outbufa.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":282:7:282:16|Synthesizing lpp.inbuf_ffta.translated | ||||
Post processing for lpp.inbuf_ffta.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":356:7:356:16|Synthesizing lpp.twid_wamod.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":69:7:69:14|Synthesizing lpp.bcounter.translated | ||||
Post processing for lpp.bcounter.translated | ||||
Post processing for lpp.twid_wamod.translated | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":393:4:393:5|Feedback mux created for signal rstAfterInit_int. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":393:4:393:5|Feedback mux created for signal preRstAfterInit. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":22:7:22:13|Synthesizing lpp.twid_ra.translated | ||||
Post processing for lpp.twid_ra.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":193:7:193:15|Synthesizing lpp.inbuf_lda.translated | ||||
Post processing for lpp.inbuf_lda.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":148:7:148:16|Synthesizing lpp.wrffttimer.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":23:7:23:13|Synthesizing lpp.counter.translated | ||||
Post processing for lpp.counter.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":23:7:23:13|Synthesizing lpp.counter.translated | ||||
Post processing for lpp.counter.translated | ||||
Post processing for lpp.wrffttimer.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":67:7:67:16|Synthesizing lpp.rdffttimer.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":23:7:23:13|Synthesizing lpp.counter.translated | ||||
Post processing for lpp.counter.translated | ||||
Post processing for lpp.rdffttimer.translated | ||||
Post processing for lpp.sm_top.translated | ||||
Post processing for lpp.corefft.translated | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":26:7:26:16|Synthesizing lpp.driver_fft.ar_driver | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":47:10:47:11|Using sequential encoding for type etat | ||||
Post processing for lpp.driver_fft.ar_driver | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|Feedback mux created for signal Data_re[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(0) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(1) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(2) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(3) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(4) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(5) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(6) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(7) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(8) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(9) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(10) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(11) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(12) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(13) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(14) assign '0', register removed by optimization | ||||
@W: CL111 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|All reachable assignments to Data_im(15) assign '0', register removed by optimization | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":38:7:38:14|Synthesizing lpp.apb_fifo.ar_apb_fifo | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":110:13:110:14|Using sequential encoding for type state_t | ||||
@W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":255:16:255:29|OTHERS clause is not synthesized | ||||
@W: CG296 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":225:0:225:6|Incomplete sensitivity list - assuming completeness | ||||
@W: CG290 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":232:39:232:44|Referenced variable sempty is not in sensitivity list | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 12 of signal Rec_4.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 13 of signal Rec_4.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 14 of signal Rec_4.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 15 of signal Rec_4.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 28 of signal Rec_4.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 29 of signal Rec_4.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 30 of signal Rec_4.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 31 of signal Rec_4.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 12 of signal Rec_3.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 13 of signal Rec_3.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 14 of signal Rec_3.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 15 of signal Rec_3.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 28 of signal Rec_3.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 29 of signal Rec_3.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 30 of signal Rec_3.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 31 of signal Rec_3.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 12 of signal Rec_2.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 13 of signal Rec_2.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 14 of signal Rec_2.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 15 of signal Rec_2.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 28 of signal Rec_2.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 29 of signal Rec_2.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 30 of signal Rec_2.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 31 of signal Rec_2.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 12 of signal Rec_1.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 13 of signal Rec_1.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 14 of signal Rec_1.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 15 of signal Rec_1.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 28 of signal Rec_1.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 29 of signal Rec_1.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 30 of signal Rec_1.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 31 of signal Rec_1.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 12 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 13 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 14 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 15 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 28 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 29 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 30 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":90:7:90:9|Bit 31 of signal Rec_0.fifo_ctrl is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 6 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 7 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 24 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 25 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 26 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 27 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 28 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 29 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 30 of signal fifo_id is undriven | ||||
@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":92:7:92:13|Bit 31 of signal fifo_id is undriven | ||||
Post processing for lpp.apb_fifo.ar_apb_fifo | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 0 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 1 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 2 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 3 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 4 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 5 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 6 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 7 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 8 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 9 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 10 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 11 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 12 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 13 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 14 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 15 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 16 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 17 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 18 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 19 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 20 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 21 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 22 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 23 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 24 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 25 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 26 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 27 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 28 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 29 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 30 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":68:4:68:7|Bit 31 of signal apbo.pirq is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 0 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 1 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 2 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 3 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 4 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 5 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 6 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 7 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 8 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 9 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 10 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 11 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 12 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 13 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 14 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 15 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 16 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 17 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 18 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 19 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 20 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 21 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 22 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 23 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 24 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 25 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 26 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 27 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 28 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 29 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 30 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 31 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 32 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 33 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 34 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 35 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 36 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 37 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 38 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 39 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 40 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 41 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 42 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 43 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 44 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 45 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 46 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 47 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 48 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 49 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 50 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 51 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 52 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 53 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 54 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 55 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 56 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 57 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 58 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 59 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 60 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 61 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 62 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 63 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 64 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 65 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 66 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 67 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 68 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 69 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 70 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 71 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 72 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 73 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 74 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 75 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 76 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 77 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 78 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":63:4:63:8|Bit 79 of signal RDATA is floating - a simulation mismatch is possible | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Pruning Register Rec_4.FIFO_Wdata(15 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Pruning Register Rec_3.FIFO_Wdata(15 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Pruning Register Rec_2.FIFO_Wdata(15 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Pruning Register Rec_1.FIFO_Wdata(15 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":191:12:191:13|Pruning Register sWen_APB(4 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":182:8:182:9|Pruning Register Rec_0.FIFO_Wdata(15 downto 0) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(31) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(30) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(29) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(28) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(27) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(26) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(25) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(24) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(15) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(14) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(13) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(12) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(7) | ||||
@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":221:16:221:17|Pruning Register apbo.prdata_cl(6) | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":249:28:249:38|Feedback mux created for signal sEmpty_d[4:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[1:1]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[2:2]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[3:3]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[4:4]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[5:5]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[8:8]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[9:9]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[10:10]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[11:11]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[16:16]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[17:17]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[18:18]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[19:19]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[20:20]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[21:21]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[22:22]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[23:23]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[6:6]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[7:7]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[12:12]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[13:13]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[14:14]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[15:15]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[24:24]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[25:25]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[26:26]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[27:27]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[28:28]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[29:29]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[30:30]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata_cl[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Feedback mux created for signal PRdata[31:31]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(6), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(7), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(12), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(13), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(14), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(15), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(24), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(25), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(26), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(27), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(28), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(29), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(30), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata_e, probably caused by a missing assignment in an if or case stmt | ||||
@W: CL117 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":206:18:206:55|Latch generated from process for signal apbo.prdata(31), probably caused by a missing assignment in an if or case stmt | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Register bit PRdata_cl(31) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Register bit PRdata(18) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":193:24:193:25|Register bit PRdata(17) is always 0, optimizing ... | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_ad_Conv\WriteGen_ADC.vhd":26:7:26:18|Synthesizing lpp.writegen_adc.ar_wg | ||||
@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_ad_Conv\WriteGen_ADC.vhd":41:10:41:11|Using sequential encoding for type etat | ||||
Post processing for lpp.writegen_adc.ar_wg | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd":32:7:32:17|Synthesizing lpp.ad7688_drvr.ar_ad7688_drvr | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_spi_if.vhd":28:7:28:19|Synthesizing lpp.ad7688_spi_if.ar_ad7688_spi_if | ||||
Post processing for lpp.ad7688_spi_if.ar_ad7688_spi_if | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_spi_if.vhd":51:1:51:2|Feedback mux created for signal DataReady. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_spi_if.vhd":51:1:51:2|Feedback mux created for signal smpout_4[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_spi_if.vhd":51:1:51:2|Feedback mux created for signal smpout_3[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_spi_if.vhd":51:1:51:2|Feedback mux created for signal smpout_2[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_spi_if.vhd":51:1:51:2|Feedback mux created for signal smpout_1[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
@A:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_spi_if.vhd":51:1:51:2|Feedback mux created for signal smpout_0[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area | ||||
Post processing for lpp.ad7688_drvr.ar_ad7688_drvr | ||||
@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\Clk_divider.vhd":26:7:26:17|Synthesizing lpp.clk_divider.ar_clk_divider | ||||
Post processing for lpp.clk_divider.ar_clk_divider | ||||
Post processing for work.leon3mp.behavioral | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":172:7:172:18|Bit 0 of signal FifoIN_Empty is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":172:7:172:18|Bit 1 of signal FifoIN_Empty is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":172:7:172:18|Bit 2 of signal FifoIN_Empty is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":172:7:172:18|Bit 3 of signal FifoIN_Empty is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":172:7:172:18|Bit 4 of signal FifoIN_Empty is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":171:7:171:17|Bit 0 of signal FifoIN_Full is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":171:7:171:17|Bit 1 of signal FifoIN_Full is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":171:7:171:17|Bit 2 of signal FifoIN_Full is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":171:7:171:17|Bit 3 of signal FifoIN_Full is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":171:7:171:17|Bit 4 of signal FifoIN_Full is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 0 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 1 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 2 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 3 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 4 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 5 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 6 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 7 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 8 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 9 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 10 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 11 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 12 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 13 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 14 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 15 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 16 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 17 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 18 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 19 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 20 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 21 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 22 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 23 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 24 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 25 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 26 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 27 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 28 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 29 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 30 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 31 of signal gpioi.sig_en is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 0 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 1 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 2 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 3 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 4 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 5 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 6 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 7 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 8 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 9 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 10 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 11 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 12 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 13 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 14 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 15 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 16 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 17 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 18 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 19 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 20 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 21 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 22 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 23 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 24 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 25 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 26 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 27 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 28 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 29 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 30 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":159:7:159:11|Bit 31 of signal gpioi.sig_in is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":156:7:156:10|gpti.wdogen is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":150:7:150:9|wpo.wprothit is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|memi.edac is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 0 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 1 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 2 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 3 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 4 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 5 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 6 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 7 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 8 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 9 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 10 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 11 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 12 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 13 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 14 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 15 of signal memi.scb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 0 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 1 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 2 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 3 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 4 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 5 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 6 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 7 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 8 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 9 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 10 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 11 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 12 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 13 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 14 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 15 of signal memi.cb is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 0 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 1 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 2 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 3 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 4 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 5 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 6 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 7 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 8 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 9 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 10 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 11 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 12 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 13 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 14 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 15 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 16 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 17 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 18 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 19 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 20 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 21 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 22 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 23 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 24 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 25 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 26 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 27 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 28 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 29 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 30 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 31 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 32 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 33 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 34 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 35 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 36 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 37 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 38 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 39 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 40 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 41 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 42 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 43 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 44 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 45 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 46 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 47 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 48 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 49 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 50 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 51 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 52 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 53 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 54 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 55 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 56 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 57 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 58 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 59 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 60 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 61 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 62 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":148:7:148:10|Bit 63 of signal memi.sd is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":143:7:143:14|ahbuarti.extclk is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":143:7:143:14|ahbuarti.ctsn is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":133:7:133:9|Bit 0 of signal cgi.clksel is floating - a simulation mismatch is possible | ||||
@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":133:7:133:9|Bit 1 of signal cgi.clksel is floating - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":133:7:133:9|cgi.pllref is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":109:4:109:7|TEST is not assigned a value (floating) - a simulation mismatch is possible | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 32 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 33 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 34 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 35 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 36 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 37 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 38 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 39 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 40 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 41 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 42 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 43 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 44 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 45 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 46 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 47 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 48 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 49 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 50 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 51 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 52 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 53 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 54 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 55 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 56 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 57 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 58 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 59 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 60 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 61 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 62 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 63 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 64 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 65 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 66 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 67 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 68 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 69 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 70 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 71 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 72 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 73 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 74 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 75 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 76 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 77 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 78 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 79 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 80 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 81 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 82 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 83 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 84 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 85 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 86 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 87 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 88 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 89 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 90 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 91 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 92 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 93 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 94 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":559:4:559:10|Bit 95 of input gpioi of instance grgpio0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":544:4:544:8|Bit 1 of input uarti of instance uart1 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":544:4:544:8|Bit 2 of input uarti of instance uart1 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":528:4:528:9|Bit 2 of input gpti of instance timer0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":506:4:506:8|Bit 1 of input uarti of instance dcom0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":506:4:506:8|Bit 2 of input uarti of instance dcom0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 41 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 42 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 43 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 44 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 45 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 46 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 47 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 48 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 49 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 50 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 51 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 52 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 53 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 54 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 55 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 56 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 57 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 58 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 59 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 60 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 61 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 62 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 63 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 64 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 65 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 66 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 67 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 68 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 69 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 70 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 71 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 72 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 73 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 74 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 75 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 76 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 77 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 78 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 79 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 80 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 81 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 82 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 83 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 84 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 85 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 86 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 87 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 88 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 89 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 90 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 91 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 92 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 93 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 94 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 95 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 96 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 97 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 98 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 99 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 100 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 101 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 102 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 103 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 104 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 105 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 106 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 107 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 108 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 109 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 110 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 111 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 112 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 113 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 114 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 115 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 116 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 117 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 118 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 119 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 120 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 121 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 122 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 123 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 124 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 125 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 126 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 127 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 128 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 129 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 130 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 131 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 132 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 133 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 134 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 135 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 136 of input memi of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Bit 137 of input memi of instance memctrlr is floating | ||||
@W: CL167 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":469:4:469:11|Input wpo of instance memctrlr is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":406:2:406:8|Bit 0 of input cgi of instance clkgen0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":406:2:406:8|Bit 4 of input cgi of instance clkgen0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":406:2:406:8|Bit 5 of input cgi of instance clkgen0 is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 0 of input empty of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 1 of input empty of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 2 of input empty of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 3 of input empty of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 4 of input empty of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 0 of input full of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 1 of input full of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 2 of input full of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 3 of input full of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 4 of input full of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 0 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 1 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 2 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 3 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 4 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 5 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 6 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 7 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 8 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 9 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 10 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 11 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 12 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 13 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 14 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 15 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 16 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 17 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 18 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 19 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 20 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 21 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 22 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 23 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 24 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 25 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 26 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 27 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 28 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 29 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 30 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 31 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 32 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 33 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 34 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 35 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 36 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 37 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 38 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 39 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 40 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 41 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 42 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 43 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 44 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 45 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 46 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 47 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 48 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 49 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 50 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 51 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 52 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 53 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 54 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 55 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 56 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 57 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 58 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 59 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 60 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 61 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 62 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 63 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 64 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 65 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 66 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 67 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 68 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 69 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 70 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 71 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 72 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 73 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 74 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 75 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 76 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 77 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 78 of input data of instance DRIVE is floating | ||||
@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":305:4:305:8|Bit 79 of input data of instance DRIVE is floating | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_ad_Conv\WriteGen_ADC.vhd":50:8:50:9|Trying to extract state machine for register ect | ||||
Extracted state machine for register ect | ||||
State machine has 3 reachable states with original encodings of: | ||||
00 | ||||
01 | ||||
10 | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 117 to 52 of apbi(117 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bit 50 of apbi(117 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 15 to 10 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 8 to 0 of apbi(117 downto 0) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":56:4:56:7|Input rclk is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":59:4:59:6|Input REN is unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd":61:8:61:9|Trying to extract state machine for register ect | ||||
Extracted state machine for register ect | ||||
State machine has 3 reachable states with original encodings of: | ||||
00 | ||||
01 | ||||
11 | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd":413:13:413:17|Input clkEn is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":318:4:318:6|Input rEn is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":454:9:454:13|Input clkEn is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":105:9:105:13|Input clkEn is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd":597:15:597:24|Input ifo_loadOn is unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd":62:8:62:9|Trying to extract state machine for register ect | ||||
Extracted state machine for register ect | ||||
State machine has 5 reachable states with original encodings of: | ||||
00001 | ||||
00010 | ||||
00100 | ||||
01000 | ||||
10000 | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":120:4:120:7|Input rclk is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":41:4:41:10|Input renable is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":48:4:48:9|Input testin is unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\TopMatrix_PDR.vhd":57:8:57:9|Trying to extract state machine for register ect | ||||
Extracted state machine for register ect | ||||
State machine has 4 reachable states with original encodings of: | ||||
00 | ||||
01 | ||||
10 | ||||
11 | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\DriveInputs.vhd":50:8:50:9|Trying to extract state machine for register ect | ||||
Extracted state machine for register ect | ||||
State machine has 7 reachable states with original encodings of: | ||||
0000001 | ||||
0000010 | ||||
0000100 | ||||
0001000 | ||||
0010000 | ||||
0100000 | ||||
1000000 | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":69:8:69:9|Trying to extract state machine for register st | ||||
Extracted state machine for register st | ||||
State machine has 8 reachable states with original encodings of: | ||||
0000000010 | ||||
0000000100 | ||||
0000001000 | ||||
0000010000 | ||||
0000100000 | ||||
0001000000 | ||||
0010000000 | ||||
0100000000 | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd":69:8:69:9|Trying to extract state machine for register ect | ||||
Extracted state machine for register ect | ||||
State machine has 10 reachable states with original encodings of: | ||||
0000000001 | ||||
0000000010 | ||||
0000000100 | ||||
0000001000 | ||||
0000010000 | ||||
0000100000 | ||||
0001000000 | ||||
0010000000 | ||||
0100000000 | ||||
1000000000 | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_matrix\GetResult.vhd":54:8:54:9|Trying to extract state machine for register ect | ||||
Extracted state machine for register ect | ||||
State machine has 4 reachable states with original encodings of: | ||||
00 | ||||
01 | ||||
10 | ||||
11 | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":48:4:48:9|Input testin is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":39:4:39:8|Input ReUse is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 117 to 52 of apbi(117 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bit 50 of apbi(117 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 15 to 1 of apbi(117 downto 0) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":56:4:56:7|Input rclk is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":59:4:59:6|Input REN is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":48:4:48:9|Input testin is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\lpp_FIFO.vhd":39:4:39:8|Input ReUse is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 117 to 66 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 15 to 7 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":67:4:67:7|Input port bits 5 to 0 of apbi(117 downto 0) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":56:4:56:7|Input rclk is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":57:4:57:7|Input wclk is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":58:4:58:8|Input ReUse is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":59:4:59:6|Input REN is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":60:4:60:6|Input WEN is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd":64:4:64:8|Input WDATA is unused | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 16 of apbo.prdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 11 of Rdata(11 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 10 of Rdata(11 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 19 of Rdata(31 downto 17) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 18 of Rdata(31 downto 17) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 15 of Rdata(15 downto 13) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":101:12:101:13|Pruning Register bit 14 of Rdata(15 downto 13) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 15 of apbo.prdata(15 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 14 of apbo.prdata(15 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 11 of apbo.prdata(15 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 10 of apbo.prdata(15 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 19 of apbo.prdata(31 downto 17) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":142:20:142:21|Pruning Register bit 18 of apbo.prdata(31 downto 17) | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":47:4:47:7|Input port bits 117 to 58 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":47:4:47:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":47:4:47:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":47:4:47:7|Input port bits 15 to 11 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd":47:4:47:7|Input port bits 9 to 0 of apbi(117 downto 0) are unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\TimerDelay.vhd":37:8:37:9|Trying to extract state machine for register ect | ||||
Extracted state machine for register ect | ||||
State machine has 3 reachable states with original encodings of: | ||||
00 | ||||
01 | ||||
10 | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Register bit Rdata(26) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Register bit Rdata(27) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Register bit Rdata(28) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Register bit Rdata(29) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Register bit Rdata(30) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Register bit Rdata(31) is always 0, optimizing ... | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Pruning Register bit 31 of Rdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Pruning Register bit 30 of Rdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Pruning Register bit 29 of Rdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Pruning Register bit 28 of Rdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Pruning Register bit 27 of Rdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":96:12:96:13|Pruning Register bit 26 of Rdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":135:16:135:17|Pruning Register bit 31 of apbo.prdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":135:16:135:17|Pruning Register bit 30 of apbo.prdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":135:16:135:17|Pruning Register bit 29 of apbo.prdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":135:16:135:17|Pruning Register bit 28 of apbo.prdata(31 downto 0) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":135:16:135:17|Pruning Register bit 27 of apbo.prdata(31 downto 0) | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":45:4:45:7|Input port bits 117 to 76 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":45:4:45:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":45:4:45:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":45:4:45:7|Input port bits 15 to 12 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd":45:4:45:7|Input port bits 10 to 0 of apbi(117 downto 0) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\rstgen.vhd":40:4:40:10|Input testrst is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\rstgen.vhd":41:4:41:9|Input testen is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\clkpad.vhd":36:49:36:52|Input rstn is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\clkgen.vhd":56:4:56:6|Input cgi is unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Trying to extract state machine for register r.d.cnt | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Trying to extract state machine for register r.x.rstate | ||||
Extracted state machine for register r.x.rstate | ||||
State machine has 4 reachable states with original encodings of: | ||||
00 | ||||
01 | ||||
10 | ||||
11 | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 203 to 200 of ico(203 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 198 to 167 of ico(203 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 165 to 134 of ico(203 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 132 to 131 of ico(203 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 129 to 128 of ico(203 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 95 to 0 of ico(203 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bits 207 to 134 of dco(210 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bit 131 of dco(210 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bits 129 to 128 of dco(210 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bits 95 to 0 of dco(210 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":77:4:77:7|Input port bits 30 to 4 of irqi(30 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":79:4:79:7|Input port bits 97 to 66 of dbgi(97 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":85:4:85:6|Input port bit 37 of fpo(69 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":85:4:85:6|Input port bits 35 to 0 of fpo(69 downto 0) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":82:4:82:7|Input mulo is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":84:4:84:7|Input divo is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":87:4:87:6|Input cpo is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd":89:4:89:6|Input tbo is unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Trying to extract state machine for register r.istate | ||||
Extracted state machine for register r.istate | ||||
State machine has 3 reachable states with original encodings of: | ||||
00 | ||||
10 | ||||
11 | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 131 to 101 of ici(131 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 95 to 64 of ici(131 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 33 to 22 of ici(131 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 1 to 0 of ici(131 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":55:4:55:6|Input port bits 117 to 40 of dci(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":55:4:55:6|Input port bits 7 to 0 of dci(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 210 to 207 of dco(210 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 205 to 180 of dco(210 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 177 to 173 of dco(210 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bit 169 of dco(210 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 165 to 156 of dco(210 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 135 to 132 of dco(210 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 130 to 0 of dco(210 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":58:4:58:7|Input port bits 41 to 37 of mcio(41 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":60:4:60:9|Input port bits 319 to 256 of icramo(319 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":60:4:60:9|Input port bits 95 to 0 of icramo(319 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":62:4:62:9|Input port bits 117 to 85 of mmudci(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":62:4:62:9|Input port bits 76 to 0 of mmudci(117 downto 0) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":64:4:64:9|Input mmuico is unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Trying to extract state machine for register r.dstate | ||||
Extracted state machine for register r.dstate | ||||
State machine has 6 reachable states with original encodings of: | ||||
000000001 | ||||
000000010 | ||||
000001000 | ||||
001000000 | ||||
010000000 | ||||
100000000 | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bit 116 of dci(117 downto 0) is unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bit 113 of dci(117 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bits 71 to 52 of dci(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bits 41 to 40 of dci(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bits 7 to 5 of dci(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":70:4:70:6|Input port bits 203 to 199 of ico(203 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":70:4:70:6|Input port bit 166 of ico(203 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":70:4:70:6|Input port bits 130 to 0 of ico(203 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":72:4:72:7|Input port bits 43 to 38 of mcdo(45 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":73:4:73:8|Input port bits 139 to 28 of ahbsi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":73:4:73:8|Input port bits 19 to 0 of ahbsi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":75:4:75:9|Input port bits 451 to 384 of dcramo(451 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":75:4:75:9|Input port bits 363 to 256 of dcramo(451 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":78:4:78:9|Input port bits 110 to 2 of mmudco(110 downto 0) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":79:4:79:7|Input sclk is unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":355:4:355:5|Trying to extract state machine for register r.bo | ||||
Extracted state machine for register r.bo | ||||
State machine has 4 reachable states with original encodings of: | ||||
00 | ||||
01 | ||||
10 | ||||
11 | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":50:4:50:7|Input port bit 35 of mcii(35 downto 0) is unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":54:4:54:8|Input port bit 66 of mcmmi(69 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":56:4:56:7|Input port bits 87 to 85 of ahbi(87 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":56:4:56:7|Input port bits 83 to 51 of ahbi(87 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":56:4:56:7|Input port bits 14 to 0 of ahbi(87 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5503 to 5372 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5359 to 5357 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5343 to 5340 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5327 to 5325 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5311 to 5308 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5295 to 5293 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5279 to 5276 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5263 to 5261 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5247 to 5028 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5015 to 5013 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4999 to 4996 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4983 to 4981 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4967 to 4964 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4951 to 4949 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4935 to 4932 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4919 to 4917 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4903 to 4684 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4671 to 4669 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4655 to 4652 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4639 to 4637 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4623 to 4620 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4607 to 4605 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4591 to 4588 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4575 to 4573 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4559 to 4340 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4327 to 4325 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4311 to 4308 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4295 to 4293 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4279 to 4276 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4263 to 4261 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4247 to 4244 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4231 to 4229 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4215 to 3996 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3983 to 3981 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3967 to 3964 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3951 to 3949 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3935 to 3932 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3919 to 3917 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3903 to 3900 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3887 to 3885 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3871 to 3652 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3639 to 3637 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3623 to 3620 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3607 to 3605 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3591 to 3588 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3575 to 3573 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3559 to 3556 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3543 to 3541 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3527 to 3308 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3295 to 3293 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3279 to 3276 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3263 to 3261 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3247 to 3244 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3231 to 3229 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3215 to 3212 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3199 to 3197 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3183 to 2964 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2951 to 2949 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2935 to 2932 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2919 to 2917 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2903 to 2900 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2887 to 2885 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2871 to 2868 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2855 to 2853 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2839 to 2620 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2607 to 2605 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2591 to 2588 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2575 to 2573 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2559 to 2556 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2543 to 2541 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2527 to 2524 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2511 to 2509 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2495 to 2276 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2263 to 2261 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2247 to 2244 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2231 to 2229 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2215 to 2212 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2199 to 2197 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2183 to 2180 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2167 to 2165 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2151 to 1932 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1919 to 1917 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1903 to 1900 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1887 to 1885 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1871 to 1868 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1855 to 1853 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1839 to 1836 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1823 to 1821 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1807 to 1588 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1575 to 1573 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1559 to 1556 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1543 to 1541 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1527 to 1524 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1511 to 1509 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1495 to 1492 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1479 to 1477 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1463 to 1244 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1231 to 1229 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1215 to 1212 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1199 to 1197 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1183 to 1180 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1167 to 1165 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1151 to 1148 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1135 to 1133 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1119 to 900 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 887 to 885 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 871 to 868 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 855 to 853 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 839 to 836 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 823 to 821 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 807 to 804 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 791 to 789 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 775 to 556 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 543 to 541 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 527 to 524 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 511 to 509 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 495 to 492 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 479 to 477 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 463 to 460 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 447 to 445 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 431 to 212 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 199 to 197 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 183 to 180 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 167 to 165 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 151 to 148 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 135 to 133 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 119 to 116 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 103 to 101 of ahbso(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 87 to 0 of ahbso(5503 downto 0) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd":59:4:59:9|Input hclken is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\mmu_cache.vhd":88:4:88:7|Input hclk is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":48:4:48:9|Input testin is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":127:4:127:6|Input wea is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":44:4:44:9|Input testin is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":188:4:188:11|Input address2 is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\proasic3\memory_apa3.vhd":189:4:189:10|Input datain2 is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\techmap\maps\syncram.vhd":44:4:44:9|Input testin is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 796 to 647 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 645 to 643 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 641 to 639 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 606 to 511 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 508 to 502 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 500 to 370 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 349 to 342 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 337 to 232 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 221 to 191 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 189 to 187 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 150 to 148 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 127 to 120 of crami(796 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 115 to 10 of crami(796 downto 0) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd":64:8:64:11|Input sclk is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 139 to 94 of ahbsi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 92 to 89 of ahbsi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 56 to 51 of ahbsi(139 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bit 49 of ahbsi(139 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 47 to 41 of ahbsi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 17 to 14 of ahbsi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 12 to 0 of ahbsi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":57:4:57:7|Input port bits 0 to 18 of dbgi(0 to 58) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":52:4:52:7|Input hclk is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":54:4:54:8|Input ahbmi is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 117 to 98 of apbi(117 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bit 82 of apbi(117 downto 0) is unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bit 66 of apbi(117 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 15 to 14 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 12 to 0 of apbi(117 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":56:4:56:7|Input port bit 0 of irqi(0 to 6) is unused | ||||
@W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Optimizing register bit r.ramoen(4) to a constant 1 | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Pruning Register bit 4 of r.ramoen(4 downto 0) | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bwrite16) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bread16) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bwrite8) is always 0, optimizing ... | ||||
@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bread8) is always 0, optimizing ... | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 0 of r.bstate(0 to 7) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 1 of r.bstate(0 to 7) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 2 of r.bstate(0 to 7) | ||||
@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 3 of r.bstate(0 to 7) | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":79:4:79:7|Input port bits 137 to 41 of memi(137 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":79:4:79:7|Input port bits 38 to 34 of memi(137 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 139 to 103 of ahbsi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 99 to 94 of ahbsi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 92 to 89 of ahbsi(139 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bit 53 of ahbsi(139 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 14 to 0 of ahbsi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 117 to 79 of apbi(117 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bit 74 of apbi(117 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 68 to 63 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 48 to 23 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 14 to 0 of apbi(117 downto 0) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":85:4:85:6|Input wpo is unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":87:4:87:5|Trying to extract state machine for register state | ||||
Extracted state machine for register state | ||||
State machine has 5 reachable states with original encodings of: | ||||
00001 | ||||
00010 | ||||
00100 | ||||
01000 | ||||
10000 | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":39:4:39:14|Input port bits 347 to 165 of mem_ctrlr_o(347 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":39:4:39:14|Input port bits 159 to 129 of mem_ctrlr_o(347 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":39:4:39:14|Input port bits 127 to 32 of mem_ctrlr_o(347 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd":39:4:39:14|Input port bits 19 to 0 of mem_ctrlr_o(347 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 5935 to 738 of msto(5935 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 705 to 482 of msto(5935 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 370 to 367 of msto(5935 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 334 to 111 of msto(5935 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 5503 to 2748 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2458 to 2443 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2407 to 2404 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2114 to 2099 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2063 to 2060 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1770 to 1755 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1719 to 1716 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1426 to 1411 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1375 to 1372 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1082 to 1067 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1031 to 1028 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 738 to 723 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 687 to 684 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 394 to 379 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 343 to 340 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 50 to 35 of slvo(5503 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\ahbmst.vhd":49:6:49:9|Input port bits 87 to 51 of ahbi(87 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\ahbmst.vhd":49:6:49:9|Input port bit 15 of ahbi(87 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\ahbmst.vhd":49:6:49:9|Input port bits 13 to 0 of ahbi(87 downto 0) are unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Trying to extract state machine for register r.txstate | ||||
Extracted state machine for register r.txstate | ||||
State machine has 3 reachable states with original encodings of: | ||||
00 | ||||
01 | ||||
10 | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Trying to extract state machine for register r.rxstate | ||||
Extracted state machine for register r.rxstate | ||||
State machine has 4 reachable states with original encodings of: | ||||
00 | ||||
01 | ||||
10 | ||||
11 | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":48:4:48:5|Input port bits 2 to 1 of ui(2 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 117 to 68 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 48 to 21 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 15 to 9 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 7 to 0 of apbi(117 downto 0) are unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":147:8:147:9|Trying to extract state machine for register r.state | ||||
Extracted state machine for register r.state | ||||
State machine has 6 reachable states with original encodings of: | ||||
000001 | ||||
000010 | ||||
000100 | ||||
001000 | ||||
010000 | ||||
100000 | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":40:6:40:9|Input port bits 14 to 3 of dmao(46 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":40:6:40:9|Input port bit 0 of dmao(46 downto 0) is unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":42:6:42:10|Input port bit 4 of uarto(12 downto 0) is unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":42:6:42:10|Input port bit 1 of uarto(12 downto 0) is unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\dcom.vhd":43:6:43:9|Input ahbi is unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":222:8:222:9|Trying to extract state machine for register r.state | ||||
Extracted state machine for register r.state | ||||
State machine has 3 reachable states with original encodings of: | ||||
00 | ||||
01 | ||||
10 | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 103 to 94 of ahbi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 92 to 89 of ahbi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 56 to 51 of ahbi(139 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bit 49 of ahbi(139 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 47 to 36 of ahbi(139 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bit 15 of ahbi(139 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 13 to 0 of ahbi(139 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 0 to 3 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 132 to 135 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 264 to 267 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 396 to 399 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 528 to 531 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 660 to 663 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 792 to 795 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 924 to 927 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1056 to 1059 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1188 to 1191 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1320 to 1323 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1452 to 1455 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1584 to 1587 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1716 to 1719 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1848 to 1851 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1980 to 1983 of apbo(0 to 2111) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 117 to 82 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 48 to 24 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 15 to 13 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 11 to 0 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd":65:4:65:7|Input port bits 2 to 1 of gpti(2 downto 0) are unused | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Trying to extract state machine for register r.txstate | ||||
Extracted state machine for register r.txstate | ||||
State machine has 4 reachable states with original encodings of: | ||||
00 | ||||
01 | ||||
10 | ||||
11 | ||||
@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Trying to extract state machine for register r.rxstate | ||||
Extracted state machine for register r.rxstate | ||||
State machine has 5 reachable states with original encodings of: | ||||
00001 | ||||
00010 | ||||
00100 | ||||
01000 | ||||
10000 | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 117 to 65 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bit 15 of apbi(117 downto 0) is unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 13 to 0 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 117 to 57 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 48 to 23 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 15 to 5 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 3 to 0 of apbi(117 downto 0) are unused | ||||
@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd":65:4:65:8|Input port bits 95 to 7 of gpioi(95 downto 0) are unused | ||||
@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\leon3mp.vhd":68:4:68:8|Input urxd1 is unused | ||||
@END | ||||
Process took 0h:00m:36s realtime, 0h:00m:36s cputime | ||||
# Thu Oct 25 15:24:07 2012 | ||||
###########################################################] | ||||
Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 | ||||
Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved | ||||
Product Version E-2010.09A-1 | ||||
@N: MF249 |Running in 32-bit mode. | ||||
@N: MF258 |Gated clock conversion disabled | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Sequential instance MemIn.apbo\.prdata_e has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Sequential instance MemIn.apbo\.prdata_e_1 has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Sequential instance MemIn.apbo\.prdata_e_2 has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Sequential instance MemIn.apbo\.prdata_e_3 has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":221:16:221:17|Sequential instance MemIn.apbo\.prdata[17] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":221:16:221:17|Sequential instance MemIn.apbo\.prdata[18] has been reduced to a combinational gate by constant propagation | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|tristate driver apbo\.prdata_tri[30] on net apbo\.prdata_tri[30] has its enable tied to GND (module APB_FIFOZ2) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|tristate driver apbo\.prdata_tri[29] on net apbo\.prdata_tri[29] has its enable tied to GND (module APB_FIFOZ2) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|tristate driver apbo\.prdata_tri[31] on net apbo\.prdata_tri[31] has its enable tied to GND (module APB_FIFOZ2) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|tristate driver apbo\.prdata_tri[28] on net apbo\.prdata_tri[28] has its enable tied to GND (module APB_FIFOZ2) | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Sequential instance Memtest.apbo\.prdata_e has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Sequential instance Memtest.apbo\.prdata_e_1 has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Sequential instance Memtest.apbo\.prdata_e_2 has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Sequential instance Memtest.apbo\.prdata_e_3 has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":221:16:221:17|Sequential instance Memtest.apbo\.prdata[17] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":221:16:221:17|Sequential instance Memtest.apbo\.prdata[18] has been reduced to a combinational gate by constant propagation | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|tristate driver apbo\.prdata_tri[30] on net apbo\.prdata_tri[30] has its enable tied to GND (module APB_FIFOZ0) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|tristate driver apbo\.prdata_tri[31] on net apbo\.prdata_tri[31] has its enable tied to GND (module APB_FIFOZ0) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|tristate driver apbo\.prdata_tri[28] on net apbo\.prdata_tri[28] has its enable tied to GND (module APB_FIFOZ0) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|tristate driver apbo\.prdata_tri[29] on net apbo\.prdata_tri[29] has its enable tied to GND (module APB_FIFOZ0) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri31 on net gpioi_tri31 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri30 on net gpioi_tri30 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri29 on net gpioi_tri29 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri28 on net gpioi_tri28 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri27 on net gpioi_tri27 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri26 on net gpioi_tri26 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri25 on net gpioi_tri25 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri24 on net gpioi_tri24 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri23 on net gpioi_tri23 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri22 on net gpioi_tri22 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri21 on net gpioi_tri21 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri20 on net gpioi_tri20 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri19 on net gpioi_tri19 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri18 on net gpioi_tri18 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri17 on net gpioi_tri17 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri16 on net gpioi_tri16 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri15 on net gpioi_tri15 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri14 on net gpioi_tri14 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri13 on net gpioi_tri13 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri12 on net gpioi_tri12 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri11 on net gpioi_tri11 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri10 on net gpioi_tri10 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri9 on net gpioi_tri9 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri8 on net gpioi_tri8 has its enable tied to GND (module leon3mp) | ||||
@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\leon3mp.vhd":415:20:415:23|tristate driver gpioi_tri7 on net gpioi_tri7 has its enable tied to GND (module leon3mp) | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Sequential instance ua1.uart1.r\.extclk has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Sequential instance memctrlr.r\.bexcn has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Sequential instance memctrlr.r\.brdyn has been reduced to a combinational gate by constant propagation | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":2193:4:2193:19|Removing sequential instance actar_0.DFN1_Mult_0_inst of view:pa3l.DFN1(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd":469:4:469:11|Removing sequential instance actar_0.DFN1_117 of view:pa3l.DFN1(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance memctrlr.r\.echeck of view:PrimLib.sdffr(prim) because there are no references to its outputs | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\apb_uart.vhd":101:12:101:13|Removing sequential instance COM0.Rdata[17], because it is equivalent to instance COM0.Rdata[13] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance Memtest.PRdata_cl_6[31], because it is equivalent to instance Memtest.PRdata_cl_9[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance Memtest.PRdata_cl_3[31], because it is equivalent to instance Memtest.PRdata_cl_2[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance Memtest.PRdata_cl_2[31], because it is equivalent to instance Memtest.PRdata_cl[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance Memtest.PRdata_cl_8[31], because it is equivalent to instance Memtest.PRdata_cl_7[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance Memtest.PRdata_cl_7[31], because it is equivalent to instance Memtest.PRdata_cl_4[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance Memtest.PRdata[31], because it is equivalent to instance Memtest.PRdata[30] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance Memtest.PRdata[30], because it is equivalent to instance Memtest.PRdata[28] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance Memtest.PRdata_cl_1[31], because it is equivalent to instance Memtest.PRdata_cl[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance Memtest.PRdata[29], because it is equivalent to instance Memtest.PRdata[28] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance MemOut.PRdata_cl_3[31], because it is equivalent to instance MemOut.PRdata_cl_2[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance MemOut.PRdata_cl_2[31], because it is equivalent to instance MemOut.PRdata_cl_1[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance MemOut.PRdata_cl_5[31], because it is equivalent to instance MemOut.PRdata_cl_8[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance MemOut.PRdata_cl_13[31], because it is equivalent to instance MemOut.PRdata_cl_12[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance MemOut.PRdata_cl_12[31], because it is equivalent to instance MemOut.PRdata_cl_10[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance MemOut.PRdata_cl_11[31], because it is equivalent to instance MemOut.PRdata_cl_9[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance MemOut.PRdata_cl_10[31], because it is equivalent to instance MemOut.PRdata_cl_7[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance MemOut.PRdata_cl_4[31], because it is equivalent to instance MemOut.PRdata_cl_8[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance MemOut.PRdata_cl_8[31], because it is equivalent to instance MemOut.PRdata_cl_6[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance Memtest.apbo.prdata_e_11, because it is equivalent to instance Memtest.apbo.prdata_e_10 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance Memtest.apbo.prdata_e_10, because it is equivalent to instance Memtest.apbo.prdata_e_8 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance MemOut.PRdata_cl_7[31], because it is equivalent to instance MemOut.PRdata_cl_9[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance Memtest.apbo.prdata_e_7, because it is equivalent to instance Memtest.apbo.prdata_e_6 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance Memtest.apbo.prdata_e_6, because it is equivalent to instance Memtest.apbo.prdata_e_4 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemOut.apbo.prdata_e_13, because it is equivalent to instance MemOut.apbo.prdata_e_12 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemOut.apbo.prdata_e_12, because it is equivalent to instance MemOut.apbo.prdata_e_10 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemOut.apbo.prdata_e_11, because it is equivalent to instance MemOut.apbo.prdata_e_9 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemOut.apbo.prdata_e_10, because it is equivalent to instance MemOut.apbo.prdata_e_8 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance MemOut.PRdata_cl_1[31], because it is equivalent to instance MemOut.PRdata_cl[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance Memtest.apbo.prdata[31], because it is equivalent to instance Memtest.apbo.prdata[30] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance Memtest.apbo.prdata[30], because it is equivalent to instance Memtest.apbo.prdata[29] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance Memtest.apbo.prdata[29], because it is equivalent to instance Memtest.apbo.prdata[28] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance Memtest.apbo.prdata_e_5, because it is equivalent to instance Memtest.apbo.prdata_e_4 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance Memtest.apbo.prdata_e_13, because it is equivalent to instance Memtest.apbo.prdata_e_12 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance Memtest.PRdata_cl_5[31], because it is equivalent to instance Memtest.PRdata_cl_4[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemOut.apbo.prdata_e_3, because it is equivalent to instance MemOut.apbo.prdata_e_1 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemOut.apbo.prdata_e_1, because it is equivalent to instance MemOut.apbo.prdata_e | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemOut.apbo.prdata_e_2, because it is equivalent to instance MemOut.apbo.prdata_e | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemOut.apbo.prdata_e_7, because it is equivalent to instance MemOut.apbo.prdata_e_6 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemOut.apbo.prdata_e_6, because it is equivalent to instance MemOut.apbo.prdata_e_5 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemOut.apbo.prdata_e_5, because it is equivalent to instance MemOut.apbo.prdata_e_4 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemOut.apbo.prdata_e_9, because it is equivalent to instance MemOut.apbo.prdata_e_8 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance Memtest.apbo.prdata_e_9, because it is equivalent to instance Memtest.apbo.prdata_e_8 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":193:24:193:25|Removing sequential instance MemIn.PRdata_cl_5[31], because it is equivalent to instance MemIn.PRdata_cl_4[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":193:24:193:25|Removing sequential instance MemIn.PRdata[31], because it is equivalent to instance MemIn.PRdata[30] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":193:24:193:25|Removing sequential instance MemIn.PRdata[30], because it is equivalent to instance MemIn.PRdata[28] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":193:24:193:25|Removing sequential instance MemIn.PRdata_cl_6[31], because it is equivalent to instance MemIn.PRdata_cl_7[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":193:24:193:25|Removing sequential instance MemIn.PRdata[29], because it is equivalent to instance MemIn.PRdata[28] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":193:24:193:25|Removing sequential instance MemIn.PRdata_cl_1[31], because it is equivalent to instance MemIn.PRdata_cl_2[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":193:24:193:25|Removing sequential instance MemIn.PRdata_cl_7[31], because it is equivalent to instance MemIn.PRdata_cl_9[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemIn.apbo.prdata_e_12, because it is equivalent to instance MemIn.apbo.prdata_e_10 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemIn.apbo.prdata_e_9, because it is equivalent to instance MemIn.apbo.prdata_e_8 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemIn.apbo.prdata[31], because it is equivalent to instance MemIn.apbo.prdata[30] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemIn.apbo.prdata[30], because it is equivalent to instance MemIn.apbo.prdata[29] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemIn.apbo.prdata[29], because it is equivalent to instance MemIn.apbo.prdata[28] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":193:24:193:25|Removing sequential instance MemIn.PRdata_cl_3[31], because it is equivalent to instance MemIn.PRdata_cl_2[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":193:24:193:25|Removing sequential instance MemIn.PRdata_cl_2[31], because it is equivalent to instance MemIn.PRdata_cl[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemIn.apbo.prdata_e_13, because it is equivalent to instance MemIn.apbo.prdata_e_10 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemIn.apbo.prdata_e_6, because it is equivalent to instance MemIn.apbo.prdata_e_5 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemIn.apbo.prdata_e_5, because it is equivalent to instance MemIn.apbo.prdata_e_4 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemIn.apbo.prdata_e_7, because it is equivalent to instance MemIn.apbo.prdata_e_4 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":193:24:193:25|Removing sequential instance MemIn.PRdata_cl_9[31], because it is equivalent to instance MemIn.PRdata_cl_8[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemIn.apbo.prdata_e_11, because it is equivalent to instance MemIn.apbo.prdata_e_10 | ||||
Available hyper_sources - for debug and ip models | ||||
None Found | ||||
Finished RTL optimizations (Time elapsed 0h:00m:05s; Memory used current: 81MB peak: 97MB) | ||||
Encoding state machine work.leon3mp(behavioral)-l3\.cpu\.0\.u0.p0.c0mmu.a0.r\.bo[0:3] | ||||
original code -> new code | ||||
00 -> 00 | ||||
01 -> 01 | ||||
10 -> 10 | ||||
11 -> 11 | ||||
@N: MF176 |Default generator successful | ||||
@N: MF176 |Default generator successful | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[0] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[1] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[2] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[3] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[4] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[5] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[6] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[7] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[8] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[9] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[10] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[11] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[15] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[16] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[17] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[18] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[19] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[20] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[21] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[22] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[23] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[25] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[26] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[27] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[28] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[29] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[30] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[31] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Sequential instance memctrlr.r.hresp[1] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\apb_delay.vhd":135:16:135:17|Sequential instance Delay0.apbo.prdata[26] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\apb_uart.vhd":142:20:142:21|Sequential instance COM0.apbo.prdata[12] has been reduced to a combinational gate by constant propagation | ||||
@W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit memctrlr.r\.hburst[2] is always 0, optimizing ... | ||||
@W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit memctrlr.r\.hburst[1] is always 0, optimizing ... | ||||
@N: BN115 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Removing instance memctrlr.un1_v\.ws_1_sqmuxa_2_0 of view:VhdlGenLib.ADD__const_cin_w4_0(verilog) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r\.hmasterlockd of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance Memtest.apbo\.prdata[28] of view:PrimLib.lat(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":191:12:191:13|Removing sequential instance Memtest.PRdata[28] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[0] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[18] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[19] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[20] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[21] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[22] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[23] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[25] has been reduced to a combinational gate by constant propagation | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[27] has been reduced to a combinational gate by constant propagation | ||||
@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\clk_divider.vhd":59:13:59:20|Found 32 bit incrementor, 'un3_cpt1[1:32]' | ||||
@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_ad_conv\ad7688_drvr.vhd":91:48:91:50|Found 6 bit incrementor, 'un6_i[27:32]' | ||||
@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_ad_conv\ad7688_spi_if.vhd":64:12:64:14|Found 5 bit incrementor, 'spidrvr.un3_i[28:32]' | ||||
Encoding state machine lpp.WriteGen_ADC(ar_wg)-ect[0:2] | ||||
original code -> new code | ||||
00 -> 00 | ||||
01 -> 01 | ||||
10 -> 10 | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":111:4:111:5|Found counter in view:lpp.lpp_fifoZ2_fifos\.1\.FIFO0(ar_lpp_fifo) inst Waddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":84:4:84:5|Found counter in view:lpp.lpp_fifoZ2_fifos\.1\.FIFO0(ar_lpp_fifo) inst Raddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":111:4:111:5|Found counter in view:lpp.lpp_fifoZ2_fifos\.4\.FIFO0(ar_lpp_fifo) inst Waddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":84:4:84:5|Found counter in view:lpp.lpp_fifoZ2_fifos\.4\.FIFO0(ar_lpp_fifo) inst Raddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":111:4:111:5|Found counter in view:lpp.lpp_fifoZ2_fifos\.0\.FIFO0(ar_lpp_fifo) inst Waddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":84:4:84:5|Found counter in view:lpp.lpp_fifoZ2_fifos\.0\.FIFO0(ar_lpp_fifo) inst Raddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":111:4:111:5|Found counter in view:lpp.lpp_fifoZ2_fifos\.3\.FIFO0(ar_lpp_fifo) inst Waddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":84:4:84:5|Found counter in view:lpp.lpp_fifoZ2_fifos\.3\.FIFO0(ar_lpp_fifo) inst Raddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":111:4:111:5|Found counter in view:lpp.lpp_fifoZ2_fifos\.2\.FIFO0(ar_lpp_fifo) inst Waddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":84:4:84:5|Found counter in view:lpp.lpp_fifoZ2_fifos\.2\.FIFO0(ar_lpp_fifo) inst Raddr_vect[7:0] | ||||
Encoding state machine lpp.Driver_FFT(ar_driver)-ect[0:2] | ||||
original code -> new code | ||||
00 -> 00 | ||||
01 -> 01 | ||||
11 -> 10 | ||||
@N: MO106 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\twiddle.vhd":37:4:37:7|Found ROM, 'lut_0.t_int1[30:0]', 128 words by 31 bits | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":42:4:42:5|Found counter in view:lpp.counter_8_139(translated) inst Q_out[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":42:4:42:5|Found counter in view:lpp.counter_3_7(translated) inst Q_out[2:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":42:4:42:5|Found counter in view:lpp.counter_7_127(translated) inst Q_out[6:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":42:4:42:5|Found counter in view:lpp.counter_8_255_ldCount(translated) inst Q_out[7:0] | ||||
@N: MF176 |Default generator successful | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":82:4:82:5|Found counter in view:lpp.bcounter(translated) inst Q_out[9:0] | ||||
@N: MF176 |Default generator successful | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":42:4:42:5|Found counter in view:lpp.counter_8_255_outBuf_rA_0(translated) inst Q_out[7:0] | ||||
@N: MF184 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":272:10:272:24|Found 16 by 16 bit subtractor, 'Hi_w_0_0[15:0]' | ||||
@N: MF176 |Default generator successful | ||||
@N: MF184 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":277:44:277:54|Found 16 by 16 bit subtractor, 'outQ_xhdl2_1_0[15:0]' | ||||
@N: MF184 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":278:39:278:49|Found 16 by 16 bit subtractor, 'outQ_xhdl2_2_0_0[15:0]' | ||||
@N: MF176 |Default generator successful | ||||
@N: MF176 |Default generator successful | ||||
@N: MF176 |Default generator successful | ||||
@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":104:24:104:47|Found 17 bit incrementor, 'un5_int_outp[16:0]' | ||||
@W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":620:4:620:5|Register bit ldMonitor is always 1, optimizing ... | ||||
Encoding state machine lpp.Linker_FFT(ar_linker)-ect[0:4] | ||||
original code -> new code | ||||
00001 -> 00001 | ||||
00010 -> 00010 | ||||
00100 -> 00100 | ||||
01000 -> 01000 | ||||
10000 -> 10000 | ||||
@N: MF176 |Default generator successful | ||||
Ram Decomposition Statistics for SRAM.inf\.x0.rfd[15:0] | ||||
RAM 512x9 : 0 | ||||
RAM 512x9 : 0 | ||||
Ram Decomposition Statistics for SRAM.inf\.x0.rfd[15:0] | ||||
RAM 512x9 : 0 | ||||
RAM 512x9 : 0 | ||||
Ram Decomposition Statistics for SRAM.inf\.x0.rfd[15:0] | ||||
RAM 512x9 : 0 | ||||
RAM 512x9 : 0 | ||||
Ram Decomposition Statistics for SRAM.inf\.x0.rfd[15:0] | ||||
RAM 512x9 : 0 | ||||
RAM 512x9 : 0 | ||||
Ram Decomposition Statistics for SRAM.inf\.x0.rfd[15:0] | ||||
RAM 512x9 : 0 | ||||
RAM 512x9 : 0 | ||||
Encoding state machine lpp.TopMatrix_PDR(ar_topmatrix_pdr)-ect[0:3] | ||||
original code -> new code | ||||
00 -> 00 | ||||
01 -> 01 | ||||
10 -> 10 | ||||
11 -> 11 | ||||
@N: MF176 |Default generator successful | ||||
@N: MF176 |Default generator successful | ||||
Encoding state machine lpp.DriveInputs(ar_driveinputs)-ect[0:6] | ||||
original code -> new code | ||||
0000001 -> 0000001 | ||||
0000010 -> 0000010 | ||||
0000100 -> 0000100 | ||||
0001000 -> 0001000 | ||||
0010000 -> 0010000 | ||||
0100000 -> 0100000 | ||||
1000000 -> 1000000 | ||||
@N: MF176 |Default generator successful | ||||
Encoding state machine lpp.ALU_Driver(ar_alu_driver)-st[0:7] | ||||
original code -> new code | ||||
0000000010 -> 00000001 | ||||
0000000100 -> 00000010 | ||||
0000001000 -> 00000100 | ||||
0000010000 -> 00001000 | ||||
0000100000 -> 00010000 | ||||
0001000000 -> 00100000 | ||||
0010000000 -> 01000000 | ||||
0100000000 -> 10000000 | ||||
Encoding state machine lpp.ALU_Driver(ar_alu_driver)-ect[0:9] | ||||
original code -> new code | ||||
0000000001 -> 0000000001 | ||||
0000000010 -> 0000000010 | ||||
0000000100 -> 0000000100 | ||||
0000001000 -> 0000001000 | ||||
0000010000 -> 0000010000 | ||||
0000100000 -> 0000100000 | ||||
0001000000 -> 0001000000 | ||||
0010000000 -> 0010000000 | ||||
0100000000 -> 0100000000 | ||||
1000000000 -> 1000000000 | ||||
@W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_matrix\alu_driver.vhd":69:8:69:9|Register bit CTRL[2] is always 0, optimizing ... | ||||
@W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_matrix\alu_driver.vhd":69:8:69:9|Register bit CTRL[1] is always 0, optimizing ... | ||||
@N: MF176 |Default generator successful | ||||
@N: MF176 |Default generator successful | ||||
@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_matrix\twocomplementer.vhd":52:40:52:49|Found 16 bit incrementor, 'rescomp_1[15:0]' | ||||
Encoding state machine lpp.GetResult(ar_getresult)-ect[0:3] | ||||
original code -> new code | ||||
00 -> 00 | ||||
01 -> 01 | ||||
10 -> 10 | ||||
11 -> 11 | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":111:4:111:5|Found counter in view:lpp.lpp_fifoZ1(ar_lpp_fifo) inst Waddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":84:4:84:5|Found counter in view:lpp.lpp_fifoZ1(ar_lpp_fifo) inst Raddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":111:4:111:5|Found counter in view:lpp.lpp_fifoZ2(ar_lpp_fifo) inst Waddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\lpp_fifo.vhd":84:4:84:5|Found counter in view:lpp.lpp_fifoZ2(ar_lpp_fifo) inst Raddr_vect[7:0] | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\baudgen.vhd":58:4:58:5|Found counter in view:lpp.BaudGen(ar_baudgen) inst cpt[11:0] | ||||
@W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Register bit REG[9] is always 1, optimizing ... | ||||
@W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Register bit Q_1[9] is always 1, optimizing ... | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\lpp_delay\timerdelay.vhd":37:8:37:9|Found counter in view:lpp.TimerDelay(ar_timerdelay) inst compt[25:0] | ||||
Encoding state machine lpp.TimerDelay(ar_timerdelay)-ect[0:2] | ||||
original code -> new code | ||||
00 -> 00 | ||||
01 -> 01 | ||||
10 -> 10 | ||||
Encoding state machine gaisler.iu3(rtl)-r\.x\.rstate[0:3] | ||||
original code -> new code | ||||
00 -> 00 | ||||
01 -> 01 | ||||
10 -> 10 | ||||
11 -> 11 | ||||
@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un6_fe_npc_0[29:0]' | ||||
@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un6_fe_npc_1[29:0]' | ||||
@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un6_fe_npc_2[29:0]' | ||||
@N: MF176 |Default generator successful | ||||
@N: MF176 |Default generator successful | ||||
@N: MF176 |Default generator successful | ||||
@N: MF176 |Default generator successful | ||||
@N: MF179 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":392:9:392:30|Found 4 bit by 4 bit '<' comparator, 'comb\.irq_trap\.op_gt\.un2_irl' | ||||
Encoding state machine gaisler.mmu_icache(rtl)-r\.istate[0:2] | ||||
original code -> new code | ||||
00 -> 00 | ||||
10 -> 01 | ||||
11 -> 10 | ||||
@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 8 bit incrementor, 'un1_r\.faddr[1:8]' | ||||
Encoding state machine gaisler.mmu_dcache(rtl)-r\.dstate[0:5] | ||||
original code -> new code | ||||
000000001 -> 000001 | ||||
000000010 -> 000010 | ||||
000001000 -> 000100 | ||||
001000000 -> 001000 | ||||
010000000 -> 010000 | ||||
100000000 -> 100000 | ||||
@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 8 bit incrementor, 'un1_r\.faddr[1:8]' | ||||
@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Found counter in view:gaisler.dsu3x(rtl) inst r\.cnt[2:0] | ||||
@N: MF176 |Default generator successful | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Sequential instance l3.dsugen.dsu0.x0.r.dsuen[0] has been reduced to a combinational gate by constant propagation | ||||
Encoding state machine lpp.ssram_plugin(ar_ssram_plugin)-state[0:4] | ||||
original code -> new code | ||||
00001 -> 00001 | ||||
00010 -> 00010 | ||||
00100 -> 00100 | ||||
01000 -> 01000 | ||||
10000 -> 10000 | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\ssram_plugin.vhd":99:12:99:22|Removing sequential instance state[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
Encoding state machine gaisler.dcom_uart(rtl)-r\.txstate[0:2] | ||||
original code -> new code | ||||
00 -> 00 | ||||
01 -> 01 | ||||
10 -> 10 | ||||
Encoding state machine gaisler.dcom_uart(rtl)-r\.rxstate[0:3] | ||||
original code -> new code | ||||
00 -> 00 | ||||
01 -> 01 | ||||
10 -> 10 | ||||
11 -> 11 | ||||
@N: MF179 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":392:9:392:30|Found 14 bit by 14 bit '<' comparator, 'uartop\.op_gt\.v\.brate2' | ||||
Encoding state machine gaisler.dcom(struct)-r\.state[0:5] | ||||
original code -> new code | ||||
000001 -> 000001 | ||||
000010 -> 000010 | ||||
000100 -> 000100 | ||||
001000 -> 001000 | ||||
010000 -> 010000 | ||||
100000 -> 100000 | ||||
@N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 6 bit decrementor, 'un5_newlen[5:0]' | ||||
@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un5_newaddr[29:0]' | ||||
Encoding state machine grlib.apbctrl(rtl)-r\.state[0:2] | ||||
original code -> new code | ||||
00 -> 00 | ||||
01 -> 01 | ||||
10 -> 10 | ||||
@N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 9 bit decrementor, 'un6_scaler[8:0]' | ||||
@N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 32 bit decrementor, 'un12_res[31:0]' | ||||
Encoding state machine gaisler.apbuart(rtl)-r\.txstate[0:3] | ||||
original code -> new code | ||||
00 -> 00 | ||||
01 -> 01 | ||||
10 -> 10 | ||||
11 -> 11 | ||||
Encoding state machine gaisler.apbuart(rtl)-r\.rxstate[0:4] | ||||
original code -> new code | ||||
00001 -> 00001 | ||||
00010 -> 00010 | ||||
00100 -> 00100 | ||||
01000 -> 01000 | ||||
10000 -> 10000 | ||||
@N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 12 bit decrementor, 'un4_scaler[11:0]' | ||||
@N: MF176 |Default generator successful | ||||
@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Sequential instance ua1.uart1.r.ctsn[0] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance SRAM.inf.x0.rfd_tile.DIN_REG1[16] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd":133:9:133:11|Sequential instance SRAM.inf.x0.rfd_tile.DIN_REG1[17] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Sequential instance arith.MACinst.CTRL.Q[1] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Sequential instance arith.MACinst.MACMUXselREG.Q[0] has been reduced to a combinational gate by constant propagation | ||||
@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Sequential instance arith.MACinst.MACMUX2selREG.Q[0] has been reduced to a combinational gate by constant propagation | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.iosn[1] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.iosn[0] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[31] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[30] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[29] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[28] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[27] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[26] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[25] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[24] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[23] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[22] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[21] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[20] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[19] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[18] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[17] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[16] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[15] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[14] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[13] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[12] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[11] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[10] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[9] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[8] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[7] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[6] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[5] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[4] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[3] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[2] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[1] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.rbdrive[0] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.romsn[1] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.romsn[0] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramsn[3] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Boundary register memctrlr.r\.ramsn[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramsn[2] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Boundary register memctrlr.r\.ramsn[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramsn[1] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Boundary register memctrlr.r\.ramsn[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramoen[3] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramoen[2] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramoen[1] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance memctrlr.r\.ramoen[0] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance memctrlr.r\.mben[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance memctrlr.r\.mben[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance memctrlr.r\.mben[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance memctrlr.r\.mben[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[3], because it is equivalent to instance ahb0.r.hrdatas[2] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatam[24], because it is equivalent to instance ahb0.r.hrdatam[13] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatam[13], because it is equivalent to instance ahb0.r.hrdatam[12] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\apb_uart.vhd":142:20:142:21|Removing sequential instance COM0.apbo.prdata[17], because it is equivalent to instance COM0.apbo.prdata[13] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[6], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[7], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[8], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[9], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[11], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[10], because it is equivalent to instance ahb0.r.hrdatas[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[17], because it is equivalent to instance ahb0.r.hrdatas[16] | ||||
Auto Dissolve of SM (inst of view:lpp.SpectralMatrix(ar_spectralmatrix)) | ||||
Finished factoring (Time elapsed 0h:00m:28s; Memory used current: 153MB peak: 154MB) | ||||
@W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Register bit ahb0.r\.hslave[2] is always 0, optimizing ... | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Removing sequential instance ua1\.uart1.r\.rtsn of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\misc\gptimer.vhd":282:8:282:9|Removing sequential instance gpt\.timer0.r\.wdog of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\misc\gptimer.vhd":282:8:282:9|Removing sequential instance gpt\.timer0.r\.wdogn of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\apbctrl.vhd":222:8:222:9|Removing sequential instance apb0.r\.haddr[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\grlib\amba\apbctrl.vhd":222:8:222:9|Removing sequential instance apb0.r\.haddr[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\misc\ahbmst.vhd":166:10:166:11|Removing sequential instance dcomgen\.dcom0.ahbmst0.r\.start of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":316:8:316:9|Removing sequential instance irqctrl\.irqctrl0.r\.cpurst[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\irqmp.vhd":316:8:316:9|Boundary register irqctrl\.irqctrl0.r\.cpurst[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Removing sequential instance l3\.dsugen\.dsu0.x0.r\.pwd[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[31] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[30] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[29] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[28] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[27] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[26] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[25] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[24] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[23] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[22] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[21] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[20] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[19] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[18] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[17] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[14] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[13] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[12] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[11] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[10] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[9] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[8] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[7] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[6] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[5] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.asi[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.asi[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.diag_op of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dlock of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.su of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.icache0.r\.su of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[31] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[30] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[29] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[28] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[27] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[26] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[25] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[24] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[23] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[22] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[21] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[20] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[19] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[18] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[17] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[14] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[13] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[12] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[11] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[10] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[9] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[8] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[7] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[6] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[5] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[18] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[17] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[14] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[13] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[12] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[11] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[10] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[9] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[8] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[7] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[6] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[5] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[13] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[12] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[11] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[10] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.dci\.asi[7] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.dci\.asi[6] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.dci\.asi[5] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[18] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[17] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[14] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[13] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[12] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[11] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[10] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[9] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[8] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[7] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[6] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[5] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.cnt[1] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.cnt[0] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.su of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[8] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[8] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[7] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[7] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[6] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[6] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[5] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[5] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[4] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[4] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[3] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[2] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[1] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.TX_REG.Q_1[0] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.TX_REG.Q_1[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.RX_REG.Q_1[9] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.RX_REG.Q_1[9] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.RX_REG.Q_1[0] of view:PrimLib.dffrs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.RX_REG.Q_1[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.RX_REG.SOUT of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.RX_REG.SOUT has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Removing sequential instance COM0.COM0.RX_REG.REG[0] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_uart\shift_reg.vhd":61:4:61:5|Boundary register COM0.COM0.RX_REG.REG[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[31] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[30] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[29] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[28] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[27] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[26] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[25] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[24] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[23] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[22] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[21] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[20] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[19] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[18] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[17] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[16] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[15] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[14] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[13] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[12] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[11] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[10] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[9] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[8] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[7] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[6] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[5] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[4] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[3] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[2] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.MULToutREG.Q[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[15] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[14] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[13] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[12] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[11] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[10] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[9] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[8] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[7] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[6] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[5] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[4] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[3] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[2] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP2REG.Q[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[15] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[14] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[13] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[12] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[11] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[10] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[9] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[8] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[7] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[6] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[5] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[4] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[3] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[2] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\general_purpose\mac_reg.vhd":46:0:46:1|Removing sequential instance SM.CALC0.ALU.arith\.MACinst.OP1REG.Q[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":54:4:54:5|Removing sequential instance FFT.postBflySw_0.validOut_xhdl3 of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":54:4:54:5|Removing sequential instance FFT.postBflySw_0.pipe1 of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftsm.vhd":338:4:338:5|Removing sequential instance FFT.smTop_0.inBuf_wA_0.fftDone_int of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftsm.vhd":338:4:338:5|Removing sequential instance FFT.smTop_0.inBuf_wA_0.swCross_int of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\driver_fft.vhd":61:8:61:9|Removing sequential instance DRIVE.Read[4] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\driver_fft.vhd":61:8:61:9|Removing sequential instance DRIVE.Read[3] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\driver_fft.vhd":61:8:61:9|Removing sequential instance DRIVE.Read[2] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\driver_fft.vhd":61:8:61:9|Removing sequential instance DRIVE.Read[1] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\driver_fft.vhd":61:8:61:9|Removing sequential instance DRIVE.Read[0] of view:PrimLib.dffs(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_ad_conv\writegen_adc.vhd":50:8:50:9|Removing sequential instance WG.ReUse_reg[4] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_ad_conv\writegen_adc.vhd":50:8:50:9|Removing sequential instance WG.ReUse_reg[3] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_ad_conv\writegen_adc.vhd":50:8:50:9|Removing sequential instance WG.ReUse_reg[2] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_ad_conv\writegen_adc.vhd":50:8:50:9|Removing sequential instance WG.ReUse_reg[1] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_ad_conv\writegen_adc.vhd":50:8:50:9|Removing sequential instance WG.ReUse_reg[0] of view:PrimLib.dffr(prim) because there are no references to its outputs | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Removing sequential instance dcomgen.dcom0.dcom_uart0.r.rxf[0], because it is equivalent to instance ua1.uart1.r.rxf[0] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[0], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[0] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[1], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[1] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[2], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[2] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[3], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[3] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[4], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[5], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[5] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[6], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[6] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[0], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[0] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[1], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[1] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[2], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[2] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[3], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[3] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[4], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[5], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[5] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[6], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[6] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[0], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[0] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[1], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[1] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[2], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[2] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[3], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[3] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[4], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[5], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[5] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[6], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[6] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[7], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[7] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[8], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[8] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[9], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[9] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[10], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[10] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[11], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[11] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[12], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[12] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[13], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[13] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[14], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[14] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[15], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[15] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[16], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[16] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[17], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[17] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[18], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[18] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[19], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[19] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[20], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[20] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[21], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[21] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[22], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[22] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[23], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[23] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[24], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[24] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[25], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[25] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[26], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[26] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[27], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[27] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[28], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[28] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[29], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[29] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[30], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[30] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[31], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[31] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.renable, because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfe2 | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.write, because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.write | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Removing sequential instance ua1.uart1.r.rxf[1], because it is equivalent to instance dcomgen.dcom0.dcom_uart0.r.rxf[1] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd":127:4:127:5|Removing sequential instance FFT.smTop_0.outBufA_0.fedge_0.in_t1, because it is equivalent to instance FFT.outBuff_0.wEn_r | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[0], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[0] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[1], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[1] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[2], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[2] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[3], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[3] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[4], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[5], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[5] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[6], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[6] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[7], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[7] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[8], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[8] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[9], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[9] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[10], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[10] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[11], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[11] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[12], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[12] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[13], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[13] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[14], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[14] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.t_r[15], because it is equivalent to instance FFT.bfly_0.am3QiTr.t_r[15] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[0], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[0] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[1], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[1] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[2], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[2] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[3], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[3] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[4], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[5], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[5] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[6], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[6] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[7], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[7] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[8], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[8] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[9], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[9] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[10], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[10] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[11], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[11] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[12], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[12] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[13], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[13] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[14], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[14] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTi.t_r[15], because it is equivalent to instance FFT.bfly_0.am3QiTi.t_r[15] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[0], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[0] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[1], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[1] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[2], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[2] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[3], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[3] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[4], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[5], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[5] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[6], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[6] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[7], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[7] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[8], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[8] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[9], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[9] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[10], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[10] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[11], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[11] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[12], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[12] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[13], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[13] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[14], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[14] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QrTr.a_r[15], because it is equivalent to instance FFT.bfly_0.am3QrTi.a_r[15] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[0], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[0] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[1], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[1] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[2], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[2] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[3], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[3] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[4], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[4] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[5], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[5] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[6], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[6] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[7], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[7] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[8], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[8] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[9], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[9] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[10], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[10] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[11], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[11] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[12], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[12] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[13], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[13] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[14], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[14] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":168:4:168:5|Removing sequential instance FFT.bfly_0.am3QiTr.a_r[15], because it is equivalent to instance FFT.bfly_0.am3QiTi.a_r[15] | ||||
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:30s; Memory used current: 157MB peak: 161MB) | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":206:18:206:55|Removing sequential instance MemIn.apbo\.prdata[28] of view:PrimLib.lat(prim) because there are no references to its outputs | ||||
@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\lpp_memory\apb_fifo.vhd":193:24:193:25|Removing sequential instance MemIn.PRdata[28] of view:PrimLib.dff(prim) because there are no references to its outputs | ||||
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:42s; Memory used current: 152MB peak: 162MB) | ||||
Starting Early Timing Optimization (Time elapsed 0h:00m:45s; Memory used current: 156MB peak: 162MB) | ||||
Finished Early Timing Optimization (Time elapsed 0h:01m:45s; Memory used current: 165MB peak: 166MB) | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT.bfly_0.outQ_xhdl2[16], because it is equivalent to instance FFT.bfly_0.outP_xhdl1[16] | ||||
@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-leonlfr-a3p3k-sheldon\..\..\lib\lpp\.\dsp\lpp_fft\fftdp.vhd":276:4:276:5|Removing sequential instance FFT.bfly_0.outQ_xhdl2[0], because it is equivalent to instance FFT.bfly_0.outP_xhdl1[0] | ||||
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:01m:47s; Memory used current: 162MB peak: 167MB) | ||||
Finished preparing to map (Time elapsed 0h:02m:09s; Memory used current: 217MB peak: 219MB) | ||||
High Fanout Net Report | ||||
********************** | ||||
Driver Instance / Pin Name Fanout, notes | ||||
---------------------------------------------------------------------------------------------------------------------------------- | ||||
rst0.rstoutl / Q 1052 : 770 asynchronous set/reset | ||||
FFT.smTop_0.smPong_xhdl14 / Q 211 | ||||
ahb0.r.hmaster[0] / Q 42 | ||||
apb0.r.haddr[2] / Q 163 | ||||
apb0.r.haddr[3] / Q 105 | ||||
apb0.r.haddr[4] / Q 28 | ||||
apb0.r.haddr[5] / Q 33 | ||||
apb0.r.pwdata[0] / Q 26 | ||||
apb0.r.pwdata[1] / Q 37 | ||||
apb0.r.pwdata[2] / Q 29 | ||||
apb0.r.pwdata[3] / Q 31 | ||||
apb0.r.pwdata[4] / Q 32 | ||||
apb0.r.pwdata[5] / Q 30 | ||||
apb0.r.pwdata[6] / Q 28 | ||||
ahb0.r.hmasterd[0] / Q 34 | ||||
memctrlr.v.writedata_0_sqmuxa / Y 32 | ||||
l3.cpu.0.u0.rst / Q 161 | ||||
l3.cpu.0.u0.p0.holdn / Y 806 | ||||
l3.cpu.0.u0.p0.c0mmu.icache0.r.flush2 / Q 35 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.r.flush / Q 47 | ||||
l3.cpu.0.u0.p0.iu0.comb.v.x.annul_all_1 / Y 29 | ||||
l3.cpu.0.u0.p0.iu0.r.d.inst_0[12] / Q 27 | ||||
l3.cpu.0.u0.p0.iu0.r.d.inst_0[21] / Q 33 | ||||
l3.cpu.0.u0.p0.iu0.r.d.inst_0[30] / Q 27 | ||||
l3.cpu.0.u0.p0.iu0.r.a.ctrl.inst[22] / Q 25 | ||||
l3.cpu.0.u0.p0.iu0.r.a.ctrl.inst[24] / Q 27 | ||||
l3.cpu.0.u0.p0.iu0.r.m.dci.dsuen / Q 29 | ||||
l3.cpu.0.u0.p0.c0mmu.icache0.r.istate_tr3_1 / Y 39 | ||||
Delay0.Rdata_0_sqmuxa_0_a3 / Y 26 | ||||
COM0.Send / Q 29 : 13 asynchronous set/reset | ||||
MemOut.un1_rst_inv_0_0_0 / Y 28 | ||||
COM0.COM0.Take / Q 36 : 20 asynchronous set/reset | ||||
COM0.COM0.RX_REG.Serialized_int / Q 25 | ||||
SM.RaZ_i_s / Y 185 : 182 asynchronous set/reset | ||||
ahb0.un1_acdm_0_0_o2_0_a2[69] / Y 34 | ||||
Delay0.un1_Rec.Delay_CFG_0_iv_0_0_i_o3[2] / Y 31 | ||||
gpt.timer0.r.tsel[0] / Q 37 | ||||
gpt.timer0.comb.1.readdata_9_sn_m3 / Y 32 | ||||
gpt.timer0.v.timers_2.value_0_sqmuxa / Y 33 | ||||
gpt.timer0.readdata_1_sqmuxa_1 / Y 33 | ||||
apb0.r.cfgsel / Q 30 | ||||
apb0.nslave_0_a4_0_a2[3] / Y 181 | ||||
apb0.nslave_i_0_i_0_a2[1] / Y 95 | ||||
apb0.N_45_i_0_a2 / Y 59 | ||||
apb0.nslave_i_i[0] / Y 30 | ||||
apb0.v.pwdata_1_sqmuxa_i_i_a2 / Y 32 | ||||
dcomgen.dcom0.dcom0.r.state[4] / Q 38 | ||||
dcomgen.dcom0.dcom0.r.state[3] / Q 36 | ||||
dcomgen.dcom0.dcom0.un1_v.data_0_sqmuxa_0_0 / Y 32 | ||||
dcomgen.dcom0.dcom_uart0.uartop.tmp_i_o5 / Y 60 | ||||
l3.dsugen.dsu0.x0.un1_v.cnt3_2_1 / Y 32 | ||||
l3.dsugen.dsu0.x0.comb.v.slv.hready33_0_o3 / Y 33 | ||||
l3.dsugen.dsu0.x0.v.slv.hwrite_0_sqmuxa_i_0_o2 / Y 32 | ||||
l3.dsugen.dsu0.x0.v.bmsk_1_sqmuxa_2_i_o2 / Y 35 | ||||
l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp / Y 32 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate[4] / Q 64 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.read_0_sqmuxa_1 / Y 35 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.wb.data2_0_sqmuxa / Y 71 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.rdatav_0_5_sqmuxa / Y 32 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.rdatav_0_1_sqmuxa_1 / Y 32 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate_tr0_0 / Y 38 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate_i[5] / Q 30 | ||||
l3.cpu.0.u0.p0.c0mmu.icache0.diagen_0_sqmuxa / Y 40 | ||||
l3.cpu.0.u0.p0.c0mmu.icache0.r.istate[0] / Q 45 | ||||
l3.cpu.0.u0.p0.c0mmu.icache0.v.vaddress_0_sqmuxa_0_a2 / Y 60 | ||||
l3.cpu.0.u0.p0.iu0.r.e.ctrl.wy / Q 68 | ||||
l3.cpu.0.u0.p0.iu0.r.x.npc[0] / Q 35 | ||||
l3.cpu.0.u0.p0.iu0.r.x.npc[1] / Q 64 | ||||
l3.cpu.0.u0.p0.iu0.r.a.rsel1[0] / Q 34 | ||||
l3.cpu.0.u0.p0.iu0.r.a.rsel1[1] / Q 65 | ||||
l3.cpu.0.u0.p0.iu0.r.a.rsel1[2] / Q 96 | ||||
l3.cpu.0.u0.p0.iu0.r.e.aluop[0] / Q 41 | ||||
l3.cpu.0.u0.p0.iu0.r.e.aluop[1] / Q 68 | ||||
l3.cpu.0.u0.p0.iu0.r.e.aluop[2] / Q 43 | ||||
l3.cpu.0.u0.p0.iu0.r.a.rsel2[0] / Q 33 | ||||
l3.cpu.0.u0.p0.iu0.r.a.rsel2[1] / Q 65 | ||||
l3.cpu.0.u0.p0.iu0.r.a.rsel2[2] / Q 97 | ||||
l3.cpu.0.u0.p0.iu0.r.e.ldbp2 / Q 71 | ||||
l3.cpu.0.u0.p0.iu0.r.e.invop2 / Q 64 | ||||
l3.cpu.0.u0.p0.iu0.comb.diagread.un497_dbgunit / Y 34 | ||||
l3.cpu.0.u0.p0.iu0.r.e.mulstep / Q 33 | ||||
l3.cpu.0.u0.p0.iu0.r.x.ctrl.ld / Q 33 | ||||
l3.cpu.0.u0.p0.iu0.r.e.ldbp1 / Q 144 | ||||
l3.cpu.0.u0.p0.iu0.comb.lock_gen.call_hold5_0_a2 / Y 37 | ||||
l3.cpu.0.u0.p0.iu0.comb.alu_op.y08 / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.un1_r.e.ctrl.wy_2 / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.data_0_sqmuxa / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.aluresult_0_sqmuxa_0_a2 / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.aluresult_3_sqmuxa_0_a2 / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.aluresult_6_sqmuxa_0_a2 / Y 25 | ||||
l3.cpu.0.u0.p0.iu0.aluresult_10_sqmuxa / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.r.e.shleft / Q 63 | ||||
l3.cpu.0.u0.p0.iu0.aluresult_12_sqmuxa_0_a2 / Y 28 | ||||
l3.cpu.0.u0.p0.iu0.fpcwr_6_sqmuxa / Y 29 | ||||
l3.cpu.0.u0.p0.iu0.data_0_sqmuxa_2 / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.data_3_sqmuxa_1 / Y 28 | ||||
l3.cpu.0.u0.p0.iu0.data_4_sqmuxa_1 / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.data_5_sqmuxa_1 / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.mresult2_1_sqmuxa_0_a2 / Y 31 | ||||
l3.cpu.0.u0.p0.iu0.mresult2_2_sqmuxa_1_0_a2 / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.v.w.s.s_3_sqmuxa / Y 40 | ||||
l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_12 / Y 39 | ||||
l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_14 / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.comb.de_hold_pc / Y 52 | ||||
l3.cpu.0.u0.p0.iu0.un2_de_hold_pc_0_a3_m1_e / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.un1_ico / Y 33 | ||||
l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_2_s3_1_a2 / Y 29 | ||||
l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_0_s1_1_a2 / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.un2_rstn_7_0_a2 / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.r.x.rstate[1] / Q 35 | ||||
l3.cpu.0.u0.p0.iu0.r.x.rstate_li_i_0_i2_0_a2[0] / Y 63 | ||||
l3.cpu.0.u0.p0.iu0.un1_r.e.jmpl_i_o2 / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.r.x.rstate_s1_0_a2_i_o2 / Y 38 | ||||
l3.cpu.0.u0.p0.iu0.aop2_2_sqmuxa / Y 33 | ||||
Delay0.Delay0.compt_1_sqmuxa_i_o2 / Y 26 | ||||
SM.CALC0.ALU.un1_clr_mac / Y 33 | ||||
SM.CALC0.ALU.arith.MACinst.CTRL.Q[0] / Q 33 | ||||
SM.CALC0.ALU.arith.MACinst.clr_MACREG2.Q[0] / Q 33 | ||||
FFT.smTop_0.twid_wA_0.slowTimer.Q_out[3] / Q 100 | ||||
FFT.smTop_0.twid_wA_0.slowTimer.Q_out[4] / Q 87 | ||||
FFT.smTop_0.twid_wA_0.slowTimer.Q_out[5] / Q 84 | ||||
FFT.smTop_0.twid_wA_0.slowTimer.Q_out[6] / Q 128 | ||||
FFT.smTop_0.twid_wA_0.slowTimer.Q_out[7] / Q 79 | ||||
FFT.smTop_0.twid_wA_0.slowTimer.Q_out[8] / Q 50 | ||||
FFT.smTop_0.twid_wA_0.slowTimer.Q_out[9] / Q 36 | ||||
FFT.smTop_0.inBuf_rA_0.swCross_int / Q 65 | ||||
FFT.autoScale_0.upScale_xhdl1 / Q 62 | ||||
FFT.bfly_0.swCrossOut_xhdl4 / Q 64 | ||||
FFT.outBuff_0.rAmsb_r2 / Q 32 | ||||
FFT.bfly_0.am3QiTr.t_r[0] / Q 44 | ||||
FFT.bfly_0.am3QiTr.t_r[3] / Q 26 | ||||
FFT.bfly_0.am3QiTr.t_r[5] / Q 26 | ||||
FFT.bfly_0.am3QiTr.t_r[7] / Q 26 | ||||
FFT.bfly_0.am3QiTr.t_r[9] / Q 26 | ||||
FFT.bfly_0.am3QiTr.t_r[11] / Q 26 | ||||
FFT.bfly_0.am3QiTr.t_r[13] / Q 26 | ||||
FFT.bfly_0.am3QiTi.t_r[0] / Q 44 | ||||
FFT.bfly_0.am3QiTi.t_r[3] / Q 26 | ||||
FFT.bfly_0.am3QiTi.t_r[5] / Q 26 | ||||
FFT.bfly_0.am3QiTi.t_r[7] / Q 26 | ||||
FFT.bfly_0.am3QiTi.t_r[9] / Q 26 | ||||
FFT.bfly_0.am3QiTi.t_r[11] / Q 26 | ||||
FFT.bfly_0.am3QiTi.t_r[13] / Q 26 | ||||
FFT.smTop_0.nGrst_i_s / Y 52 : 52 asynchronous set/reset | ||||
ADC.reset / Y 96 : 94 asynchronous set/reset | ||||
l3.cpu.0.u0.p0.iu0.edata_3_sqmuxa / Y 32 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s0 / Y 32 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s1 / Y 32 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.read_1 / Y 38 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.mexc_0_sqmuxa / Y 32 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.rdatasel_1_1 / Y 32 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.v.hit2 / Y 39 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.data1_0_sqmuxa_i_o2 / Y 33 | ||||
l3.cpu.0.u0.p0.iu0.comb.ex_sari_1_1_i / Y 31 | ||||
l3.cpu.0.u0.p0.iu0.un1_aop2_1_sqmuxa / Y 33 | ||||
l3.cpu.0.u0.p0.iu0.comb.misc_op.bpdata6 / Y 32 | ||||
ADC.spidrvr.DataReady_1_sqmuxa_i / Y 81 | ||||
ADC.spidrvr.smpout_0_1_sqmuxa_0_a3 / Y 80 | ||||
l3.cpu.0.u0.p0.iu0.r.x.mexc_1_sqmuxa / Y 34 | ||||
l3.cpu.0.u0.p0.iu0.comb.un1_r.m.ctrl.ld / Y 38 | ||||
l3.cpu.0.u0.p0.iu0.aluresult_1_sqmuxa / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.aluresult_2_sqmuxa / Y 32 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.wb.data2_0_sqmuxa_1 / Y 36 | ||||
l3.cpu.0.u0.p0.iu0.aluresult_7_sqmuxa_0_a2 / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.comb.v.x.annul_all2 / Y 83 | ||||
l3.cpu.0.u0.p0.iu0.r.x.rstate_tr4_1 / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.fpcwr_0_sqmuxa_1 / Y 33 | ||||
l3.cpu.0.u0.p0.iu0.fpcwr_0_sqmuxa / Y 38 | ||||
memctrlr.v.ramoen_0_sqmuxa_0_m3 / Y 43 | ||||
dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_2[2] / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.comb.un6_xc_exception_i / Y 33 | ||||
l3.cpu.0.u0.p0.iu0.comb.v.f.pc_0_a2_10_m2 / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.comb.ra_bpmiss_1 / Y 33 | ||||
l3.cpu.0.u0.p0.iu0.comb.ex_bpmiss / Y 43 | ||||
l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_3 / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.xc_trap_address_1_sqmuxa / Y 31 | ||||
l3.cpu.0.u0.p0.iu0.comb.dcache_gen.jump_0_a2 / Y 29 | ||||
l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[1] / Y 37 | ||||
l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[0] / Y 38 | ||||
l3.cpu.0.u0.p0.iu0.vir.addr_1_sqmuxa / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.vir.addr_2_sqmuxa / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.vir.addr_3_sqmuxa / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.un1_vir.addr_0_sqmuxa / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_6 / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.fpcwr_8_sqmuxa / Y 30 | ||||
memctrlr.v.address_1_sqmuxa / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.aop1_1_sqmuxa / Y 34 | ||||
dcomgen.dcom0.dcom0.un1_r.state_4_0_0_0 / Y 31 | ||||
dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_3[2] / Y 30 | ||||
l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.pc_1_sqmuxa / Y 31 | ||||
l3.cpu.0.u0.p0.iu0.comb.logic_op.y14 / Y 32 | ||||
SM.CALC0.DRIVE.OP1im_1_sqmuxa / Y 32 | ||||
TopSM.Read_0_0_a2_0_0_a2[4] / Y 37 | ||||
SM.RES0.un1_Received_0_sqmuxa_0_a2_0_a2 / Y 33 | ||||
SM.CALC0.ALU.arith.MACinst.adder_inst.un1_add / Y 32 | ||||
SM.CALC0.DRIVE.un1_reset_inv / Y 32 | ||||
SM.CALC0.DRIVE.OP1re_1_sqmuxa / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.comb.un16_casaen_0 / Y 92 | ||||
l3.cpu.0.u0.p0.c0mmu.dcache0.wlock_1_sqmuxa_i_o3_0_tz / Y 30 | ||||
l3.cpu.0.u0.p0.iu0.xc_trap_address_2_sqmuxa_0 / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.icc_0_sqmuxa_1_27_a2_2_0 / Y 25 | ||||
l3.cpu.0.u0.p0.iu0.N_5623_m_0_0 / Y 40 | ||||
gpt.timer0.comb.v.timers_1.value_1_sn_m1_0_a2 / Y 32 | ||||
gpt.timer0.comb.v.timers_2.value_1_sn_m1_0_a2 / Y 32 | ||||
l3.cpu.0.u0.p0.c0mmu.icache0.cdwrite_0_sqmuxa / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.aluresult_8_sqmuxa_0_a2 / Y 25 | ||||
l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[1] / Y 33 | ||||
l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[2] / Y 35 | ||||
l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[3] / Y 39 | ||||
l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[4] / Y 47 | ||||
l3.cpu.0.u0.p0.iu0.r.d.pc_1198_e / Y 31 | ||||
l3.dsugen.dsu0.x0.un1_v.cnt3_i_a2_m2_e / Y 31 | ||||
l3.cpu.0.u0.p0.iu0.un1_r.e.ctrl.wy_1_0 / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.v.w.s.y_1_sqmuxa_0 / Y 32 | ||||
l3.cpu.0.u0.p0.iu0.v.w.s.y_2_sqmuxa_1 / Y 32 | ||||
================================================================================================================================== | ||||
@N: FP130 |Promoting Net lclk_c_c on CLKINT lclk_inferred_clock | ||||
@N: FP130 |Promoting Net rstn on CLKINT I_1723 | ||||
@N: FP130 |Promoting Net l3\.cpu\.0\.u0.holdn on CLKINT I_1724 | ||||
@N: FP130 |Promoting Net apbi\.penable on CLKINT apb0.r\.penable_inferred_clock | ||||
@N: FP130 |Promoting Net un1_FFT on CLKINT I_1725 | ||||
@N: FP130 |Promoting Net SM.IN1.raz_i_1 on CLKINT I_1726 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.v.w.s.y_2_sqmuxa_1, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.v.w.s.y_1_sqmuxa_0, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.e.ctrl.wy_1_0, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.dsugen.dsu0.x0.un1_v.cnt3_i_a2_m2_e, fanout 31 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.d.pc_1198_e, fanout 31 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[4], fanout 47 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[3], fanout 39 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[2], fanout 35 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[1], fanout 33 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_8_sqmuxa_0_a2, fanout 25 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.cdwrite_0_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance gpt.timer0.comb.v.timers_2.value_1_sn_m1_0_a2, fanout 32 segments 2 | ||||
Replicating Combinational Instance gpt.timer0.comb.v.timers_1.value_1_sn_m1_0_a2, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.N_5623_m_0_0, fanout 40 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.icc_0_sqmuxa_1_27_a2_2_0, fanout 25 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.xc_trap_address_2_sqmuxa_0, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.wlock_1_sqmuxa_i_o3_0_tz, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.un16_casaen_0, fanout 92 segments 4 | ||||
Replicating Combinational Instance SM.CALC0.DRIVE.OP1re_1_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance SM.CALC0.DRIVE.un1_reset_inv, fanout 32 segments 2 | ||||
Replicating Combinational Instance SM.CALC0.ALU.arith.MACinst.adder_inst.un1_add, fanout 32 segments 2 | ||||
Replicating Combinational Instance SM.RES0.un1_Received_0_sqmuxa_0_a2_0_a2, fanout 33 segments 2 | ||||
Replicating Combinational Instance TopSM.Read_0_0_a2_0_0_a2[4], fanout 37 segments 2 | ||||
Replicating Combinational Instance SM.CALC0.DRIVE.OP1im_1_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.logic_op.y14, fanout 32 segments 2 | ||||
Replicating Combinational Instance Delay0.Rec.Delay_FreqBoard_1_sqmuxa_0_a3_i_i_a3, fanout 26 segments 2 | ||||
Replicating Combinational Instance ua1.uart1.v.brate_1_sqmuxa_0_a2, fanout 25 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.pc_1_sqmuxa, fanout 31 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp, fanout 32 segments 2 | ||||
Replicating Combinational Instance dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_3[2], fanout 30 segments 2 | ||||
Replicating Combinational Instance dcomgen.dcom0.dcom0.un1_r.state_4_0_0_0, fanout 31 segments 2 | ||||
Replicating Combinational Instance dcomgen.dcom0.dcom_uart0.v.brate_0_sqmuxa, fanout 38 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aop1_1_sqmuxa, fanout 34 segments 2 | ||||
Replicating Combinational Instance memctrlr.v.address_1_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.fpcwr_8_sqmuxa, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_6, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_vir.addr_0_sqmuxa, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.vir.addr_3_sqmuxa, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.vir.addr_2_sqmuxa, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.vir.addr_1_sqmuxa, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[0], fanout 38 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[1], fanout 37 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.dcache_gen.jump_0_a2, fanout 29 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.xc_trap_address_1_sqmuxa, fanout 31 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_3, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_bpmiss, fanout 43 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ra_bpmiss_1, fanout 33 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.v.f.pc_0_a2_10_m2, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.un6_xc_exception_i, fanout 33 segments 2 | ||||
Replicating Combinational Instance dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_2[2], fanout 30 segments 2 | ||||
Replicating Combinational Instance gpt.timer0.v.timers_2.value_1_sqmuxa, fanout 33 segments 2 | ||||
Replicating Combinational Instance gpt.timer0.v.timers_1.value_1_sqmuxa, fanout 33 segments 2 | ||||
Replicating Combinational Instance gpt.timer0.v.timers_2.value_2_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance gpt.timer0.v.timers_1.value_2_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance gpt.timer0.v.timers_2.reload_1_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance gpt.timer0.v.timers_1.reload_1_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance memctrlr.v.ramoen_0_sqmuxa_0_m3, fanout 43 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.fpcwr_0_sqmuxa, fanout 39 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.fpcwr_0_sqmuxa_1, fanout 33 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.x.rstate_tr4_1, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.v.x.annul_all2, fanout 83 segments 4 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_7_sqmuxa_0_a2, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.wb.data2_0_sqmuxa_1, fanout 36 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_2_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_1_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.un1_r.m.ctrl.ld, fanout 38 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.x.mexc_1_sqmuxa, fanout 34 segments 2 | ||||
Replicating Combinational Instance ADC.spidrvr.smpout_0_1_sqmuxa_0_a3, fanout 80 segments 4 | ||||
Replicating Combinational Instance ADC.spidrvr.DataReady_1_sqmuxa_i, fanout 81 segments 4 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.misc_op.bpdata6, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_aop2_1_sqmuxa, fanout 33 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_sari_1_1_i, fanout 31 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.data1_0_sqmuxa_i_o2, fanout 33 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.v.hit2, fanout 39 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.rdatasel_1_1, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.mexc_0_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.read_1, fanout 38 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s1, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s0, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.edata_3_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance ADC.reset, fanout 99 segments 5 | ||||
Replicating Combinational Instance FFT.smTop_0.nGrst_i_s, fanout 52 segments 3 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTi.t_r[13], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTi.t_r[11], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTi.t_r[9], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTi.t_r[7], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTi.t_r[5], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTi.t_r[3], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTi.t_r[0], fanout 44 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTr.t_r[13], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTr.t_r[11], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTr.t_r[9], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTr.t_r[7], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTr.t_r[5], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTr.t_r[3], fanout 26 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.am3QiTr.t_r[0], fanout 44 segments 2 | ||||
Replicating Sequential Instance FFT.outBuff_0.rAmsb_r2, fanout 32 segments 2 | ||||
Replicating Sequential Instance FFT.bfly_0.swCrossOut_xhdl4, fanout 64 segments 3 | ||||
Replicating Sequential Instance FFT.autoScale_0.upScale_xhdl1, fanout 62 segments 3 | ||||
Replicating Sequential Instance FFT.smTop_0.inBuf_rA_0.swCross_int, fanout 65 segments 3 | ||||
Replicating Sequential Instance FFT.smTop_0.twid_wA_0.slowTimer.Q_out[9], fanout 36 segments 2 | ||||
Replicating Sequential Instance FFT.smTop_0.twid_wA_0.slowTimer.Q_out[8], fanout 50 segments 3 | ||||
Replicating Sequential Instance FFT.smTop_0.twid_wA_0.slowTimer.Q_out[7], fanout 79 segments 4 | ||||
Replicating Sequential Instance FFT.smTop_0.twid_wA_0.slowTimer.Q_out[6], fanout 128 segments 6 | ||||
Replicating Sequential Instance FFT.smTop_0.twid_wA_0.slowTimer.Q_out[5], fanout 84 segments 4 | ||||
Replicating Sequential Instance FFT.smTop_0.twid_wA_0.slowTimer.Q_out[4], fanout 87 segments 4 | ||||
Replicating Sequential Instance FFT.smTop_0.twid_wA_0.slowTimer.Q_out[3], fanout 100 segments 5 | ||||
Replicating Sequential Instance SM.CALC0.ALU.arith.MACinst.clr_MACREG2.Q[0], fanout 34 segments 2 | ||||
Replicating Sequential Instance SM.CALC0.ALU.arith.MACinst.CTRL.Q[0], fanout 33 segments 2 | ||||
Replicating Combinational Instance SM.CALC0.ALU.un1_clr_mac, fanout 33 segments 2 | ||||
Replicating Combinational Instance Delay0.Delay0.compt_1_sqmuxa_i_o2, fanout 26 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aop2_2_sqmuxa, fanout 33 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.x.rstate_s1_0_a2_i_o2, fanout 38 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.e.jmpl_i_o2, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.x.rstate_li_i_0_i2_0_a2[0], fanout 66 segments 3 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.rstate[1], fanout 39 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un2_rstn_7_0_a2, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_0_s1_1_a2, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_2_s3_1_a2, fanout 29 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_ico, fanout 33 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un2_de_hold_pc_0_a3_m1_e, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.de_hold_pc, fanout 56 segments 3 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_14, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_12, fanout 39 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.v.w.s.s_3_sqmuxa, fanout 40 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.mresult2_2_sqmuxa_1_0_a2, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.mresult2_1_sqmuxa_0_a2, fanout 31 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_5_sqmuxa_1, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_4_sqmuxa_1, fanout 30 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_3_sqmuxa_1, fanout 28 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_0_sqmuxa_2, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.fpcwr_6_sqmuxa, fanout 29 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_12_sqmuxa_0_a2, fanout 28 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.shleft, fanout 63 segments 3 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_10_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_6_sqmuxa_0_a2, fanout 25 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_3_sqmuxa_0_a2, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_0_sqmuxa_0_a2, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_0_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.e.ctrl.wy_2, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.alu_op.y08, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.lock_gen.call_hold5_0_a2, fanout 37 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.ldbp1, fanout 145 segments 7 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.ctrl.ld, fanout 33 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.mulstep, fanout 34 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.diagread.un497_dbgunit, fanout 34 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.invop2, fanout 64 segments 3 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.ldbp2, fanout 75 segments 4 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel2[2], fanout 97 segments 5 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel2[1], fanout 65 segments 3 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel2[0], fanout 33 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.aluop[2], fanout 44 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.aluop[1], fanout 69 segments 3 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.aluop[0], fanout 41 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel1[2], fanout 96 segments 4 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel1[1], fanout 65 segments 3 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel1[0], fanout 34 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.npc[1], fanout 67 segments 3 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.npc[0], fanout 38 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.ctrl.wy, fanout 71 segments 3 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.v.vaddress_0_sqmuxa_0_a2, fanout 60 segments 3 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.icache0.r.istate[0], fanout 45 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.diagen_0_sqmuxa, fanout 41 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate_i[5], fanout 31 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate_tr0_0, fanout 38 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.rdatav_0_1_sqmuxa_1, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.rdatav_0_5_sqmuxa, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.wb.data2_0_sqmuxa, fanout 72 segments 3 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.read_0_sqmuxa_1, fanout 37 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate[4], fanout 65 segments 3 | ||||
Replicating Combinational Instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.dsugen.dsu0.x0.v.bmsk_1_sqmuxa_2_i_o2, fanout 36 segments 2 | ||||
Replicating Combinational Instance l3.dsugen.dsu0.x0.v.slv.hwrite_0_sqmuxa_i_0_o2, fanout 32 segments 2 | ||||
Replicating Combinational Instance l3.dsugen.dsu0.x0.comb.v.slv.hready33_0_o3, fanout 33 segments 2 | ||||
Replicating Combinational Instance l3.dsugen.dsu0.x0.un1_v.cnt3_2_1, fanout 32 segments 2 | ||||
Replicating Combinational Instance irqctrl.irqctrl0.v.ipend_1_sqmuxa_i_o2_0_o2, fanout 25 segments 2 | ||||
Replicating Combinational Instance dcomgen.dcom0.dcom_uart0.uartop.tmp_i_o5, fanout 60 segments 3 | ||||
Replicating Combinational Instance dcomgen.dcom0.dcom0.un1_v.data_0_sqmuxa_0_0, fanout 32 segments 2 | ||||
Replicating Sequential Instance dcomgen.dcom0.dcom0.r.state[3], fanout 36 segments 2 | ||||
Replicating Sequential Instance dcomgen.dcom0.dcom0.r.state[4], fanout 41 segments 2 | ||||
Replicating Combinational Instance apb0.v.pwdata_1_sqmuxa_i_i_a2, fanout 32 segments 2 | ||||
Replicating Combinational Instance apb0.nslave_i_i[0], fanout 30 segments 2 | ||||
Replicating Combinational Instance apb0.N_45_i_0_a2, fanout 59 segments 3 | ||||
Replicating Combinational Instance apb0.nslave_i_0_i_0_a2[1], fanout 95 segments 4 | ||||
Replicating Combinational Instance apb0.nslave_0_a4_0_a2[3], fanout 181 segments 8 | ||||
Replicating Sequential Instance apb0.r.cfgsel, fanout 30 segments 2 | ||||
Replicating Combinational Instance gpt.timer0.readdata_1_sqmuxa_1, fanout 34 segments 2 | ||||
Replicating Combinational Instance gpt.timer0.v.timers_2.value_0_sqmuxa, fanout 34 segments 2 | ||||
Replicating Combinational Instance gpt.timer0.comb.1.readdata_9_sn_m3, fanout 32 segments 2 | ||||
Replicating Sequential Instance gpt.timer0.r.tsel[0], fanout 37 segments 2 | ||||
Replicating Combinational Instance Delay0.un1_Rec.Delay_CFG_0_iv_0_0_i_o3[2], fanout 31 segments 2 | ||||
Replicating Combinational Instance ahb0.un1_acdm_0_0_o2_0_a2[69], fanout 34 segments 2 | ||||
Replicating Combinational Instance Delay0.Rec.Delay_Timer_1_sqmuxa_0_a3_i_i_a3, fanout 26 segments 2 | ||||
Replicating Sequential Instance COM0.COM0.RX_REG.Serialized_int, fanout 25 segments 2 | ||||
Replicating Sequential Instance COM0.COM0.Take, fanout 37 segments 2 | ||||
Buffering COM0.COM0.Bclk, fanout 50 segments 3 | ||||
Replicating Combinational Instance MemOut.un1_rst_inv_0_0_0, fanout 28 segments 2 | ||||
Replicating Sequential Instance COM0.Send, fanout 29 segments 2 | ||||
Replicating Combinational Instance Delay0.Rdata_0_sqmuxa_0_a3, fanout 26 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.r.istate_tr3_1, fanout 42 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.m.dci.dsuen, fanout 30 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.ctrl.inst[24], fanout 27 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.ctrl.inst[22], fanout 25 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.d.inst_0[30], fanout 28 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.d.inst_0[21], fanout 33 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.d.inst_0[12], fanout 27 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.v.x.annul_all_1, fanout 29 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.dcache0.r.flush, fanout 47 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.icache0.r.flush2, fanout 35 segments 2 | ||||
Replicating Sequential Instance l3.cpu.0.u0.rst, fanout 162 segments 7 | ||||
Replicating Combinational Instance memctrlr.v.writedata_0_sqmuxa, fanout 32 segments 2 | ||||
Replicating Sequential Instance ahb0.r.hmasterd[0], fanout 35 segments 2 | ||||
Replicating Sequential Instance apb0.r.pwdata[6], fanout 28 segments 2 | ||||
Replicating Sequential Instance apb0.r.pwdata[5], fanout 30 segments 2 | ||||
Replicating Sequential Instance apb0.r.pwdata[4], fanout 32 segments 2 | ||||
Replicating Sequential Instance apb0.r.pwdata[3], fanout 31 segments 2 | ||||
Replicating Sequential Instance apb0.r.pwdata[2], fanout 29 segments 2 | ||||
Replicating Sequential Instance apb0.r.pwdata[1], fanout 37 segments 2 | ||||
Replicating Sequential Instance apb0.r.pwdata[0], fanout 26 segments 2 | ||||
Replicating Sequential Instance apb0.r.haddr[5], fanout 33 segments 2 | ||||
Replicating Sequential Instance apb0.r.haddr[4], fanout 28 segments 2 | ||||
Replicating Sequential Instance apb0.r.haddr[3], fanout 107 segments 5 | ||||
Replicating Sequential Instance apb0.r.haddr[2], fanout 164 segments 7 | ||||
Replicating Sequential Instance ahb0.r.hmaster[0], fanout 43 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.un16_casaen_0, fanout 25 segments 2 | ||||
Replicating Combinational Instance apb0.v.hready_0_sqmuxa_0_a3_0_a2, fanout 34 segments 2 | ||||
Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.diagread.un462_dbgunit, fanout 27 segments 2 | ||||
Finished technology mapping (Time elapsed 0h:02m:22s; Memory used current: 240MB peak: 255MB) | ||||
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:02m:25s; Memory used current: 240MB peak: 255MB) | ||||
Added 2 Buffers | ||||
Added 302 Cells via replication | ||||
Added 128 Sequential Cells via replication | ||||
Added 174 Combinational Cells via replication | ||||
Finished restoring hierarchy (Time elapsed 0h:02m:28s; Memory used current: 246MB peak: 255MB) | ||||
Writing Analyst data base C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3P3K-Sheldon\synthesis\leon3mp.srm | ||||
Finished Writing Netlist Databases (Time elapsed 0h:02m:32s; Memory used current: 236MB peak: 255MB) | ||||
Writing EDIF Netlist and constraint files | ||||
E-2010.09A-1 | ||||
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:02m:36s; Memory used current: 241MB peak: 255MB) | ||||
@W: MT420 |Found inferred clock leon3mp|clk50MHz with period 10.00ns. A user-defined clock should be declared on object "p:clk50MHz" | ||||
@W: MT420 |Found inferred clock leon3mp|lclk_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:lclk" | ||||
@W: MT420 |Found inferred clock apbctrl|r_penable_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:apb0.r.penable" | ||||
@W: MT420 |Found inferred clock BaudGen|Bclk_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:COM0.COM0.BaudGenerator.Bclk" | ||||
##### START OF TIMING REPORT #####[ | ||||
# Timing Report written on Thu Oct 25 15:26:49 2012 | ||||
# | ||||
Top view: leon3mp | ||||
Library name: pa3l | ||||
Operating conditions: COMWC-1 ( T = 70.0, V = 1.14, P = 1.10, tree_type = balanced_tree ) | ||||
Requested Frequency: 100.0 MHz | ||||
Wire load mode: top | ||||
Wire load model: pa3l | ||||
Paths requested: 5 | ||||
Constraint File(s): | ||||
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.. | ||||
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.. | ||||
Performance Summary | ||||
******************* | ||||
Worst slack in design: -15.271 | ||||
Requested Estimated Requested Estimated Clock Clock | ||||
Starting Clock Frequency Frequency Period Period Slack Type Group | ||||
----------------------------------------------------------------------------------------------------------------------------------------- | ||||
BaudGen|Bclk_inferred_clock 100.0 MHz 130.9 MHz 10.000 7.639 2.361 inferred Inferred_clkgroup_3 | ||||
apbctrl|r_penable_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 | ||||
leon3mp|clk50MHz 100.0 MHz 342.9 MHz 10.000 2.916 7.084 inferred Inferred_clkgroup_2 | ||||
leon3mp|lclk_inferred_clock 100.0 MHz 39.6 MHz 10.000 25.271 -15.271 inferred Inferred_clkgroup_0 | ||||
========================================================================================================================================= | ||||
Clock Relationships | ||||
******************* | ||||
Clocks | rise to rise | fall to fall | rise to fall | fall to rise | ||||
------------------------------------------------------------------------------------------------------------------------------------------------------------- | ||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack | ||||
------------------------------------------------------------------------------------------------------------------------------------------------------------- | ||||
leon3mp|lclk_inferred_clock leon3mp|lclk_inferred_clock | 10.000 -15.271 | 10.000 3.493 | 5.000 -1.630 | 5.000 1.056 | ||||
leon3mp|lclk_inferred_clock apbctrl|r_penable_inferred_clock | Diff grp - | No paths - | No paths - | No paths - | ||||
apbctrl|r_penable_inferred_clock leon3mp|lclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - | ||||
leon3mp|clk50MHz leon3mp|clk50MHz | 10.000 7.084 | No paths - | No paths - | No paths - | ||||
BaudGen|Bclk_inferred_clock leon3mp|lclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - | ||||
BaudGen|Bclk_inferred_clock BaudGen|Bclk_inferred_clock | 10.000 2.361 | No paths - | No paths - | No paths - | ||||
============================================================================================================================================================= | ||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. | ||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. | ||||
Interface Information | ||||
********************* | ||||
No IO constraint found | ||||
==================================== | ||||
Detailed Report for Clock: BaudGen|Bclk_inferred_clock | ||||
==================================== | ||||
Starting Points with Worst Slack | ||||
******************************** | ||||
Starting Arrival | ||||
Instance Reference Type Pin Net Time Slack | ||||
Clock | ||||
--------------------------------------------------------------------------------------------------------------------------- | ||||
COM0.COM0.RX_REG.CptBits[9] BaudGen|Bclk_inferred_clock DFN1C1 Q CptBits[9] 0.693 2.361 | ||||
COM0.COM0.RX_REG.CptBits[7] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[7] 0.693 2.593 | ||||
COM0.COM0.RX_REG.CptBits[1] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[1] 0.693 2.659 | ||||
COM0.COM0.RX_REG.CptBits[6] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[6] 0.693 2.699 | ||||
COM0.COM0.RX_REG.CptBits[8] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[8] 0.693 2.732 | ||||
COM0.COM0.RX_REG.CptBits[3] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[3] 0.693 2.793 | ||||
COM0.COM0.RX_REG.CptBits[0] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[0] 0.693 2.805 | ||||
COM0.COM0.RX_REG.CptBits[2] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[2] 0.693 2.899 | ||||
COM0.COM0.RX_REG.Serialized_int_0 BaudGen|Bclk_inferred_clock DFN1C1 Q Taken_0 0.693 3.336 | ||||
COM0.COM0.RX_REG.CptBits[4] BaudGen|Bclk_inferred_clock DFN1E0C1 Q CptBits[4] 0.693 3.419 | ||||
=========================================================================================================================== | ||||
Ending Points with Worst Slack | ||||
****************************** | ||||
Starting Required | ||||
Instance Reference Type Pin Net Time Slack | ||||
Clock | ||||
---------------------------------------------------------------------------------------------------------------- | ||||
COM0.COM0.RX_REG.Q_1[1] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[1] 7.460 2.361 | ||||
COM0.COM0.RX_REG.Q_1[2] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[2] 7.460 2.361 | ||||
COM0.COM0.RX_REG.Q_1[3] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[3] 7.460 2.361 | ||||
COM0.COM0.RX_REG.Q_1[4] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[4] 7.460 2.361 | ||||
COM0.COM0.RX_REG.Q_1[5] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[5] 7.460 2.361 | ||||
COM0.COM0.RX_REG.Q_1[6] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[6] 7.460 2.361 | ||||
COM0.COM0.RX_REG.Q_1[7] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[7] 7.460 2.361 | ||||
COM0.COM0.RX_REG.Q_1[8] BaudGen|Bclk_inferred_clock DFN1P1C1 D Q_3[8] 7.460 2.361 | ||||
COM0.COM0.TX_REG.REG[1] BaudGen|Bclk_inferred_clock DFN1P1C1 D REG_3[1] 7.460 4.577 | ||||
COM0.COM0.TX_REG.REG[2] BaudGen|Bclk_inferred_clock DFN1P1C1 D REG_3[2] 7.460 4.577 | ||||
================================================================================================================ | ||||
Worst Path Information | ||||
*********************** | ||||
Path information for path number 1: | ||||
Requested Period: 10.000 | ||||
- Setup time: 2.540 | ||||
+ Clock delay at ending point: 0.000 (ideal) | ||||
= Required time: 7.460 | ||||
- Propagation time: 5.100 | ||||
- Clock delay at starting point: 0.000 (ideal) | ||||
= Slack (non-critical) : 2.361 | ||||
Number of logic level(s): 4 | ||||
Starting point: COM0.COM0.RX_REG.CptBits[9] / Q | ||||
Ending point: COM0.COM0.RX_REG.Q_1[1] / D | ||||
The start point is clocked by BaudGen|Bclk_inferred_clock [rising] on pin CLK | ||||
The end point is clocked by BaudGen|Bclk_inferred_clock [rising] on pin CLK | ||||
Instance / Net Pin Pin Arrival No. of | ||||
Name Type Name Dir Delay Time Fan Out(s) | ||||
------------------------------------------------------------------------------------------------------------- | ||||
COM0.COM0.RX_REG.CptBits[9] DFN1C1 Q Out 0.693 0.693 - | ||||
CptBits[9] Net - - 0.508 - 3 | ||||
COM0.COM0.RX_REG.CptBits_RNID3M7[8] NOR2B B In - 1.202 - | ||||
COM0.COM0.RX_REG.CptBits_RNID3M7[8] NOR2B Y Out 0.590 1.792 - | ||||
cptbits_flag_4 Net - - 0.203 - 1 | ||||
COM0.COM0.RX_REG.CptBits_RNIB92N[0] NOR3C C In - 1.995 - | ||||
COM0.COM0.RX_REG.CptBits_RNIB92N[0] NOR3C Y Out 0.603 2.598 - | ||||
cptbits_flag_7 Net - - 0.243 - 2 | ||||
COM0.COM0.RX_REG.Serialized_int_0_RNIT3S81 NOR3B B In - 2.842 - | ||||
COM0.COM0.RX_REG.Serialized_int_0_RNIT3S81 NOR3B Y Out 0.571 3.412 - | ||||
Serialized_int_0_sqmuxa Net - - 1.034 - 8 | ||||
COM0.COM0.RX_REG.Q_1_RNO_0[1] MX2 S In - 4.446 - | ||||
COM0.COM0.RX_REG.Q_1_RNO_0[1] MX2 Y Out 0.451 4.897 - | ||||
Q_3[1] Net - - 0.203 - 1 | ||||
COM0.COM0.RX_REG.Q_1[1] DFN1P1C1 D In - 5.100 - | ||||
============================================================================================================= | ||||
Total path delay (propagation time + setup) of 7.639 is 5.448(71.3%) logic and 2.191(28.7%) route. | ||||
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
==================================== | ||||
Detailed Report for Clock: leon3mp|clk50MHz | ||||
==================================== | ||||
Starting Points with Worst Slack | ||||
******************************** | ||||
Starting Arrival | ||||
Instance Reference Type Pin Net Time Slack | ||||
Clock | ||||
------------------------------------------------------------------------------------------- | ||||
SSRAM_0.state[3] leon3mp|clk50MHz DFN1C1 Q state[3] 0.693 7.084 | ||||
SSRAM_0.state[1] leon3mp|clk50MHz DFN1C1 Q state[1] 0.693 7.722 | ||||
lclk leon3mp|clk50MHz DFN1 Q lclk_i 0.693 7.876 | ||||
SSRAM_0.state[2] leon3mp|clk50MHz DFN1C1 Q state[2] 0.693 7.894 | ||||
=========================================================================================== | ||||
Ending Points with Worst Slack | ||||
****************************** | ||||
Starting Required | ||||
Instance Reference Type Pin Net Time Slack | ||||
Clock | ||||
----------------------------------------------------------------------------------------------- | ||||
SSRAM_0.state[3] leon3mp|clk50MHz DFN1C1 D state_ns[1] 9.493 7.084 | ||||
lclk leon3mp|clk50MHz DFN1 D lclk_i_i 9.493 7.876 | ||||
SSRAM_0.state[2] leon3mp|clk50MHz DFN1C1 D state[3] 9.460 7.960 | ||||
SSRAM_0.state[1] leon3mp|clk50MHz DFN1C1 D state[2] 9.460 8.524 | ||||
=============================================================================================== | ||||
Worst Path Information | ||||
*********************** | ||||
Path information for path number 1: | ||||
Requested Period: 10.000 | ||||
- Setup time: 0.507 | ||||
+ Clock delay at ending point: 0.000 (ideal) | ||||
= Required time: 9.493 | ||||
- Propagation time: 2.409 | ||||
- Clock delay at starting point: 0.000 (ideal) | ||||
= Slack (non-critical) : 7.084 | ||||
Number of logic level(s): 1 | ||||
Starting point: SSRAM_0.state[3] / Q | ||||
Ending point: SSRAM_0.state[3] / D | ||||
The start point is clocked by leon3mp|clk50MHz [rising] on pin CLK | ||||
The end point is clocked by leon3mp|clk50MHz [rising] on pin CLK | ||||
Instance / Net Pin Pin Arrival No. of | ||||
Name Type Name Dir Delay Time Fan Out(s) | ||||
------------------------------------------------------------------------------------- | ||||
SSRAM_0.state[3] DFN1C1 Q Out 0.693 0.693 - | ||||
state[3] Net - - 0.807 - 5 | ||||
SSRAM_0.state_RNO[3] NOR3 C In - 1.500 - | ||||
SSRAM_0.state_RNO[3] NOR3 Y Out 0.706 2.206 - | ||||
state_ns[1] Net - - 0.203 - 1 | ||||
SSRAM_0.state[3] DFN1C1 D In - 2.409 - | ||||
===================================================================================== | ||||
Total path delay (propagation time + setup) of 2.916 is 1.907(65.4%) logic and 1.010(34.6%) route. | ||||
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
==================================== | ||||
Detailed Report for Clock: leon3mp|lclk_inferred_clock | ||||
==================================== | ||||
Starting Points with Worst Slack | ||||
******************************** | ||||
Starting Arrival | ||||
Instance Reference Type Pin Net Time Slack | ||||
Clock | ||||
---------------------------------------------------------------------------------------------------------------------------------- | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_4 leon3mp|lclk_inferred_clock DFN1E0 Q ldbp1_4 0.693 -15.271 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[0] leon3mp|lclk_inferred_clock DFN1E1 Q data_0[0] 0.693 -15.248 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1 leon3mp|lclk_inferred_clock DFN1E0 Q ldbp1 0.693 -15.238 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[9] leon3mp|lclk_inferred_clock DFN1E1 Q data_0_0[9] 0.693 -15.205 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[11] leon3mp|lclk_inferred_clock DFN1E1 Q data_0[11] 0.693 -15.148 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_2 leon3mp|lclk_inferred_clock DFN1E0 Q ldbp1_2 0.693 -15.147 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[13] leon3mp|lclk_inferred_clock DFN1E1 Q data_0_0[13] 0.693 -15.095 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1[0] leon3mp|lclk_inferred_clock DFN1E0 Q op1[0] 0.693 -15.019 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_5 leon3mp|lclk_inferred_clock DFN1E0 Q ldbp1_5 0.693 -14.955 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1[9] leon3mp|lclk_inferred_clock DFN1E0 Q op1[9] 0.693 -14.916 | ||||
================================================================================================================================== | ||||
Ending Points with Worst Slack | ||||
****************************** | ||||
Starting Required | ||||
Instance Reference Type Pin Net Time Slack | ||||
Clock | ||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[0] leon3mp|lclk_inferred_clock DFN1E0 D valid_0_1[0] 9.460 -15.271 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[1] leon3mp|lclk_inferred_clock DFN1E0 D valid_0_1[1] 9.460 -15.271 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[2] leon3mp|lclk_inferred_clock DFN1E0 D valid_0_1[2] 9.460 -15.271 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[3] leon3mp|lclk_inferred_clock DFN1E0 D valid_0_1[3] 9.460 -15.271 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[0] leon3mp|lclk_inferred_clock DFN1E0 E valid_0_2_sqmuxa 9.428 -14.892 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[1] leon3mp|lclk_inferred_clock DFN1E0 E valid_0_2_sqmuxa 9.428 -14.892 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[2] leon3mp|lclk_inferred_clock DFN1E0 E valid_0_2_sqmuxa 9.428 -14.892 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[3] leon3mp|lclk_inferred_clock DFN1E0 E valid_0_2_sqmuxa 9.428 -14.892 | ||||
l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.1\.u0.u0 leon3mp|lclk_inferred_clock RAM512X18 WD0 vdtdatain_0_1[18] 9.819 -14.168 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush leon3mp|lclk_inferred_clock DFN1 D flush_0_0_RNIQ2USLN 9.460 -14.160 | ||||
========================================================================================================================================================================================= | ||||
Worst Path Information | ||||
*********************** | ||||
Path information for path number 1: | ||||
Requested Period: 10.000 | ||||
- Setup time: 0.540 | ||||
+ Clock delay at ending point: 0.000 (ideal) | ||||
= Required time: 9.460 | ||||
- Propagation time: 24.732 | ||||
- Clock delay at starting point: 0.000 (ideal) | ||||
= Slack (critical) : -15.271 | ||||
Number of logic level(s): 22 | ||||
Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_4 / Q | ||||
Ending point: l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[0] / D | ||||
The start point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
The end point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
Instance / Net Pin Pin Arrival No. of | ||||
Name Type Name Dir Delay Time Fan Out(s) | ||||
--------------------------------------------------------------------------------------------------------------------------------------- | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_4 DFN1E0 Q Out 0.693 0.693 - | ||||
ldbp1_4 Net - - 1.502 - 21 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI7JN8[0] MX2 S In - 2.195 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI7JN8[0] MX2 Y Out 0.373 2.568 - | ||||
un1_iu0_6[0] Net - - 1.313 - 14 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I1_P0N OR2 A In - 3.881 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I1_P0N OR2 Y Out 0.477 4.358 - | ||||
N398_0 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1_0 AND2 A In - 4.561 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1_0 AND2 Y Out 0.484 5.045 - | ||||
ADD_33x33_fast_I206_Y_0_a3_1_0 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1 AND2 B In - 5.248 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1 AND2 Y Out 0.590 5.838 - | ||||
N_57 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2 B In - 6.041 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2 Y Out 0.608 6.649 - | ||||
N616_0 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR2B A In - 7.395 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR2B Y Out 0.484 7.879 - | ||||
I204_un1_Y_1 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR2 B In - 8.082 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR2 Y Out 0.608 8.691 - | ||||
N674_0 Net - - 0.508 - 3 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_un1_Y OR3C C In - 9.199 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_un1_Y OR3C Y Out 0.603 9.802 - | ||||
I268_un1_Y_i Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_Y OR2B B In - 10.005 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_Y OR2B Y Out 0.486 10.491 - | ||||
N782 Net - - 0.243 - 2 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I313_Y_0 XNOR3 C In - 10.734 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I313_Y_0 XNOR3 Y Out 0.927 11.661 - | ||||
un6_ex_add_res_s1_i[23] Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIAN00P3 MX2C A In - 11.864 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIAN00P3 MX2C Y Out 0.544 12.409 - | ||||
eaddress[22] Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 NOR2 A In - 13.155 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 NOR2 Y Out 0.342 13.497 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 NOR3C C In - 13.699 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 NOR3C Y Out 0.603 14.303 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 AND2 B In - 14.506 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 AND2 Y Out 0.590 15.096 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 AND2 A In - 15.299 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 AND2 Y Out 0.484 15.783 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0 NOR2B A In - 15.986 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0 NOR2B Y Out 0.484 16.470 - | ||||
un1_addout_10 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIRAUD1A1 OR2B B In - 17.216 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIRAUD1A1 OR2B Y Out 0.590 17.806 - | ||||
un1_addout_1 Net - - 0.508 - 3 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.twrite_15_iv_m1_e OR2 B In - 18.315 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.twrite_15_iv_m1_e OR2 Y Out 0.484 18.799 - | ||||
un1_addout Net - - 1.456 - 19 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.m\.casa_RNIRS73J92 OR2B B In - 20.254 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.m\.casa_RNIRS73J92 OR2B Y Out 0.486 20.740 - | ||||
un16_casaen Net - - 1.370 - 16 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.rstate_RNI9LC8J92[0] NOR2A A In - 22.110 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.rstate_RNI9LC8J92[0] NOR2A Y Out 0.590 22.700 - | ||||
un1_nullify_0_sqmuxa_2 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.twrite_0_sqmuxa_1_i_RNI22CPMO1 MX2C B In - 22.903 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.twrite_0_sqmuxa_1_i_RNI22CPMO1 MX2C Y Out 0.538 23.441 - | ||||
N_2902 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0_RNO[0] NOR2 A In - 24.187 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0_RNO[0] NOR2 Y Out 0.342 24.529 - | ||||
valid_0_1[0] Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[0] DFN1E0 D In - 24.732 - | ||||
======================================================================================================================================= | ||||
Total path delay (propagation time + setup) of 25.271 is 12.952(51.3%) logic and 12.319(48.7%) route. | ||||
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
Path information for path number 2: | ||||
Requested Period: 10.000 | ||||
- Setup time: 0.540 | ||||
+ Clock delay at ending point: 0.000 (ideal) | ||||
= Required time: 9.460 | ||||
- Propagation time: 24.732 | ||||
- Clock delay at starting point: 0.000 (ideal) | ||||
= Slack (critical) : -15.271 | ||||
Number of logic level(s): 22 | ||||
Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_4 / Q | ||||
Ending point: l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[3] / D | ||||
The start point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
The end point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
Instance / Net Pin Pin Arrival No. of | ||||
Name Type Name Dir Delay Time Fan Out(s) | ||||
--------------------------------------------------------------------------------------------------------------------------------------- | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_4 DFN1E0 Q Out 0.693 0.693 - | ||||
ldbp1_4 Net - - 1.502 - 21 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI7JN8[0] MX2 S In - 2.195 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI7JN8[0] MX2 Y Out 0.373 2.568 - | ||||
un1_iu0_6[0] Net - - 1.313 - 14 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I1_P0N OR2 A In - 3.881 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I1_P0N OR2 Y Out 0.477 4.358 - | ||||
N398_0 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1_0 AND2 A In - 4.561 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1_0 AND2 Y Out 0.484 5.045 - | ||||
ADD_33x33_fast_I206_Y_0_a3_1_0 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1 AND2 B In - 5.248 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1 AND2 Y Out 0.590 5.838 - | ||||
N_57 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2 B In - 6.041 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2 Y Out 0.608 6.649 - | ||||
N616_0 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR2B A In - 7.395 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR2B Y Out 0.484 7.879 - | ||||
I204_un1_Y_1 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR2 B In - 8.082 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR2 Y Out 0.608 8.691 - | ||||
N674_0 Net - - 0.508 - 3 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_un1_Y OR3C C In - 9.199 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_un1_Y OR3C Y Out 0.603 9.802 - | ||||
I268_un1_Y_i Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_Y OR2B B In - 10.005 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_Y OR2B Y Out 0.486 10.491 - | ||||
N782 Net - - 0.243 - 2 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I313_Y_0 XNOR3 C In - 10.734 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I313_Y_0 XNOR3 Y Out 0.927 11.661 - | ||||
un6_ex_add_res_s1_i[23] Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIAN00P3 MX2C A In - 11.864 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIAN00P3 MX2C Y Out 0.544 12.409 - | ||||
eaddress[22] Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 NOR2 A In - 13.155 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 NOR2 Y Out 0.342 13.497 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 NOR3C C In - 13.699 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 NOR3C Y Out 0.603 14.303 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 AND2 B In - 14.506 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 AND2 Y Out 0.590 15.096 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 AND2 A In - 15.299 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 AND2 Y Out 0.484 15.783 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0 NOR2B A In - 15.986 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0 NOR2B Y Out 0.484 16.470 - | ||||
un1_addout_10 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIRAUD1A1 OR2B B In - 17.216 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIRAUD1A1 OR2B Y Out 0.590 17.806 - | ||||
un1_addout_1 Net - - 0.508 - 3 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.twrite_15_iv_m1_e OR2 B In - 18.315 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.twrite_15_iv_m1_e OR2 Y Out 0.484 18.799 - | ||||
un1_addout Net - - 1.456 - 19 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.m\.casa_RNIRS73J92 OR2B B In - 20.254 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.m\.casa_RNIRS73J92 OR2B Y Out 0.486 20.740 - | ||||
un16_casaen Net - - 1.370 - 16 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.rstate_RNI9LC8J92[0] NOR2A A In - 22.110 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.rstate_RNI9LC8J92[0] NOR2A Y Out 0.590 22.700 - | ||||
un1_nullify_0_sqmuxa_2 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.twrite_0_sqmuxa_1_i_RNI22CPMO1 MX2C B In - 22.903 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.twrite_0_sqmuxa_1_i_RNI22CPMO1 MX2C Y Out 0.538 23.441 - | ||||
N_2902 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0_RNO[3] NOR2 A In - 24.187 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0_RNO[3] NOR2 Y Out 0.342 24.529 - | ||||
valid_0_1[3] Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[3] DFN1E0 D In - 24.732 - | ||||
======================================================================================================================================= | ||||
Total path delay (propagation time + setup) of 25.271 is 12.952(51.3%) logic and 12.319(48.7%) route. | ||||
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
Path information for path number 3: | ||||
Requested Period: 10.000 | ||||
- Setup time: 0.540 | ||||
+ Clock delay at ending point: 0.000 (ideal) | ||||
= Required time: 9.460 | ||||
- Propagation time: 24.732 | ||||
- Clock delay at starting point: 0.000 (ideal) | ||||
= Slack (critical) : -15.271 | ||||
Number of logic level(s): 22 | ||||
Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_4 / Q | ||||
Ending point: l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[1] / D | ||||
The start point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
The end point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
Instance / Net Pin Pin Arrival No. of | ||||
Name Type Name Dir Delay Time Fan Out(s) | ||||
--------------------------------------------------------------------------------------------------------------------------------------- | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_4 DFN1E0 Q Out 0.693 0.693 - | ||||
ldbp1_4 Net - - 1.502 - 21 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI7JN8[0] MX2 S In - 2.195 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI7JN8[0] MX2 Y Out 0.373 2.568 - | ||||
un1_iu0_6[0] Net - - 1.313 - 14 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I1_P0N OR2 A In - 3.881 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I1_P0N OR2 Y Out 0.477 4.358 - | ||||
N398_0 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1_0 AND2 A In - 4.561 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1_0 AND2 Y Out 0.484 5.045 - | ||||
ADD_33x33_fast_I206_Y_0_a3_1_0 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1 AND2 B In - 5.248 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1 AND2 Y Out 0.590 5.838 - | ||||
N_57 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2 B In - 6.041 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2 Y Out 0.608 6.649 - | ||||
N616_0 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR2B A In - 7.395 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR2B Y Out 0.484 7.879 - | ||||
I204_un1_Y_1 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR2 B In - 8.082 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR2 Y Out 0.608 8.691 - | ||||
N674_0 Net - - 0.508 - 3 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_un1_Y OR3C C In - 9.199 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_un1_Y OR3C Y Out 0.603 9.802 - | ||||
I268_un1_Y_i Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_Y OR2B B In - 10.005 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_Y OR2B Y Out 0.486 10.491 - | ||||
N782 Net - - 0.243 - 2 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I313_Y_0 XNOR3 C In - 10.734 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I313_Y_0 XNOR3 Y Out 0.927 11.661 - | ||||
un6_ex_add_res_s1_i[23] Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIAN00P3 MX2C A In - 11.864 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIAN00P3 MX2C Y Out 0.544 12.409 - | ||||
eaddress[22] Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 NOR2 A In - 13.155 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 NOR2 Y Out 0.342 13.497 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 NOR3C C In - 13.699 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 NOR3C Y Out 0.603 14.303 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 AND2 B In - 14.506 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 AND2 Y Out 0.590 15.096 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 AND2 A In - 15.299 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 AND2 Y Out 0.484 15.783 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0 NOR2B A In - 15.986 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0 NOR2B Y Out 0.484 16.470 - | ||||
un1_addout_10 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIRAUD1A1 OR2B B In - 17.216 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIRAUD1A1 OR2B Y Out 0.590 17.806 - | ||||
un1_addout_1 Net - - 0.508 - 3 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.twrite_15_iv_m1_e OR2 B In - 18.315 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.twrite_15_iv_m1_e OR2 Y Out 0.484 18.799 - | ||||
un1_addout Net - - 1.456 - 19 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.m\.casa_RNIRS73J92 OR2B B In - 20.254 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.m\.casa_RNIRS73J92 OR2B Y Out 0.486 20.740 - | ||||
un16_casaen Net - - 1.370 - 16 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.rstate_RNI9LC8J92[0] NOR2A A In - 22.110 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.rstate_RNI9LC8J92[0] NOR2A Y Out 0.590 22.700 - | ||||
un1_nullify_0_sqmuxa_2 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.twrite_0_sqmuxa_1_i_RNI22CPMO1 MX2C B In - 22.903 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.twrite_0_sqmuxa_1_i_RNI22CPMO1 MX2C Y Out 0.538 23.441 - | ||||
N_2902 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0_RNO[1] NOR2 A In - 24.187 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0_RNO[1] NOR2 Y Out 0.342 24.529 - | ||||
valid_0_1[1] Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[1] DFN1E0 D In - 24.732 - | ||||
======================================================================================================================================= | ||||
Total path delay (propagation time + setup) of 25.271 is 12.952(51.3%) logic and 12.319(48.7%) route. | ||||
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
Path information for path number 4: | ||||
Requested Period: 10.000 | ||||
- Setup time: 0.540 | ||||
+ Clock delay at ending point: 0.000 (ideal) | ||||
= Required time: 9.460 | ||||
- Propagation time: 24.732 | ||||
- Clock delay at starting point: 0.000 (ideal) | ||||
= Slack (critical) : -15.271 | ||||
Number of logic level(s): 22 | ||||
Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_4 / Q | ||||
Ending point: l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[2] / D | ||||
The start point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
The end point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
Instance / Net Pin Pin Arrival No. of | ||||
Name Type Name Dir Delay Time Fan Out(s) | ||||
--------------------------------------------------------------------------------------------------------------------------------------- | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_4 DFN1E0 Q Out 0.693 0.693 - | ||||
ldbp1_4 Net - - 1.502 - 21 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI7JN8[0] MX2 S In - 2.195 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI7JN8[0] MX2 Y Out 0.373 2.568 - | ||||
un1_iu0_6[0] Net - - 1.313 - 14 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I1_P0N OR2 A In - 3.881 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I1_P0N OR2 Y Out 0.477 4.358 - | ||||
N398_0 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1_0 AND2 A In - 4.561 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1_0 AND2 Y Out 0.484 5.045 - | ||||
ADD_33x33_fast_I206_Y_0_a3_1_0 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1 AND2 B In - 5.248 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1 AND2 Y Out 0.590 5.838 - | ||||
N_57 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2 B In - 6.041 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2 Y Out 0.608 6.649 - | ||||
N616_0 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR2B A In - 7.395 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR2B Y Out 0.484 7.879 - | ||||
I204_un1_Y_1 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR2 B In - 8.082 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR2 Y Out 0.608 8.691 - | ||||
N674_0 Net - - 0.508 - 3 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_un1_Y OR3C C In - 9.199 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_un1_Y OR3C Y Out 0.603 9.802 - | ||||
I268_un1_Y_i Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_Y OR2B B In - 10.005 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_Y OR2B Y Out 0.486 10.491 - | ||||
N782 Net - - 0.243 - 2 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I313_Y_0 XNOR3 C In - 10.734 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I313_Y_0 XNOR3 Y Out 0.927 11.661 - | ||||
un6_ex_add_res_s1_i[23] Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIAN00P3 MX2C A In - 11.864 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIAN00P3 MX2C Y Out 0.544 12.409 - | ||||
eaddress[22] Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 NOR2 A In - 13.155 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 NOR2 Y Out 0.342 13.497 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 NOR3C C In - 13.699 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 NOR3C Y Out 0.603 14.303 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 AND2 B In - 14.506 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 AND2 Y Out 0.590 15.096 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 AND2 A In - 15.299 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 AND2 Y Out 0.484 15.783 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0 NOR2B A In - 15.986 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0 NOR2B Y Out 0.484 16.470 - | ||||
un1_addout_10 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIRAUD1A1 OR2B B In - 17.216 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIRAUD1A1 OR2B Y Out 0.590 17.806 - | ||||
un1_addout_1 Net - - 0.508 - 3 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.twrite_15_iv_m1_e OR2 B In - 18.315 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.twrite_15_iv_m1_e OR2 Y Out 0.484 18.799 - | ||||
un1_addout Net - - 1.456 - 19 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.m\.casa_RNIRS73J92 OR2B B In - 20.254 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.m\.casa_RNIRS73J92 OR2B Y Out 0.486 20.740 - | ||||
un16_casaen Net - - 1.370 - 16 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.rstate_RNI9LC8J92[0] NOR2A A In - 22.110 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.rstate_RNI9LC8J92[0] NOR2A Y Out 0.590 22.700 - | ||||
un1_nullify_0_sqmuxa_2 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.twrite_0_sqmuxa_1_i_RNI22CPMO1 MX2C B In - 22.903 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.twrite_0_sqmuxa_1_i_RNI22CPMO1 MX2C Y Out 0.538 23.441 - | ||||
N_2902 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0_RNO[2] NOR2 A In - 24.187 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0_RNO[2] NOR2 Y Out 0.342 24.529 - | ||||
valid_0_1[2] Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[2] DFN1E0 D In - 24.732 - | ||||
======================================================================================================================================= | ||||
Total path delay (propagation time + setup) of 25.271 is 12.952(51.3%) logic and 12.319(48.7%) route. | ||||
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
Path information for path number 5: | ||||
Requested Period: 10.000 | ||||
- Setup time: 0.540 | ||||
+ Clock delay at ending point: 0.000 (ideal) | ||||
= Required time: 9.460 | ||||
- Propagation time: 24.708 | ||||
- Clock delay at starting point: 0.000 (ideal) | ||||
= Slack (non-critical) : -15.248 | ||||
Number of logic level(s): 22 | ||||
Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[0] / Q | ||||
Ending point: l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[0] / D | ||||
The start point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
The end point is clocked by leon3mp|lclk_inferred_clock [rising] on pin CLK | ||||
Instance / Net Pin Pin Arrival No. of | ||||
Name Type Name Dir Delay Time Fan Out(s) | ||||
--------------------------------------------------------------------------------------------------------------------------------------- | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[0] DFN1E1 Q Out 0.693 0.693 - | ||||
data_0[0] Net - - 1.313 - 14 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI7JN8[0] MX2 B In - 2.006 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNI7JN8[0] MX2 Y Out 0.538 2.544 - | ||||
un1_iu0_6[0] Net - - 1.313 - 14 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I1_P0N OR2 A In - 3.857 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I1_P0N OR2 Y Out 0.477 4.335 - | ||||
N398_0 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1_0 AND2 A In - 4.537 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1_0 AND2 Y Out 0.484 5.021 - | ||||
ADD_33x33_fast_I206_Y_0_a3_1_0 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1 AND2 B In - 5.224 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_a3_1 AND2 Y Out 0.590 5.814 - | ||||
N_57 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2 B In - 6.017 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I206_Y_0_o3_1 OR2 Y Out 0.608 6.626 - | ||||
N616_0 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR2B A In - 7.372 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_un1_Y NOR2B Y Out 0.484 7.856 - | ||||
I204_un1_Y_1 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR2 B In - 8.059 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I204_Y OR2 Y Out 0.608 8.667 - | ||||
N674_0 Net - - 0.508 - 3 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_un1_Y OR3C C In - 9.176 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_un1_Y OR3C Y Out 0.603 9.779 - | ||||
I268_un1_Y_i Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_Y OR2B B In - 9.982 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I268_Y OR2B Y Out 0.486 10.467 - | ||||
N782 Net - - 0.243 - 2 | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I313_Y_0 XNOR3 C In - 10.711 - | ||||
l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I313_Y_0 XNOR3 Y Out 0.927 11.638 - | ||||
un6_ex_add_res_s1_i[23] Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIAN00P3 MX2C A In - 11.841 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIAN00P3 MX2C Y Out 0.544 12.385 - | ||||
eaddress[22] Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 NOR2 A In - 13.132 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 NOR2 Y Out 0.342 13.473 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_6 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 NOR3C C In - 13.676 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 NOR3C Y Out 0.603 14.279 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_10 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 AND2 B In - 14.482 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 AND2 Y Out 0.590 15.073 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_14 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 AND2 A In - 15.275 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 AND2 Y Out 0.484 15.759 - | ||||
mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0_16 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0 NOR2B A In - 15.962 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.mexc_1_sqmuxa_0_a2_0_1tt_m3_e_0 NOR2B Y Out 0.484 16.446 - | ||||
un1_addout_10 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIRAUD1A1 OR2B B In - 17.192 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIRAUD1A1 OR2B Y Out 0.590 17.783 - | ||||
un1_addout_1 Net - - 0.508 - 3 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.twrite_15_iv_m1_e OR2 B In - 18.291 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.dctrl\.twrite_15_iv_m1_e OR2 Y Out 0.484 18.775 - | ||||
un1_addout Net - - 1.456 - 19 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.m\.casa_RNIRS73J92 OR2B B In - 20.231 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.m\.casa_RNIRS73J92 OR2B Y Out 0.486 20.716 - | ||||
un16_casaen Net - - 1.370 - 16 | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.rstate_RNI9LC8J92[0] NOR2A A In - 22.086 - | ||||
l3\.cpu\.0\.u0.p0.iu0.r\.x\.rstate_RNI9LC8J92[0] NOR2A Y Out 0.590 22.677 - | ||||
un1_nullify_0_sqmuxa_2 Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.twrite_0_sqmuxa_1_i_RNI22CPMO1 MX2C B In - 22.880 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.twrite_0_sqmuxa_1_i_RNI22CPMO1 MX2C Y Out 0.538 23.417 - | ||||
N_2902 Net - - 0.746 - 4 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0_RNO[0] NOR2 A In - 24.164 - | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0_RNO[0] NOR2 Y Out 0.342 24.506 - | ||||
valid_0_1[0] Net - - 0.203 - 1 | ||||
l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.valid_0[0] DFN1E0 D In - 24.708 - | ||||
======================================================================================================================================= | ||||
Total path delay (propagation time + setup) of 25.248 is 13.117(52.0%) logic and 12.131(48.0%) route. | ||||
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value | ||||
##### END OF TIMING REPORT #####] | ||||
-------------------------------------------------------------------------------- | ||||
Target Part: A3PE3000L_PQFP208_-1 | ||||
Report for cell leon3mp.behavioral | ||||
Core Cell usage: | ||||
cell count area count*area | ||||
AND2 1190 1.0 1190.0 | ||||
AND2A 17 1.0 17.0 | ||||
AND3 352 1.0 352.0 | ||||
AND3A 1 1.0 1.0 | ||||
AO1 547 1.0 547.0 | ||||
AO13 46 1.0 46.0 | ||||
AO15 2 1.0 2.0 | ||||
AO16 3 1.0 3.0 | ||||
AO17 2 1.0 2.0 | ||||
AO18 33 1.0 33.0 | ||||
AO1A 183 1.0 183.0 | ||||
AO1B 263 1.0 263.0 | ||||
AO1C 149 1.0 149.0 | ||||
AO1D 71 1.0 71.0 | ||||
AOI1 130 1.0 130.0 | ||||
AOI1A 8 1.0 8.0 | ||||
AOI1B 487 1.0 487.0 | ||||
AX1 18 1.0 18.0 | ||||
AX1A 32 1.0 32.0 | ||||
AX1B 15 1.0 15.0 | ||||
AX1C 113 1.0 113.0 | ||||
AX1D 36 1.0 36.0 | ||||
AX1E 20 1.0 20.0 | ||||
AXO1 1 1.0 1.0 | ||||
AXO2 3 1.0 3.0 | ||||
AXO3 2 1.0 2.0 | ||||
AXO5 4 1.0 4.0 | ||||
AXO6 1 1.0 1.0 | ||||
AXO7 6 1.0 6.0 | ||||
AXOI1 3 1.0 3.0 | ||||
AXOI2 1 1.0 1.0 | ||||
AXOI3 5 1.0 5.0 | ||||
AXOI4 7 1.0 7.0 | ||||
AXOI5 8 1.0 8.0 | ||||
AXOI7 2 1.0 2.0 | ||||
BUFF 226 1.0 226.0 | ||||
CLKINT 6 0.0 0.0 | ||||
GND 198 0.0 0.0 | ||||
INV 57 1.0 57.0 | ||||
MAJ3 578 1.0 578.0 | ||||
MAJ3X 1 1.0 1.0 | ||||
MIN3 127 1.0 127.0 | ||||
MIN3X 1 1.0 1.0 | ||||
MX2 2326 1.0 2326.0 | ||||
MX2A 334 1.0 334.0 | ||||
MX2B 129 1.0 129.0 | ||||
MX2C 1206 1.0 1206.0 | ||||
NAND2 70 1.0 70.0 | ||||
NOR2 709 1.0 709.0 | ||||
NOR2A 996 1.0 996.0 | ||||
NOR2B 1357 1.0 1357.0 | ||||
NOR3 221 1.0 221.0 | ||||
NOR3A 299 1.0 299.0 | ||||
NOR3B 288 1.0 288.0 | ||||
NOR3C 895 1.0 895.0 | ||||
OA1 173 1.0 173.0 | ||||
OA1A 325 1.0 325.0 | ||||
OA1B 96 1.0 96.0 | ||||
OA1C 81 1.0 81.0 | ||||
OAI1 88 1.0 88.0 | ||||
OR2 587 1.0 587.0 | ||||
OR2A 1206 1.0 1206.0 | ||||
OR2B 1774 1.0 1774.0 | ||||
OR3 224 1.0 224.0 | ||||
OR3A 335 1.0 335.0 | ||||
OR3B 316 1.0 316.0 | ||||
OR3C 580 1.0 580.0 | ||||
VCC 198 0.0 0.0 | ||||
XA1 48 1.0 48.0 | ||||
XA1A 168 1.0 168.0 | ||||
XA1B 88 1.0 88.0 | ||||
XA1C 36 1.0 36.0 | ||||
XAI1 15 1.0 15.0 | ||||
XAI1A 17 1.0 17.0 | ||||
XNOR2 646 1.0 646.0 | ||||
XNOR3 97 1.0 97.0 | ||||
XO1 7 1.0 7.0 | ||||
XO1A 6 1.0 6.0 | ||||
XOR2 1732 1.0 1732.0 | ||||
XOR3 589 1.0 589.0 | ||||
DFN0E0C0 80 1.0 80.0 | ||||
DFN0E1 81 1.0 81.0 | ||||
DFN0E1C0 6 1.0 6.0 | ||||
DFN1 2546 1.0 2546.0 | ||||
DFN1C0 325 1.0 325.0 | ||||
DFN1C1 87 1.0 87.0 | ||||
DFN1E0 1289 1.0 1289.0 | ||||
DFN1E0C0 14 1.0 14.0 | ||||
DFN1E0C1 96 1.0 96.0 | ||||
DFN1E0P0 75 1.0 75.0 | ||||
DFN1E0P1 10 1.0 10.0 | ||||
DFN1E1 640 1.0 640.0 | ||||
DFN1E1C0 218 1.0 218.0 | ||||
DFN1E1C1 71 1.0 71.0 | ||||
DFN1E1P0 169 1.0 169.0 | ||||
DFN1E1P1 1 1.0 1.0 | ||||
DFN1P0 9 1.0 9.0 | ||||
DFN1P1 9 1.0 9.0 | ||||
DFN1P1C1 23 4.0 92.0 | ||||
DLN1 142 1.0 142.0 | ||||
DLN1P1C1 1 2.0 2.0 | ||||
RAM4K9 16 0.0 0.0 | ||||
RAM512X18 35 0.0 0.0 | ||||
----- ---------- | ||||
TOTAL 29160 28777.0 | ||||
IO Cell usage: | ||||
cell count | ||||
BIBUF 39 | ||||
INBUF 10 | ||||
OUTBUF 52 | ||||
----- | ||||
TOTAL 101 | ||||
Core Cells : 28777 of 75264 (38%) | ||||
IO Cells : 101 | ||||
RAM/ROM Usage Summary | ||||
Block Rams : 51 of 112 (45%) | ||||
Mapper successful! | ||||
Process took 0h:02m:41s realtime, 0h:02m:38s cputime | ||||
# Thu Oct 25 15:26:50 2012 | ||||
###########################################################] | ||||