HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd

Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI

martin - - Load All Authors

File last commit:

r98:0de5e600d49b martin


                r109:02eade4e2829

martin

Download file

             lpp_ad_Conv.vhd
        
                    127 lines
            
             | 4.1 KiB
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / lib / lpp / lpp_ad_Conv / lpp_ad_Conv.vhd
          
                    History
                
                 |
                  Source
                 | Raw
                 |Copy content
                 |Copy permalink

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      ------------------------------------------------------------------------------

      --  This file is a part of the LPP VHDL IP LIBRARY

      --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS

      --

      --  This program is free software; you can redistribute it and/or modify

      --  it under the terms of the GNU General Public License as published by

      --  the Free Software Foundation; either version 3 of the License, or

      --  (at your option) any later version.

      --

      --  This program is distributed in the hope that it will be useful,

      --  but WITHOUT ANY WARRANTY; without even the implied warranty of

      --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

      --  GNU General Public License for more details.

      --

      --  You should have received a copy of the GNU General Public License

      --  along with this program; if not, write to the Free Software

      --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

      -------------------------------------------------------------------------------

        Alexis
    
Minor changes

              r38
            
      --                    Author : Alexis Jeandet

      --                     Mail : alexis.jeandet@lpp.polytechnique.fr

      ----------------------------------------------------------------------------

        Alexis
    
Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.

              r20
            
        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      library IEEE;

      use IEEE.STD_LOGIC_1164.all;

        Alexis
    
Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.

              r20
            
      library grlib;

      use grlib.amba.all;

      use grlib.stdlib.all;

      use grlib.devices.all;

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      package lpp_ad_conv is

        Alexis
    
Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.

              r20
            
        constant    AD7688    : integer := 0;

        constant    ADS7886   : integer := 1;

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
        type AD7688_out is

          record

              CNV        : std_logic;

              SCK        : std_logic;

          end record;

        type AD7688_in_element is

          record

              SDI        : std_logic;

          end record;

      	 type AD7688_in is array(natural range <>) of AD7688_in_element;

      	type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0);

      	component  AD7688_drvr is

        Alexis
    
Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.

              r20
            
      		    generic(ChanelCount	:	integer; 

      				clkkHz		:	integer);

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      		 Port ( clk 	: in  STD_LOGIC;

        martin
    
update ADC

              r98
            
                                      rstn        :      in  STD_LOGIC;

                                      enable      :      in  std_logic;

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      				  smplClk: in	STD_LOGIC;

        Alexis
    
Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.

              r20
            
      				  DataReady : out std_logic;

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      				  smpout : out Samples_out(ChanelCount-1 downto 0);	

      				  AD_in	: in	AD7688_in(ChanelCount-1 downto 0);	

      				  AD_out : out AD7688_out);

      	end component;

        Alexis
    
Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.

              r20
            
      component AD7688_spi_if is

      	 generic(ChanelCount	:	integer);

          Port(    clk      : in  STD_LOGIC;

                   reset    : in  STD_LOGIC;

                   cnv      : in  STD_LOGIC;

        martin
    
update ADC

              r98
            
      	     DataReady:	out std_logic;

        Alexis
    
Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.

              r20
            
                   sdi      : in	AD7688_in(ChanelCount-1 downto 0);

                   smpout   :  out Samples_out(ChanelCount-1 downto 0)

           );

      end component;

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
        Alexis
    
Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.

              r20
            
      component lpp_apb_ad_conv

              generic(

                pindex      : integer := 0;

                paddr       : integer := 0;

                pmask       : integer := 16#fff#;

                pirq        : integer := 0;

                abits       : integer := 8;

                ChanelCount : integer := 1; 

                clkkHz      : integer := 50000;

      	  smpClkHz    : integer := 100;

                ADCref      : integer := AD7688);

          Port ( 

                clk        : in   STD_LOGIC;

                reset      : in   STD_LOGIC;

                apbi       : in   apb_slv_in_type;

                apbo       : out  apb_slv_out_type;

                AD_in      : in   AD7688_in(ChanelCount-1 downto 0);	

                AD_out     : out  AD7688_out);

      end component;

      component ADS7886_drvr is

          generic(ChanelCount :      integer; 

                  clkkHz      :      integer);

          Port ( 

                  clk         :      in  STD_LOGIC;

        martin
    
update ADC

              r98
            
                   reset 	: in  STD_LOGIC;

        Alexis
    
Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.

              r20
            
                  smplClk     :      in  STD_LOGIC;

                  DataReady   :      out std_logic;

                  smpout      :      out Samples_out(ChanelCount-1 downto 0);	

                  AD_in       :      in  AD7688_in(ChanelCount-1 downto 0);	

                  AD_out      :      out AD7688_out

                 );

      end component;

        martin
    
update ADC

              r98
            
      component WriteGen_ADC is

          port(

              clk         : in std_logic;

              rstn        : in std_logic;

              SmplCLK     : in std_logic;

              DataReady   : in std_logic;

              Full        : in std_logic_vector(4 downto 0);

              ReUse       : out std_logic_vector(4 downto 0);

              Write       : out std_logic_vector(4 downto 0)

          );

      end component;

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      end lpp_ad_conv;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	------------------------------------------------------------------------------
		-- This file is a part of the LPP VHDL IP LIBRARY
		-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
		--
		-- This program is free software; you can redistribute it and/or modify
		-- it under the terms of the GNU General Public License as published by
		-- the Free Software Foundation; either version 3 of the License, or
		-- (at your option) any later version.
		--
		-- This program is distributed in the hope that it will be useful,
		-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		-- GNU General Public License for more details.
		--
		-- You should have received a copy of the GNU General Public License
		-- along with this program; if not, write to the Free Software
		-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		-------------------------------------------------------------------------------
Alexis Minor changes	r38	-- Author : Alexis Jeandet
		-- Mail : alexis.jeandet@lpp.polytechnique.fr
		----------------------------------------------------------------------------
Alexis Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.	r20
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	library IEEE;
		use IEEE.STD_LOGIC_1164.all;
Alexis Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.	r20	library grlib;
		use grlib.amba.all;
		use grlib.stdlib.all;
		use grlib.devices.all;
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19

		package lpp_ad_conv is

Alexis Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.	r20
		constant AD7688 : integer := 0;
		constant ADS7886 : integer := 1;

Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
		type AD7688_out is
		record
		CNV : std_logic;
		SCK : std_logic;
		end record;

		type AD7688_in_element is
		record
		SDI : std_logic;
		end record;

		type AD7688_in is array(natural range <>) of AD7688_in_element;

		type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0);

		component AD7688_drvr is
Alexis Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.	r20	generic(ChanelCount : integer;
		clkkHz : integer);
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	Port ( clk : in STD_LOGIC;
martin update ADC	r98	rstn : in STD_LOGIC;
		enable : in std_logic;
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	smplClk: in STD_LOGIC;
Alexis Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.	r20	DataReady : out std_logic;
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	smpout : out Samples_out(ChanelCount-1 downto 0);
		AD_in : in AD7688_in(ChanelCount-1 downto 0);
		AD_out : out AD7688_out);
		end component;


Alexis Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.	r20	component AD7688_spi_if is
		generic(ChanelCount : integer);
		Port( clk : in STD_LOGIC;
		reset : in STD_LOGIC;
		cnv : in STD_LOGIC;
martin update ADC	r98	DataReady: out std_logic;
Alexis Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.	r20	sdi : in AD7688_in(ChanelCount-1 downto 0);
		smpout : out Samples_out(ChanelCount-1 downto 0)
		);
		end component;
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19

Alexis Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.	r20	component lpp_apb_ad_conv
		generic(
		pindex : integer := 0;
		paddr : integer := 0;
		pmask : integer := 16#fff#;
		pirq : integer := 0;
		abits : integer := 8;
		ChanelCount : integer := 1;
		clkkHz : integer := 50000;
		smpClkHz : integer := 100;
		ADCref : integer := AD7688);
		Port (
		clk : in STD_LOGIC;
		reset : in STD_LOGIC;
		apbi : in apb_slv_in_type;
		apbo : out apb_slv_out_type;
		AD_in : in AD7688_in(ChanelCount-1 downto 0);
		AD_out : out AD7688_out);
		end component;

		component ADS7886_drvr is
		generic(ChanelCount : integer;
		clkkHz : integer);
		Port (
		clk : in STD_LOGIC;
martin update ADC	r98	reset : in STD_LOGIC;
Alexis Added ADS7886 VHD driver, improved APB_CNA and fixed AD7688 driver.	r20	smplClk : in STD_LOGIC;
		DataReady : out std_logic;
		smpout : out Samples_out(ChanelCount-1 downto 0);
		AD_in : in AD7688_in(ChanelCount-1 downto 0);
		AD_out : out AD7688_out
		);
		end component;

martin update ADC	r98	component WriteGen_ADC is
		port(
		clk : in std_logic;
		rstn : in std_logic;
		SmplCLK : in std_logic;
		DataReady : in std_logic;
		Full : in std_logic_vector(4 downto 0);
		ReUse : out std_logic_vector(4 downto 0);
		Write : out std_logic_vector(4 downto 0)
		);
		end component;
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
		end lpp_ad_conv;