@@ -41,7 +41,6 | |||||
41 | #define APID_TM_SCIENCE_NORMAL_BURST 0x0ccc // PID 76 CAT 12 |
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41 | #define APID_TM_SCIENCE_NORMAL_BURST 0x0ccc // PID 76 CAT 12 | |
42 | #define APID_TM_SCIENCE_SBM1_SBM2 0x0cfc // PID 79 CAT 12 |
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42 | #define APID_TM_SCIENCE_SBM1_SBM2 0x0cfc // PID 79 CAT 12 | |
43 | #define APID_TM_PARAMETER_DUMP 0x0cc6 // PID 76 CAT 6 |
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43 | #define APID_TM_PARAMETER_DUMP 0x0cc6 // PID 76 CAT 6 | |
44 | #define APID_TM_KCOEFFICIENTS_DUMP 0x0cc6 // PID 76 CAT 6 |
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45 |
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44 | |||
46 | // PACKET CAT |
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45 | // PACKET CAT | |
47 | #define TM_PACKET_CAT_TC_EXE 1 |
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46 | #define TM_PACKET_CAT_TC_EXE 1 |
@@ -111,11 +111,9 typedef struct ring_node | |||||
111 | #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688 |
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111 | #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688 | |
112 | #define TIME_OFFSET 2 |
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112 | #define TIME_OFFSET 2 | |
113 | #define TIME_OFFSET_IN_BYTES 8 |
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113 | #define TIME_OFFSET_IN_BYTES 8 | |
114 | //#define WAVEFORM_EXTENDED_HEADER_OFFSET 22 |
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115 | #define NB_BYTES_SWF_BLK (2 * 6) |
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114 | #define NB_BYTES_SWF_BLK (2 * 6) | |
116 | #define NB_WORDS_SWF_BLK 3 |
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115 | #define NB_WORDS_SWF_BLK 3 | |
117 | #define NB_BYTES_CWF3_LIGHT_BLK 6 |
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116 | #define NB_BYTES_CWF3_LIGHT_BLK 6 | |
118 | //#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8 |
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119 | #define NB_RING_NODES_F0 3 // AT LEAST 3 |
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117 | #define NB_RING_NODES_F0 3 // AT LEAST 3 | |
120 | #define NB_RING_NODES_F1 5 // AT LEAST 3 |
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118 | #define NB_RING_NODES_F1 5 // AT LEAST 3 | |
121 | #define NB_RING_NODES_F2 5 // AT LEAST 3 |
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119 | #define NB_RING_NODES_F2 5 // AT LEAST 3 | |
@@ -239,7 +237,6 typedef struct ring_node | |||||
239 | #define APB_OFFSET_VHDL_REV 0xb0 |
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237 | #define APB_OFFSET_VHDL_REV 0xb0 | |
240 | #define REGS_ADDR_VHDL_VERSION 0x80000ff0 |
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238 | #define REGS_ADDR_VHDL_VERSION 0x80000ff0 | |
241 |
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239 | |||
242 | #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff |
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243 | #define APBUART_CTRL_REG_MASK_TE 0x00000002 |
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240 | #define APBUART_CTRL_REG_MASK_TE 0x00000002 | |
244 | // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1 |
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241 | // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1 | |
245 | #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400 |
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242 | #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400 | |
@@ -330,7 +327,6 typedef struct ring_node | |||||
330 | #define MSG_QUEUE_COUNT_PRC1 10 |
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327 | #define MSG_QUEUE_COUNT_PRC1 10 | |
331 | #define MSG_QUEUE_COUNT_PRC2 5 |
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328 | #define MSG_QUEUE_COUNT_PRC2 5 | |
332 | #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1 |
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329 | #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1 | |
333 | #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options |
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334 | #define MSG_QUEUE_SIZE_PRC0 36 // two pointers, one rtems_event + 6 integers |
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330 | #define MSG_QUEUE_SIZE_PRC0 36 // two pointers, one rtems_event + 6 integers | |
335 | #define MSG_QUEUE_SIZE_PRC1 36 // two pointers, one rtems_event + 6 integers |
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331 | #define MSG_QUEUE_SIZE_PRC1 36 // two pointers, one rtems_event + 6 integers | |
336 | #define MSG_QUEUE_SIZE_PRC2 36 // two pointers, one rtems_event + 6 integers |
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332 | #define MSG_QUEUE_SIZE_PRC2 36 // two pointers, one rtems_event + 6 integers |
@@ -56,7 +56,6 | |||||
56 | #define DLEN_ASM_F0_PKT_1 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float |
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56 | #define DLEN_ASM_F0_PKT_1 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |
57 | #define DLEN_ASM_F0_PKT_2 2400 // 24 * 25 * 4, 25 components per matrix, 4 bytes per float |
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57 | #define DLEN_ASM_F0_PKT_2 2400 // 24 * 25 * 4, 25 components per matrix, 4 bytes per float | |
58 | #define ASM_F0_INDICE_START 16 // 17 - 1, (-1) due to the VHDL behaviour |
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58 | #define ASM_F0_INDICE_START 16 // 17 - 1, (-1) due to the VHDL behaviour | |
59 | #define ASM_F0_INDICE_STOP 103 // 104 - 1, 2 packets of 44 bins |
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60 | // |
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59 | // | |
61 | #define NB_BINS_PER_ASM_F1 104 |
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60 | #define NB_BINS_PER_ASM_F1 104 | |
62 | #define NB_BINS_PER_PKT_ASM_F1_1 36 |
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61 | #define NB_BINS_PER_PKT_ASM_F1_1 36 | |
@@ -64,13 +63,11 | |||||
64 | #define DLEN_ASM_F1_PKT_1 3600 // 36 * 25 * 4, 25 components per matrix, 4 bytes per float |
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63 | #define DLEN_ASM_F1_PKT_1 3600 // 36 * 25 * 4, 25 components per matrix, 4 bytes per float | |
65 | #define DLEN_ASM_F1_PKT_2 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float |
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64 | #define DLEN_ASM_F1_PKT_2 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |
66 | #define ASM_F1_INDICE_START 5 // 6 - 1, (-1) due to the VHDL behaviour |
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65 | #define ASM_F1_INDICE_START 5 // 6 - 1, (-1) due to the VHDL behaviour | |
67 | #define ASM_F1_INDICE_STOP 108 // 109 - 1, 2 packets of 52 bins |
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68 | // |
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66 | // | |
69 | #define NB_BINS_PER_ASM_F2 96 |
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67 | #define NB_BINS_PER_ASM_F2 96 | |
70 | #define NB_BINS_PER_PKT_ASM_F2 32 |
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68 | #define NB_BINS_PER_PKT_ASM_F2 32 | |
71 | #define DLEN_ASM_F2_PKT 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float |
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69 | #define DLEN_ASM_F2_PKT 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |
72 | #define ASM_F2_INDICE_START 6 // 7 - 1, (-1) due to the VHDL behaviour |
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70 | #define ASM_F2_INDICE_START 6 // 7 - 1, (-1) due to the VHDL behaviour | |
73 | #define ASM_F2_INDICE_STOP 101 // 102 - 1, 2 packets of 48 bins |
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74 | // |
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71 | // | |
75 | #define KCOEFF_BLK_SIZE 130 |
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72 | #define KCOEFF_BLK_SIZE 130 | |
76 | #define KCOEFF_FREQ 2 |
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73 | #define KCOEFF_FREQ 2 |
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