HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/JEANDET/LFR_FSW Changelog

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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » JEANDET » LFR_FSW

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Select second commit Show combined diff		Commit Message	Age	Author	Refs
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	`r167:6c1a4ac855d5`	timegen-qt project rebuilt	Fri, 26 Sep 2014 06:35:25	paul	patch rev 2	0
	`r166:b9d810e81e1d`	Many corrections done after Logiscope analysis	Wed, 24 Sep 2014 09:11:45	paul	patch rev 2	0
	`r165:c9daaae78ba2`	Creation of a spool task (SPOO) to handle	Thu, 28 Aug 2014 12:56:55	paul	spool	0
	`r164:3367da3ef050`	2.0.1.0 JIRA 283 corrected (acquisition_time)	Tue, 15 Jul 2014 14:04:09	paul	patch rev 2	0
	`r163:397b59567aca`	Sync before going back to 1.0.0.12 for sources delivery	Fri, 11 Jul 2014 07:48:17	paul	VHDLib206	0
	`r162:32d2a1c32a62`	Sync before going back to 1.0.0.12 for srec generation	Tue, 24 Jun 2014 10:53:02	paul	VHDLib206	0
	`r161:e0676cd8b3cd`	1.0.0.12 HK dummy packet removed	Mon, 23 Jun 2014 05:51:50	paul	VHDLib206	0
	`r160:75f8f2eae54e`	Bug 177 Bug 159 (period between snapshots)	Mon, 23 Jun 2014 05:10:29	paul	VHDLib206	0
	`r159:b822fb2ec6ef`	Bug 176	Fri, 20 Jun 2014 13:36:04	paul	VHDLib206	0
	`r158:8bd84199eb55`	Bug 174	Thu, 19 Jun 2014 06:44:49	paul	VHDLib206	0
	`r157:a703b578b7d4`	Bug 175	Thu, 19 Jun 2014 06:17:11	paul	VHDLib206	0
	`r156:ebd45713607b`	1.0.0.11	Tue, 17 Jun 2014 14:15:49	paul	VHDLib206	0
	`r155:6a098ef96fef`	Bug 117 sequence_cnt first value is 0 for the TM_LFR_SCIENCE_ packets	Tue, 17 Jun 2014 11:41:00	paul	VHDLib206	0
	`r154:57c7f914a70c`	Bug 171	Tue, 17 Jun 2014 11:25:19	paul	VHDLib206	0
	`r153:6bc069473488`	1.0.0.10 Bug 85	Tue, 17 Jun 2014 08:41:52	paul	VHDLib206	0
	`r152:de079a204567`	Bug 167 parameter checking updated	Tue, 17 Jun 2014 08:22:25	paul	VHDLib206	0
	`r151:058ea1100118`	Bug 171	Tue, 17 Jun 2014 05:36:14	paul	VHDLib206	0
	`r150:035669d03c81`	updates for the compliance with the spectral matrix VHDL design	Mon, 16 Jun 2014 13:54:41	paul	VHDLib206	0
	`r149:60ce8c978d3f`	Bug 117	Mon, 16 Jun 2014 07:27:42	paul	VHDLib206	0
	`r148:4ac63cfd5fe1`	1.0.0.9	Fri, 13 Jun 2014 07:38:32	paul	VHDLib206	0
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