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SID corrected in TM_LFR_TC_EXE packets...
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@@ -0,0 +1,26
1 #ifndef FSW_PARAMS_PROCESSING_H
2 #define FSW_PARAMS_PROCESSING_H
3
4 #define NB_BINS_PER_SM 128
5 #define NB_VALUES_PER_SM 25
6 #define TOTAL_SIZE_SM (NB_BINS_PER_SM * NB_VALUES_PER_SM)
7
8 #define NB_BINS_COMPRESSED_SM_F0 11
9 #define NB_BINS_COMPRESSED_SM_F1 13
10 #define NB_BINS_COMPRESSED_SM_F2 12
11 #define TOTAL_SIZE_COMPRESSED_MATRIX_f0 (NB_BINS_COMPRESSED_SM_F0 * NB_VALUES_PER_SM)
12 #define NB_AVERAGE_NORMAL_f0 96*4
13 #define NB_SM_TO_RECEIVE_BEFORE_AVF0 8
14
15 struct BP1_str{
16 volatile unsigned char PE[2];
17 volatile unsigned char PB[2];
18 volatile unsigned char V0;
19 volatile unsigned char V1;
20 volatile unsigned char V2_ELLIP_DOP;
21 volatile unsigned char SZ;
22 volatile unsigned char VPHI;
23 };
24 typedef struct BP1_str BP1_t;
25
26 #endif // FSW_PARAMS_PROCESSING_H
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@@ -1,6 +1,6
1 1 #############################################################################
2 # Makefile for building: bin/fsw
3 # Generated by qmake (2.01a) (Qt 4.8.4) on: Fri Jul 19 08:56:46 2013
2 # Makefile for building: bin/fsw-gsa
3 # Generated by qmake (2.01a) (Qt 4.8.4) on: Thu Jul 25 10:29:57 2013
4 4 # Project: fsw-qt.pro
5 5 # Template: app
6 6 # Command: /usr/bin/qmake-qt4 -spec /usr/lib64/qt4/mkspecs/linux-g++ -o Makefile fsw-qt.pro
@@ -10,7 +10,7
10 10
11 11 CC = sparc-rtems-gcc
12 12 CXX = sparc-rtems-g++
13 DEFINES = -DSW_VERSION_N1=0 -DSW_VERSION_N2=0 -DSW_VERSION_N3=0 -DSW_VERSION_N4=9 -DPRINT_MESSAGES_ON_CONSOLE
13 DEFINES = -DSW_VERSION_N1=0 -DSW_VERSION_N2=0 -DSW_VERSION_N3=0 -DSW_VERSION_N4=11 -DPRINT_MESSAGES_ON_CONSOLE -DGSA
14 14 CFLAGS = -pipe -O3 -Wall $(DEFINES)
15 15 CXXFLAGS = -pipe -O3 -Wall $(DEFINES)
16 16 INCPATH = -I/usr/lib64/qt4/mkspecs/linux-g++ -I. -I../src -I../header
@@ -78,9 +78,9 DIST = /usr/lib64/qt4/mkspecs/c
78 78 /usr/lib64/qt4/mkspecs/features/lex.prf \
79 79 /usr/lib64/qt4/mkspecs/features/include_source_dir.prf \
80 80 fsw-qt.pro
81 QMAKE_TARGET = fsw
81 QMAKE_TARGET = fsw-gsa
82 82 DESTDIR = bin/
83 TARGET = bin/fsw
83 TARGET = bin/fsw-gsa
84 84
85 85 first: all
86 86 ####### Implicit rules
@@ -159,8 +159,8 qmake: FORCE
159 159 @$(QMAKE) -spec /usr/lib64/qt4/mkspecs/linux-g++ -o Makefile fsw-qt.pro
160 160
161 161 dist:
162 @$(CHK_DIR_EXISTS) obj/fsw1.0.0 || $(MKDIR) obj/fsw1.0.0
163 $(COPY_FILE) --parents $(SOURCES) $(DIST) obj/fsw1.0.0/ && (cd `dirname obj/fsw1.0.0` && $(TAR) fsw1.0.0.tar fsw1.0.0 && $(COMPRESS) fsw1.0.0.tar) && $(MOVE) `dirname obj/fsw1.0.0`/fsw1.0.0.tar.gz . && $(DEL_FILE) -r obj/fsw1.0.0
162 @$(CHK_DIR_EXISTS) obj/fsw-gsa1.0.0 || $(MKDIR) obj/fsw-gsa1.0.0
163 $(COPY_FILE) --parents $(SOURCES) $(DIST) obj/fsw-gsa1.0.0/ && (cd `dirname obj/fsw-gsa1.0.0` && $(TAR) fsw-gsa1.0.0.tar fsw-gsa1.0.0 && $(COMPRESS) fsw-gsa1.0.0.tar) && $(MOVE) `dirname obj/fsw-gsa1.0.0`/fsw-gsa1.0.0.tar.gz . && $(DEL_FILE) -r obj/fsw-gsa1.0.0
164 164
165 165
166 166 clean:compiler_clean
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1 NO CONTENT: modified file, binary diff hidden
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1 NO CONTENT: modified file, binary diff hidden
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@@ -1,17 +1,17
1 1 TEMPLATE = app
2 2 # CONFIG += console v8 sim
3 3 # CONFIG options = verbose *** cpu_usage_report *** gsa
4 CONFIG += console verbose
4 CONFIG += console verbose gsa
5 5 CONFIG -= qt
6 6
7 7 include(./sparc.pri)
8 8
9 9 # flight software version
10 SWVERSION=-0-9
10 SWVERSION=-0-11
11 11 DEFINES += SW_VERSION_N1=0
12 12 DEFINES += SW_VERSION_N2=0
13 13 DEFINES += SW_VERSION_N3=0
14 DEFINES += SW_VERSION_N4=9
14 DEFINES += SW_VERSION_N4=11
15 15
16 16 contains( CONFIG, verbose ) {
17 17 DEFINES += PRINT_MESSAGES_ON_CONSOLE
@@ -47,5 +47,6 HEADERS += \
47 47 ../header/fsw_params.h \
48 48 ../header/fsw_misc.h \
49 49 ../header/fsw_init.h \
50 ../header/ccsds_types.h
50 ../header/ccsds_types.h \
51 ../header/fsw_params_processing.h
51 52
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@@ -1,6 +1,6
1 1 <?xml version="1.0" encoding="UTF-8"?>
2 2 <!DOCTYPE QtCreatorProject>
3 <!-- Written by QtCreator 2.7.0, 2013-07-19T08:53:16. -->
3 <!-- Written by QtCreator 2.7.0, 2013-07-25T07:26:34. -->
4 4 <qtcreator>
5 5 <data>
6 6 <variable>ProjectExplorer.Project.ActiveTarget</variable>
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@@ -1,7 +1,7
1
2 1 #ifndef CCSDS_H_INCLUDED
3 2 #define CCSDS_H_INCLUDED
4 3
4 #define CCSDS_PROTOCOLE_EXTRA_BYTES 4
5 5 #define CCSDS_TELEMETRY_HEADER_LENGTH 16+4
6 6 #define CCSDS_TM_PKT_MAX_SIZE 4412
7 7 #define CCSDS_TELECOMMAND_HEADER_LENGTH 10+4
@@ -25,12 +25,6
25 25 #define TM_PACKET_SEQ_CTRL_LAST 2
26 26 #define TM_PACKET_SEQ_CTRL_STANDALONE 3
27 27
28 // FAILURE CODES
29 #define FAILURE_CODE_INCONSISTENT 5 // 0x00 0x05
30 #define FAILURE_CODE_NOT_EXECUTABLE 42000 // 0xa4 0x10
31 #define FAILURE_CODE_NOT_IMPLEMENTED 42002 // 0xa4 0x12
32 #define FAILURE_CODE_ERROR 42003 // 0xa4 0x13
33 #define FAILURE_CODE_CORRUPTED 42005 // 0xa4 0x15
34 28 //
35 29 #define TM_DESTINATION_ID_GROUND 0
36 30 #define TM_DESTINATION_ID_MISSION_TIMELINE 110
@@ -108,6 +102,12
108 102 #define TM_SUBTYPE_SCIENCE 3
109 103 #define TM_SUBTYPE_LFR_SCIENCE 3
110 104
105 // FAILURE CODES
106 #define FAILURE_CODE_INCONSISTENT 5 // 0x00 0x05
107 #define FAILURE_CODE_NOT_EXECUTABLE 42000 // 0xa4 0x10
108 #define FAILURE_CODE_NOT_IMPLEMENTED 42002 // 0xa4 0x12
109 #define FAILURE_CODE_ERROR 42003 // 0xa4 0x13
110 #define FAILURE_CODE_CORRUPTED 42005 // 0xa4 0x15
111 111 // TM SID
112 112 #define SID_DEFAULT 0
113 113 #define SID_EXE_INC 5
@@ -149,6 +149,9
149 149 #define LENGTH_TM_LFR_TC_EXE_MAX 32
150 150 #define LENGTH_TM_LFR_HK 126
151 151
152 // HEADER_LENGTH
153 #define TM_HEADER_LEN 16
154 #define HEADER_LENGTH_TM_LFR_SCIENCE_ASM 28
152 155 // PACKET_LENGTH
153 156 #define PACKET_LENGTH_TC_EXE_SUCCESS (20 - CCSDS_TC_TM_PACKET_OFFSET)
154 157 #define PACKET_LENGTH_TC_EXE_INCONSISTENT (26 - CCSDS_TC_TM_PACKET_OFFSET)
@@ -158,7 +161,7
158 161 #define PACKET_LENGTH_TC_EXE_CORRUPTED (32 - CCSDS_TC_TM_PACKET_OFFSET)
159 162 #define PACKET_LENGTH_HK (126 - CCSDS_TC_TM_PACKET_OFFSET)
160 163 #define PACKET_LENGTH_PARAMETER_DUMP (34 - CCSDS_TC_TM_PACKET_OFFSET)
161 #define TM_HEADER_LEN 16
164 #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM (TOTAL_SIZE_SM + HEADER_LENGTH_TM_LFR_SCIENCE_ASM - CCSDS_TC_TM_PACKET_OFFSET)
162 165
163 166 #define SPARE1_PUSVERSION_SPARE2 0x10
164 167
@@ -264,6 +267,31 struct Header_TM_LFR_SCIENCE_CWF_str
264 267 };
265 268 typedef struct Header_TM_LFR_SCIENCE_CWF_str Header_TM_LFR_SCIENCE_CWF_t;
266 269
270 struct Header_TM_LFR_SCIENCE_ASM_str
271 {
272 volatile unsigned char targetLogicalAddress;
273 volatile unsigned char protocolIdentifier;
274 volatile unsigned char reserved;
275 volatile unsigned char userApplication;
276 volatile unsigned char packetID[2];
277 volatile unsigned char packetSequenceControl[2];
278 volatile unsigned char packetLength[2];
279 // DATA FIELD HEADER
280 volatile unsigned char spare1_pusVersion_spare2;
281 volatile unsigned char serviceType;
282 volatile unsigned char serviceSubType;
283 volatile unsigned char destinationID;
284 volatile unsigned char time[6];
285 // AUXILIARY HEADER
286 volatile unsigned char sid;
287 volatile unsigned char biaStatusInfo;
288 volatile unsigned char cntASM;
289 volatile unsigned char nrASM;
290 volatile unsigned char acquisitionTime[6];
291 volatile unsigned char blkNr[2];
292 };
293 typedef struct Header_TM_LFR_SCIENCE_ASM_str Header_TM_LFR_SCIENCE_ASM_t;
294
267 295 struct ccsdsTelecommandPacket_str
268 296 {
269 297 //unsigned char targetLogicalAddress; // removed by the grspw module
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@@ -17,6 +17,9 extern spw_stats spacewire_stats_backup;
17 17
18 18 int configure_timer(gptimer_regs_t *gptimer_regs, unsigned char timer, unsigned int clock_divider,
19 19 unsigned char interrupt_level, rtems_isr (*timer_isr)() );
20 int timer_start( gptimer_regs_t *gptimer_regs, unsigned char timer );
21 int timer_stop( gptimer_regs_t *gptimer_regs, unsigned char timer );
22 int timer_set_clock_divider(gptimer_regs_t *gptimer_regs, unsigned char timer, unsigned int clock_divider);
20 23 void update_spacewire_statistics();
21 24
22 25 // SERIAL LINK
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@@ -1,6 +1,8
1 1 #ifndef FSW_RTEMS_CONFIG_H_INCLUDED
2 2 #define FSW_RTEMS_CONFIG_H_INCLUDED
3 3
4 #include <fsw_params_processing.h>
5
4 6 #define GRSPW_DEVICE_NAME "/dev/grspw0"
5 7 #define UART_DEVICE_NAME "/dev/console"
6 8
@@ -30,7 +32,7
30 32 // NORM
31 33 #define DEFAULT_SY_LFR_N_SWF_L 2048 // nb sample
32 34 #define DEFAULT_SY_LFR_N_SWF_P 16 // sec
33 #define DEFAULT_SY_LFR_N_ASM_P 3600 // sec
35 #define DEFAULT_SY_LFR_N_ASM_P 16 // sec
34 36 #define DEFAULT_SY_LFR_N_BP_P0 4 // sec
35 37 #define DEFAULT_SY_LFR_N_BP_P1 20 // sec
36 38 // BURST
@@ -49,8 +51,12
49 51 #define REGS_ADDR_GPTIMER 0x80000300
50 52 #define REGS_ADDR_GRSPW 0x80000500
51 53 #define REGS_ADDR_TIME_MANAGEMENT 0x80000600
52 #define REGS_ADDR_SPECTRAL_MATRICES 0x80000700
53 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f20
54 #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
55
56 #ifdef GSA
57 #else
58 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f20
59 #endif
54 60
55 61 #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
56 62 #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400 (0x50)
@@ -67,11 +73,13
67 73 #define IRQ_SPARC_TIME2 0x1d // see sparcv8.pdf p.76 for interrupt levels
68 74 #define IRQ_WAVEFORM_PICKER 14
69 75 #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
76 #define IRQ_SPECTRAL_MATRIX 6
77 #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
70 78
71 79 //*****
72 80 // TIME
73 #define CLKDIV_SM_SIMULATOR 9999
74 #define CLKDIV_WF_SIMULATOR 9999999
81 #define CLKDIV_SM_SIMULATOR (10000 - 1) // 10 ms
82 #define CLKDIV_WF_SIMULATOR (10000000 - 1) // 10 000 000 * 1 us = 10 s
75 83 #define TIMER_SM_SIMULATOR 1
76 84 #define TIMER_WF_SIMULATOR 2
77 85 #define HK_PERIOD 100 // 100 * 10ms => 1sec
@@ -93,6 +101,7
93 101 #define TASKID_WFRM 8
94 102 #define TASKID_DUMB 9
95 103 #define TASKID_HOUS 10
104 #define TASKID_MATR 11
96 105
97 106 #define ACTION_MSG_QUEUE_COUNT 10
98 107
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@@ -1,33 +1,17
1 1 #ifndef FSW_RTEMS_PROCESSING_H_INCLUDED
2 2 #define FSW_RTEMS_PROCESSING_H_INCLUDED
3
4 #define NB_BINS_spec_mat 128
5 #define NB_VALUES_PER_spec_mat 25
6 #define TOTAL_SIZE_SPEC_MAT NB_BINS_spec_mat * NB_VALUES_PER_spec_mat
7 #define NB_BINS_COMPRESSED_MATRIX_f0 11
8 #define SIZE_COMPRESSED_spec_mat_f1 13
9 #define SIZE_COMPRESSED_spec_mat_f2 12
10 #define TOTAL_SIZE_COMPRESSED_MATRIX_f0 NB_BINS_COMPRESSED_MATRIX_f0 * NB_VALUES_PER_spec_mat
11 #define NB_AVERAGE_NORMAL_f0 96*4
12 #define NB_SM_TO_RECEIVE_BEFORE_AVF0 8
13 3
14 #include <rtems.h>
15 #include <grlib_regs.h>
4 #include <rtems.h>
5 #include <grspw.h>
6 #include <leon.h>
7
8 #include <fsw_init.h>
16 9 #include <fsw_params.h>
17 #include <stdio.h>
10 #include <grlib_regs.h>
11 #include <ccsds_types.h>
12
13 #include <stdio.h>
18 14 #include <stdlib.h>
19 #include <leon.h>
20
21 struct BP1_str{
22 volatile unsigned char PE[2];
23 volatile unsigned char PB[2];
24 volatile unsigned char V0;
25 volatile unsigned char V1;
26 volatile unsigned char V2_ELLIP_DOP;
27 volatile unsigned char SZ;
28 volatile unsigned char VPHI;
29 };
30 typedef struct BP1_str BP1_t;
31 15
32 16 extern volatile int spec_mat_f0_a[ ];
33 17 extern volatile int spec_mat_f0_b[ ];
@@ -37,30 +21,35 extern volatile int spec_mat_f0_e[ ];
37 21 extern volatile int spec_mat_f0_f[ ];
38 22 extern volatile int spec_mat_f0_g[ ];
39 23 extern volatile int spec_mat_f0_h[ ];
40 extern float averaged_spec_mat_f0[ ];
41 extern float compressed_spec_mat_f0[ ];
42 extern unsigned char LFR_BP1_F0[ ];
43
44 extern BP1_t data_BP1[ ];
45 24
46 25 extern rtems_id Task_id[ ]; /* array of task ids */
47
48 extern spectral_matrices_regs_t *spectral_matrices_regs;
49
26
27 extern time_management_regs_t *time_management_regs;
28 extern spectral_matrix_regs_t *spectral_matrix_regs;
29
50 30 // ISR
51 rtems_isr spectral_matrices_isr( rtems_vector_number vector );
52
31 rtems_isr spectral_matrices_isr( rtems_vector_number vector );
32
53 33 // RTEMS TASKS
54 34 rtems_task spw_bppr_task(rtems_task_argument argument);
55 35 rtems_task avf0_task(rtems_task_argument argument);
56 rtems_task bpf0_task(rtems_task_argument argument);
57 rtems_task smiq_task(rtems_task_argument argument); // added to test the spectral matrix simulator
36 rtems_task bpf0_task(rtems_task_argument argument);
37 rtems_task smiq_task(rtems_task_argument argument); // added to test the spectral matrix simulator
38 rtems_task matr_task(rtems_task_argument argument);
58 39
59 40 rtems_task spw_bppr_task_rate_monotonic(rtems_task_argument argument);
60 void matrix_average(volatile int *spec_mat, float *averaged_spec_mat);
61 void matrix_compression(float *averaged_spec_mat, unsigned char fChannel, float *compressed_spec_mat);
62 void matrix_reset(float *averaged_spec_mat);
41
42 void matrix_average(volatile int *spec_mat, volatile float *averaged_spec_mat);
43 void matrix_compression(volatile float *averaged_spec_mat, unsigned char fChannel, float *compressed_spec_mat);
44 void matrix_reset(volatile float *averaged_spec_mat);
63 45 void BP1_set(float * compressed_spec_mat, unsigned char nb_bins_compressed_spec_mat, unsigned char * LFR_BP1);
64 void BP2_set(float * compressed_spec_mat, unsigned char nb_bins_compressed_spec_mat);
46 void BP2_set(float * compressed_spec_mat, unsigned char nb_bins_compressed_spec_mat);
47 //
48 void init_header_asm( Header_TM_LFR_SCIENCE_ASM_t *header);
49 void send_spectral_matrix(Header_TM_LFR_SCIENCE_ASM_t *header, char *spectral_matrix,
50 unsigned int sid, spw_ioctl_pkt_send *spw_ioctl_send);
51 void convert_averaged_spectral_matrix(volatile float *input_matrix, char *output_matrix);
52 void init_averaged_spectral_matrix();
53 void reset_spectral_matrix_regs();
65 54
66 55 #endif // FSW_RTEMS_PROCESSING_H_INCLUDED
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@@ -37,13 +37,6 struct gptimer_regs_str
37 37 };
38 38 typedef struct gptimer_regs_str gptimer_regs_t;
39 39
40 struct spectral_matrices_regs_str{
41 volatile int ctrl;
42 volatile int address0;
43 volatile int address1;
44 };
45 typedef struct spectral_matrices_regs_str spectral_matrices_regs_t;
46
47 40 struct time_management_regs_str{
48 41 volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time
49 42 volatile int coarse_time_load;
@@ -68,4 +61,14 struct waveform_picker_regs_str{
68 61 };
69 62 typedef struct waveform_picker_regs_str waveform_picker_regs_t;
70 63
64 struct spectral_matrix_regs_str{
65 volatile int config;
66 volatile int status;
67 volatile int matrixF0_Address0;
68 volatile int matrixFO_Address1;
69 volatile int matrixF1_Address;
70 volatile int matrixF2_Address;
71 };
72 typedef struct spectral_matrix_regs_str spectral_matrix_regs_t;
73
71 74 #endif // GRLIBREGS_H_INCLUDED
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@@ -48,7 +48,7 void send_waveform_CWF( Header_TM_LFR_SC
48 48 void set_wfp_data_shaping(unsigned char data_shaping);
49 49 void set_wfp_delta_snapshot(unsigned int delta_snapshot);
50 50 void reset_wfp_burst_enable();
51 void reset_wfp_regs();
51 void reset_waveform_picker_regs();
52 52 //
53 53 int build_value(int value1, int value0);
54 54
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@@ -1,7 +1,9
1 #include <fsw_processing.h>
1 //#include <fsw_processing.h>
2 2 #include <rtems.h>
3 3 #include <grspw.h>
4 4 #include <ccsds_types.h>
5 #include <grlib_regs.h>
6 #include <fsw_params.h>
5 7
6 8 // RTEMS GLOBAL VARIABLES
7 9 rtems_name misc_name[5];
@@ -11,12 +13,14 rtems_name Task_name[15]; /* array
11 13 int fdSPW = 0;
12 14 int fdUART = 0;
13 15
14 spectral_matrices_regs_t *spectral_matrices_regs = NULL;
15
16 16 // APB CONFIGURATION REGISTERS
17 17 time_management_regs_t *time_management_regs = (time_management_regs_t*) REGS_ADDR_TIME_MANAGEMENT;
18 waveform_picker_regs_t *waveform_picker_regs = (waveform_picker_regs_t*) REGS_ADDR_WAVEFORM_PICKER;
19 18 gptimer_regs_t *gptimer_regs = (gptimer_regs_t *) REGS_ADDR_GPTIMER;
19 #ifdef GSA
20 #else
21 waveform_picker_regs_t *waveform_picker_regs = (waveform_picker_regs_t*) REGS_ADDR_WAVEFORM_PICKER;
22 #endif
23 spectral_matrix_regs_t *spectral_matrix_regs = (spectral_matrix_regs_t*) REGS_ADDR_SPECTRAL_MATRIX;
20 24
21 25 // WAVEFORMS GLOBAL VARIABLES // 2048 * 3 * 4 + 2 * 4 = 24576 + 8 bytes
22 26 volatile int wf_snap_f0[ NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK + TIME_OFFSET];
@@ -27,17 +31,21 volatile int wf_snap_f2_bis[ NB_SAMPLES_
27 31 volatile int wf_cont_f3[ NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK + TIME_OFFSET];
28 32
29 33 // SPECTRAL MATRICES GLOBAL VARIABLES
30 volatile int spec_mat_f0_a[ TOTAL_SIZE_SPEC_MAT ];
31 volatile int spec_mat_f0_b[ TOTAL_SIZE_SPEC_MAT ];
32 volatile int spec_mat_f0_c[ TOTAL_SIZE_SPEC_MAT ];
33 volatile int spec_mat_f0_d[ TOTAL_SIZE_SPEC_MAT ];
34 volatile int spec_mat_f0_e[ TOTAL_SIZE_SPEC_MAT ];
35 volatile int spec_mat_f0_f[ TOTAL_SIZE_SPEC_MAT ];
36 volatile int spec_mat_f0_g[ TOTAL_SIZE_SPEC_MAT ];
37 volatile int spec_mat_f0_h[ TOTAL_SIZE_SPEC_MAT ];
34 volatile int spec_mat_f0_a[ TOTAL_SIZE_SM ];
35 volatile int spec_mat_f0_b[ TOTAL_SIZE_SM ];
36 volatile int spec_mat_f0_c[ TOTAL_SIZE_SM ];
37 volatile int spec_mat_f0_d[ TOTAL_SIZE_SM ];
38 volatile int spec_mat_f0_e[ TOTAL_SIZE_SM ];
39 volatile int spec_mat_f0_f[ TOTAL_SIZE_SM ];
40 volatile int spec_mat_f0_g[ TOTAL_SIZE_SM ];
41 volatile int spec_mat_f0_h[ TOTAL_SIZE_SM ];
38 42 //
39 float averaged_spec_mat_f0[ TOTAL_SIZE_SPEC_MAT ];
40 float compressed_spec_mat_f0[ TOTAL_SIZE_COMPRESSED_MATRIX_f0 ];
43 volatile int spec_mat_f1_a[ TOTAL_SIZE_SM ];
44 volatile int spec_mat_f2_a[ TOTAL_SIZE_SM ];
45 //
46 volatile int spec_mat_f0_a_bis[ TOTAL_SIZE_SM ];
47 volatile int spec_mat_f1_a_bis[ TOTAL_SIZE_SM ];
48 volatile int spec_mat_f2_a_bis[ TOTAL_SIZE_SM ];
41 49
42 50 // MODE PARAMETERS
43 51 Packet_TM_LFR_PARAMETER_DUMP_t parameter_dump_packet;
@@ -50,7 +58,4 unsigned short sequenceCounters[SEQ_CNT_
50 58 spw_stats spacewire_stats;
51 59 spw_stats spacewire_stats_backup;
52 60
53 // BASIC PARAMETERS GLOBAL VARIABLES
54 unsigned char LFR_BP1_F0[ NB_BINS_COMPRESSED_MATRIX_f0 * 9 ];
55 BP1_t data_BP1[ NB_BINS_COMPRESSED_MATRIX_f0 ];
56 61
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@@ -55,7 +55,7 char *lstates[6] = {"Error-reset",
55 55 rtems_task Init( rtems_task_argument ignored )
56 56 {
57 57 rtems_status_code status;
58 rtems_isr_entry old_isr_handler;
58 rtems_isr_entry old_isr_handler;
59 59
60 60 PRINTF("\n\n\n\n\n")
61 61 PRINTF("***************************\n")
@@ -91,48 +91,26 rtems_task Init( rtems_task_argument ign
91 91
92 92 #ifdef GSA
93 93 // simulator
94 PRINTF("GSA is defined *** fsw-gsa is running \n")
95 94 configure_timer((gptimer_regs_t*) REGS_ADDR_GPTIMER, TIMER_WF_SIMULATOR, CLKDIV_WF_SIMULATOR,
96 95 IRQ_SPARC_WF, waveforms_simulator_isr );
96 LEON_Mask_interrupt( IRQ_WF );
97 97 #else
98 // configure the registers of the waveform picker
99 reset_wfp_regs();
100 // configure the waveform picker interrupt service routine
98 // configure the waveform picker
99 reset_waveform_picker_regs();
101 100 status = rtems_interrupt_catch( waveforms_isr,
102 101 IRQ_SPARC_WAVEFORM_PICKER,
103 102 &old_isr_handler) ;
104 103 LEON_Mask_interrupt( IRQ_WAVEFORM_PICKER );
104 // configure the spectral matrix
105 reset_spectral_matrix_regs();
106 status = rtems_interrupt_catch( waveforms_isr,
107 IRQ_SPARC_SPECTRAL_MATRIX,
108 &old_isr_handler) ;
109 LEON_Mask_interrupt( IRQ_SPECTRAL_MATRIX );
105 110 #endif
106 111
107 112 //**********
108 113
109 //*****************************************
110 // irq handling of the time management unit
111 status = rtems_interrupt_catch( commutation_isr1,
112 IRQ_SPARC_TIME1,
113 &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
114 if (status==RTEMS_SUCCESSFUL) {
115 PRINTF("OK *** commutation_isr1 *** rtems_interrupt_catch successfullly configured\n")
116 }
117
118 status = rtems_interrupt_catch( commutation_isr2,
119 IRQ_SPARC_TIME2,
120 &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
121 if (status==RTEMS_SUCCESSFUL) {
122 PRINTF("OK *** commutation_isr2 *** rtems_interrupt_catch successfullly configured\n")
123 }
124
125 LEON_Unmask_interrupt( IRQ_TIME1 );
126 LEON_Unmask_interrupt( IRQ_TIME2 );
127
128 #ifdef GSA
129 if (rtems_event_send( Task_id[TASKID_WFRM], RTEMS_EVENT_MODE_NORMAL ) != RTEMS_SUCCESSFUL) {
130 PRINTF("in INIT *** Error sending event to WFRM\n")
131 }
132 #endif
133
134 LEON_Force_interrupt(IRQ_WF);
135
136 114 status = rtems_task_delete(RTEMS_SELF);
137 115
138 116 }
@@ -261,6 +239,7 int create_names( void )
261 239 Task_name[TASKID_WFRM] = rtems_build_name( 'W', 'F', 'R', 'M' );
262 240 Task_name[TASKID_DUMB] = rtems_build_name( 'D', 'U', 'M', 'B' );
263 241 Task_name[TASKID_HOUS] = rtems_build_name( 'H', 'O', 'U', 'S' );
242 Task_name[TASKID_MATR] = rtems_build_name( 'M', 'A', 'T', 'R' );
264 243
265 244 // rate monotonic period name
266 245 HK_name = rtems_build_name( 'H', 'O', 'U', 'S' );
@@ -332,6 +311,12 int create_all_tasks( void )
332 311 RTEMS_DEFAULT_MODES,
333 312 RTEMS_DEFAULT_ATTRIBUTES, &Task_id[TASKID_HOUS]
334 313 );
314 // MATR
315 status = rtems_task_create(
316 Task_name[TASKID_MATR], 250, RTEMS_MINIMUM_STACK_SIZE * 2,
317 RTEMS_DEFAULT_MODES,
318 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_MATR]
319 );
335 320
336 321 return 0;
337 322 }
@@ -390,6 +375,11 int start_all_tasks( void )
390 375 PRINTF("In INIT *** Error starting TASK_HOUS\n")
391 376 }
392 377
378 status = rtems_task_start( Task_id[TASKID_MATR], matr_task, 1 );
379 if (status!=RTEMS_SUCCESSFUL) {
380 PRINTF("In INIT *** Error starting TASK_MATR\n")
381 }
382
393 383 return 0;
394 384 }
395 385
Show file before | Show file after | Hide comments
@@ -14,9 +14,18 int configure_timer(gptimer_regs_t *gpti
14 14 rtems_isr_entry old_isr_handler;
15 15
16 16 status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
17 //if (status==RTEMS_SUCCESSFUL) PRINTF("In configure_timer_for_wf_simulation *** rtems_interrupt_catch successfullly configured\n")
17 if (status==RTEMS_SUCCESSFUL)
18 {
19 PRINTF("In configure_timer *** rtems_interrupt_catch successfullly configured\n")
20 }
18 21
19 gptimer_regs->timer[timer].reload = clock_divider; // base clock frequency is 1 MHz
22 timer_set_clock_divider( gptimer_regs, timer, clock_divider);
23
24 return 1;
25 }
26
27 int timer_start(gptimer_regs_t *gptimer_regs, unsigned char timer)
28 {
20 29 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000010; // clear pending IRQ if any
21 30 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000004; // LD load value from the reload register
22 31 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000001; // EN enable the timer
@@ -26,6 +35,22 int configure_timer(gptimer_regs_t *gpti
26 35 return 1;
27 36 }
28 37
38 int timer_stop(gptimer_regs_t *gptimer_regs, unsigned char timer)
39 {
40 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & 0xfffffffe; // EN enable the timer
41 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & 0xffffffef; // IE interrupt enable
42 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000010; // clear pending IRQ if any
43
44 return 1;
45 }
46
47 int timer_set_clock_divider(gptimer_regs_t *gptimer_regs, unsigned char timer, unsigned int clock_divider)
48 {
49 gptimer_regs->timer[timer].reload = clock_divider; // base clock frequency is 1 MHz
50
51 return 1;
52 }
53
29 54 void update_spacewire_statistics()
30 55 {
31 56 rtems_status_code status;
@@ -189,9 +214,20 rtems_task hous_task(rtems_task_argument
189 214
190 215 update_spacewire_statistics();
191 216
217 // SEND PACKET
192 218 result = write ( fdSPW, &housekeeping_packet, LEN_TM_LFR_HK);
193 if (result==-1) {
194 PRINTF("ERR *** in HOUS *** HK send\n");
219 if (status == -1) {
220 while (true) {
221 if (status != RTEMS_SUCCESSFUL) {
222 result = write ( fdSPW, &housekeeping_packet, LEN_TM_LFR_HK);
223 PRINTF("x")
224 sched_yield();
225 }
226 else {
227 PRINTF("\n")
228 break;
229 }
230 }
195 231 }
196 232 }
197 233 }
Show file before | Show file after | Hide comments
@@ -3,6 +3,12
3 3
4 4 #include <fsw_processing_globals.c>
5 5
6 unsigned char LFR_BP1_F0[ NB_BINS_COMPRESSED_SM_F0 * 9 ];
7 BP1_t data_BP1[ NB_BINS_COMPRESSED_SM_F0 ];
8 float averaged_spec_mat_f0[ TOTAL_SIZE_SM ];
9 char averaged_spec_mat_f0_char[ TOTAL_SIZE_SM * 2 ];
10 float compressed_spec_mat_f0[ TOTAL_SIZE_COMPRESSED_MATRIX_f0 ];
11
6 12 //***********************************************************
7 13 // Interrupt Service Routine for spectral matrices processing
8 14 rtems_isr spectral_matrices_isr( rtems_vector_number vector )
@@ -17,15 +23,19 rtems_isr spectral_matrices_isr( rtems_v
17 23 rtems_task smiq_task(rtems_task_argument argument) // process the Spectral Matrices IRQ
18 24 {
19 25 rtems_event_set event_out;
20 unsigned char nb_interrupt_f0 = 0;
26 unsigned int nb_interrupt_f0 = 0;
27 unsigned int nb_interrupt_f0_MAX = 0;
28
29 nb_interrupt_f0_MAX = ( (parameter_dump_packet.sy_lfr_n_asm_p[0]) * 256
30 + parameter_dump_packet.sy_lfr_n_asm_p[1] ) * 100;
21 31
22 32 PRINTF("in SMIQ *** \n")
23 33
24 34 while(1){
25 35 rtems_event_receive(RTEMS_EVENT_0, RTEMS_WAIT, RTEMS_NO_TIMEOUT, &event_out); // wait for an RTEMS_EVENT0
26 36 nb_interrupt_f0 = nb_interrupt_f0 + 1;
27 if (nb_interrupt_f0 == (NB_SM_TO_RECEIVE_BEFORE_AVF0-1) ){
28 if (rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
37 if (nb_interrupt_f0 == nb_interrupt_f0_MAX ){
38 if (rtems_event_send( Task_id[TASKID_MATR], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
29 39 {
30 40 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
31 41 }
@@ -42,24 +52,20 rtems_task spw_bppr_task(rtems_task_argu
42 52 //static int nb_average_f1 = 0;
43 53 //static int nb_average_f2 = 0;
44 54
45 spectral_matrices_regs = (struct spectral_matrices_regs_str *) REGS_ADDR_SPECTRAL_MATRICES;
46 spectral_matrices_regs->address0 = (volatile int) spec_mat_f0_a;
47 spectral_matrices_regs->address1 = (volatile int) spec_mat_f0_b;
48
49 55 printf("in BPPR ***\n");
50 56
51 57 while(true){ // wait for an event to begin with the processing
52 58 status = rtems_event_receive(RTEMS_EVENT_0, RTEMS_WAIT, RTEMS_NO_TIMEOUT, &event_out);
53 59 if (status == RTEMS_SUCCESSFUL) {
54 if ((spectral_matrices_regs->ctrl & 0x00000001)==1) {
60 if ((spectral_matrix_regs->status & 0x00000001)==1) {
55 61 matrix_average(spec_mat_f0_a, averaged_spec_mat_f0);
56 spectral_matrices_regs->ctrl = spectral_matrices_regs->ctrl & 0xfffffffe;
62 spectral_matrix_regs->status = spectral_matrix_regs->status & 0xfffffffe;
57 63 //printf("f0_a\n");
58 64 Nb_average_f0++;
59 65 }
60 if (((spectral_matrices_regs->ctrl>>1) & 0x00000001)==1) {
66 if (((spectral_matrix_regs->status>>1) & 0x00000001)==1) {
61 67 matrix_average(spec_mat_f0_b, compressed_spec_mat_f0);
62 spectral_matrices_regs->ctrl = spectral_matrices_regs->ctrl & 0xfffffffd;
68 spectral_matrix_regs->status = spectral_matrix_regs->status & 0xfffffffd;
63 69 //printf("f0_b\n");
64 70 Nb_average_f0++;
65 71 }
@@ -73,23 +79,20 rtems_task spw_bppr_task(rtems_task_argu
73 79 }
74 80 }
75 81
76 rtems_task avf0_task(rtems_task_argument argument){
77 int i;
82 rtems_task avf0_task(rtems_task_argument argument)
83 {
84 //int i;
78 85 static int nb_average;
79 86 rtems_event_set event_out;
80 87 rtems_status_code status;
81 88
82 spectral_matrices_regs = (struct spectral_matrices_regs_str *) REGS_ADDR_SPECTRAL_MATRICES;
83 spectral_matrices_regs->address0 = (volatile int) spec_mat_f0_a;
84 spectral_matrices_regs->address1 = (volatile int) spec_mat_f0_b;
85
86 89 nb_average = 0;
87 90
88 91 PRINTF("in AVFO *** \n")
89 92
90 93 while(1){
91 94 rtems_event_receive(RTEMS_EVENT_0, RTEMS_WAIT, RTEMS_NO_TIMEOUT, &event_out); // wait for an RTEMS_EVENT0
92 for(i=0; i<TOTAL_SIZE_SPEC_MAT; i++){
95 /*for(i=0; i<TOTAL_SIZE_SM; i++){
93 96 averaged_spec_mat_f0[i] = averaged_spec_mat_f0[i] + spec_mat_f0_a[i]
94 97 + spec_mat_f0_b[i]
95 98 + spec_mat_f0_c[i]
@@ -98,20 +101,20 rtems_task avf0_task(rtems_task_argument
98 101 + spec_mat_f0_f[i]
99 102 + spec_mat_f0_g[i]
100 103 + spec_mat_f0_h[i];
101 }
102 spectral_matrices_regs->ctrl = spectral_matrices_regs->ctrl & 0xfffffffe; // reset the appropriate bit in the register
104 }*/
103 105 nb_average = nb_average + NB_SM_TO_RECEIVE_BEFORE_AVF0;
104 106 if (nb_average == NB_AVERAGE_NORMAL_f0) {
105 107 nb_average = 0;
106 status = rtems_event_send( Task_id[7], RTEMS_EVENT_0 ); // sending an event to the task 7, BPF0
108 status = rtems_event_send( Task_id[TASKID_MATR], RTEMS_EVENT_0 ); // sending an event to the task 7, BPF0
107 109 if (status != RTEMS_SUCCESSFUL) {
108 printf("iN TASK AVF0 *** Error sending RTEMS_EVENT_0, code %d\n", status);
110 printf("in AVF0 *** Error sending RTEMS_EVENT_0, code %d\n", status);
109 111 }
110 112 }
111 113 }
112 114 }
113 115
114 rtems_task bpf0_task(rtems_task_argument argument){
116 rtems_task bpf0_task(rtems_task_argument argument)
117 {
115 118 rtems_event_set event_out;
116 119
117 120 PRINTF("in BPFO *** \n")
@@ -119,17 +122,38 rtems_task bpf0_task(rtems_task_argument
119 122 while(1){
120 123 rtems_event_receive(RTEMS_EVENT_0, RTEMS_WAIT, RTEMS_NO_TIMEOUT, &event_out); // wait for an RTEMS_EVENT0
121 124 matrix_compression(averaged_spec_mat_f0, 0, compressed_spec_mat_f0);
122 BP1_set(compressed_spec_mat_f0, NB_BINS_COMPRESSED_MATRIX_f0, LFR_BP1_F0);
125 BP1_set(compressed_spec_mat_f0, NB_BINS_COMPRESSED_SM_F0, LFR_BP1_F0);
123 126 //PRINTF("IN TASK BPF0 *** Matrix compressed, parameters calculated\n")
124 127 }
125 128 }
126 129
130 rtems_task matr_task(rtems_task_argument argument)
131 {
132 spw_ioctl_pkt_send spw_ioctl_send_ASM;
133 rtems_event_set event_out;
134 Header_TM_LFR_SCIENCE_ASM_t headerASM;
135
136 init_header_asm( &headerASM );
137
138 PRINTF("in MATR *** \n")
139
140 init_averaged_spectral_matrix( );
141
142 while(1){
143 rtems_event_receive(RTEMS_EVENT_0, RTEMS_WAIT, RTEMS_NO_TIMEOUT, &event_out); // wait for an RTEMS_EVENT0
144
145 convert_averaged_spectral_matrix( averaged_spec_mat_f0, averaged_spec_mat_f0_char);
146
147 send_spectral_matrix( &headerASM, averaged_spec_mat_f0_char, SID_NORM_ASM_F0, &spw_ioctl_send_ASM);
148 }
149 }
150
127 151 //*****************************
128 152 // Spectral matrices processing
129 void matrix_average(volatile int *spec_mat, float *averaged_spec_mat)
153 void matrix_average(volatile int *spec_mat, volatile float *averaged_spec_mat)
130 154 {
131 155 int i;
132 for(i=0; i<TOTAL_SIZE_SPEC_MAT; i++){
156 for(i=0; i<TOTAL_SIZE_SM; i++){
133 157 averaged_spec_mat[i] = averaged_spec_mat[i] + spec_mat_f0_a[i]
134 158 + spec_mat_f0_b[i]
135 159 + spec_mat_f0_c[i]
@@ -141,21 +165,21 void matrix_average(volatile int *spec_m
141 165 }
142 166 }
143 167
144 void matrix_reset(float *averaged_spec_mat)
168 void matrix_reset(volatile float *averaged_spec_mat)
145 169 {
146 int i;
147 for(i=0; i<TOTAL_SIZE_SPEC_MAT; i++){
148 averaged_spec_mat_f0[i] = 0;
149 }
170 // int i;
171 // for(i=0; i<TOTAL_SIZE_SM; i++){
172 // averaged_spec_mat_f0[i] = 0;
173 // }
150 174 }
151 175
152 void matrix_compression(float *averaged_spec_mat, unsigned char fChannel, float *compressed_spec_mat)
176 void matrix_compression(volatile float *averaged_spec_mat, unsigned char fChannel, float *compressed_spec_mat)
153 177 {
154 178 int i;
155 179 int j;
156 180 switch (fChannel){
157 181 case 0:
158 for(i=0;i<NB_BINS_COMPRESSED_MATRIX_f0;i++){
182 for(i=0;i<NB_BINS_COMPRESSED_SM_F0;i++){
159 183 j = 17 + (i * 8);
160 184 compressed_spec_mat[i] = (averaged_spec_mat[j]
161 185 + averaged_spec_mat[j+1]
@@ -241,7 +265,7 void BP1_set(float * compressed_spec_mat
241 265 LFR_BP1[i*9+6] = LFR_BP1[i*9+6] | ((tmp_u_char&0x0f)<<3); // keeps 4 bits of the resulting unsigned char
242 266 //==============================================================
243 267 // BP1 degree of polarization == PAR_LFR_SC_BP1_DOP_F0 == 3 bits
244 for(j = 0; j<NB_VALUES_PER_spec_mat;j++){
268 for(j = 0; j<NB_VALUES_PER_SM;j++){
245 269 tr_SB_SB = compressed_spec_mat[i*30] * compressed_spec_mat[i*30]
246 270 + compressed_spec_mat[(i*30) + 10] * compressed_spec_mat[(i*30) + 10]
247 271 + compressed_spec_mat[(i*30) + 18] * compressed_spec_mat[(i*30) + 18]
@@ -361,3 +385,191 void BP2_set(float * compressed_spec_mat
361 385 }
362 386 }
363 387
388 void init_header_asm( Header_TM_LFR_SCIENCE_ASM_t *header)
389 {
390 header->targetLogicalAddress = CCSDS_DESTINATION_ID;
391 header->protocolIdentifier = CCSDS_PROTOCOLE_ID;
392 header->reserved = 0x00;
393 header->userApplication = CCSDS_USER_APP;
394 header->packetID[0] = (unsigned char) (TM_PACKET_ID_SCIENCE_NORMAL >> 8);
395 header->packetID[1] = (unsigned char) (TM_PACKET_ID_SCIENCE_NORMAL);
396 header->packetSequenceControl[0] = 0xc0;
397 header->packetSequenceControl[1] = 0x00;
398 header->packetLength[0] = 0x00;
399 header->packetLength[1] = 0x00;
400 // DATA FIELD HEADER
401 header->spare1_pusVersion_spare2 = 0x10;
402 header->serviceType = TM_TYPE_LFR_SCIENCE; // service type
403 header->serviceSubType = TM_SUBTYPE_LFR_SCIENCE; // service subtype
404 header->destinationID = TM_DESTINATION_ID_GROUND;
405 // AUXILIARY DATA HEADER
406 header->sid = 0x00;
407 header->biaStatusInfo = 0x00;
408 header->cntASM = 0x00;
409 header->nrASM = 0x00;
410 header->time[0] = 0x00;
411 header->time[0] = 0x00;
412 header->time[0] = 0x00;
413 header->time[0] = 0x00;
414 header->time[0] = 0x00;
415 header->time[0] = 0x00;
416 header->blkNr[0] = 0x00; // BLK_NR MSB
417 header->blkNr[1] = 0x00; // BLK_NR LSB
418 }
419
420 void send_spectral_matrix(Header_TM_LFR_SCIENCE_ASM_t *header, char *spectral_matrix,
421 unsigned int sid, spw_ioctl_pkt_send *spw_ioctl_send)
422 {
423 unsigned int i;
424 unsigned int length = 0;
425 rtems_status_code status;
426
427 header->sid = (unsigned char) sid;
428
429 for (i=0; i<2; i++)
430 {
431 // BUILD THE DATA
432 spw_ioctl_send->dlen = TOTAL_SIZE_SM;
433 spw_ioctl_send->data = &spectral_matrix[ i * TOTAL_SIZE_SM];
434 spw_ioctl_send->hlen = HEADER_LENGTH_TM_LFR_SCIENCE_ASM + CCSDS_PROTOCOLE_EXTRA_BYTES;
435 spw_ioctl_send->hdr = (char *) header;
436 spw_ioctl_send->options = 0;
437
438 // BUILD THE HEADER
439 length = PACKET_LENGTH_TM_LFR_SCIENCE_ASM;
440 header->packetLength[0] = (unsigned char) (length>>8);
441 header->packetLength[1] = (unsigned char) (length);
442 header->sid = (unsigned char) sid; // SID
443 header->cntASM = 2;
444 header->nrASM = (unsigned char) (i+1);
445 header->blkNr[0] =(unsigned char) ( (NB_BINS_PER_SM/2) >> 8 ); // BLK_NR MSB
446 header->blkNr[1] = (unsigned char) (NB_BINS_PER_SM/2); // BLK_NR LSB
447 // SET PACKET TIME
448 header->time[0] = (unsigned char) (time_management_regs->coarse_time>>24);
449 header->time[1] = (unsigned char) (time_management_regs->coarse_time>>16);
450 header->time[2] = (unsigned char) (time_management_regs->coarse_time>>8);
451 header->time[3] = (unsigned char) (time_management_regs->coarse_time);
452 header->time[4] = (unsigned char) (time_management_regs->fine_time>>8);
453 header->time[5] = (unsigned char) (time_management_regs->fine_time);
454 header->acquisitionTime[0] = (unsigned char) (time_management_regs->coarse_time>>24);
455 header->acquisitionTime[1] = (unsigned char) (time_management_regs->coarse_time>>16);
456 header->acquisitionTime[2] = (unsigned char) (time_management_regs->coarse_time>>8);
457 header->acquisitionTime[3] = (unsigned char) (time_management_regs->coarse_time);
458 header->acquisitionTime[4] = (unsigned char) (time_management_regs->fine_time>>8);
459 header->acquisitionTime[5] = (unsigned char) (time_management_regs->fine_time);
460 // SEND PACKET
461 status = write_spw(spw_ioctl_send);
462 if (status != RTEMS_SUCCESSFUL) {
463 while (true) {
464 if (status != RTEMS_SUCCESSFUL) {
465 status = write_spw(spw_ioctl_send);
466 //PRINTF1("%d", i)
467 sched_yield();
468 }
469 else {
470 //PRINTF("\n")
471 break;
472 }
473 }
474 }
475 }
476 }
477
478 void convert_averaged_spectral_matrix( volatile float *input_matrix, char *output_matrix)
479 {
480 unsigned int i;
481 unsigned int j;
482 char * pt_char_input;
483 char * pt_char_output;
484
485 pt_char_input = NULL;
486 pt_char_output = NULL;
487
488 for( i=0; i<NB_BINS_PER_SM; i++)
489 {
490 for ( j=0; j<NB_VALUES_PER_SM; j++)
491 {
492 pt_char_input = (char*) &input_matrix[ (i*NB_VALUES_PER_SM) + j ];
493 pt_char_output = (char*) &output_matrix[ 2 * ( (i*NB_VALUES_PER_SM) + j ) ];
494 pt_char_output[0] = pt_char_input[0]; // bits 31 downto 24 of the float
495 pt_char_output[1] = pt_char_input[1]; // bits 23 downto 16 of the float
496 }
497 }
498 }
499
500 void init_averaged_spectral_matrix( )
501 {
502 float offset = 10.;
503 float coeff = 100000.;
504 averaged_spec_mat_f0[ 0 + 25 * 0 ] = 0. + offset;
505 averaged_spec_mat_f0[ 0 + 25 * 1 ] = 1. + offset;
506 averaged_spec_mat_f0[ 0 + 25 * 2 ] = 2. + offset;
507 averaged_spec_mat_f0[ 0 + 25 * 3 ] = 3. + offset;
508 averaged_spec_mat_f0[ 0 + 25 * 4 ] = 4. + offset;
509 averaged_spec_mat_f0[ 0 + 25 * 5 ] = 5. + offset;
510 averaged_spec_mat_f0[ 0 + 25 * 6 ] = 6. + offset;
511 averaged_spec_mat_f0[ 0 + 25 * 7 ] = 7. + offset;
512 averaged_spec_mat_f0[ 0 + 25 * 8 ] = 8. + offset;
513 averaged_spec_mat_f0[ 0 + 25 * 9 ] = 9. + offset;
514 averaged_spec_mat_f0[ 0 + 25 * 10 ] = 10. + offset;
515 averaged_spec_mat_f0[ 0 + 25 * 11 ] = 11. + offset;
516 averaged_spec_mat_f0[ 0 + 25 * 12 ] = 12. + offset;
517 averaged_spec_mat_f0[ 0 + 25 * 13 ] = 13. + offset;
518 averaged_spec_mat_f0[ 0 + 25 * 14 ] = 14. + offset;
519 averaged_spec_mat_f0[ 9 + 25 * 0 ] = -(0. + offset)* coeff;
520 averaged_spec_mat_f0[ 9 + 25 * 1 ] = -(1. + offset)* coeff;
521 averaged_spec_mat_f0[ 9 + 25 * 2 ] = -(2. + offset)* coeff;
522 averaged_spec_mat_f0[ 9 + 25 * 3 ] = -(3. + offset)* coeff;
523 averaged_spec_mat_f0[ 9 + 25 * 4 ] = -(4. + offset)* coeff;
524 averaged_spec_mat_f0[ 9 + 25 * 5 ] = -(5. + offset)* coeff;
525 averaged_spec_mat_f0[ 9 + 25 * 6 ] = -(6. + offset)* coeff;
526 averaged_spec_mat_f0[ 9 + 25 * 7 ] = -(7. + offset)* coeff;
527 averaged_spec_mat_f0[ 9 + 25 * 8 ] = -(8. + offset)* coeff;
528 averaged_spec_mat_f0[ 9 + 25 * 9 ] = -(9. + offset)* coeff;
529 averaged_spec_mat_f0[ 9 + 25 * 10 ] = -(10. + offset)* coeff;
530 averaged_spec_mat_f0[ 9 + 25 * 11 ] = -(11. + offset)* coeff;
531 averaged_spec_mat_f0[ 9 + 25 * 12 ] = -(12. + offset)* coeff;
532 averaged_spec_mat_f0[ 9 + 25 * 13 ] = -(13. + offset)* coeff;
533 averaged_spec_mat_f0[ 9 + 25 * 14 ] = -(14. + offset)* coeff;
534 offset = 10000000;
535 averaged_spec_mat_f0[ 16 + 25 * 0 ] = (0. + offset)* coeff;
536 averaged_spec_mat_f0[ 16 + 25 * 1 ] = (1. + offset)* coeff;
537 averaged_spec_mat_f0[ 16 + 25 * 2 ] = (2. + offset)* coeff;
538 averaged_spec_mat_f0[ 16 + 25 * 3 ] = (3. + offset)* coeff;
539 averaged_spec_mat_f0[ 16 + 25 * 4 ] = (4. + offset)* coeff;
540 averaged_spec_mat_f0[ 16 + 25 * 5 ] = (5. + offset)* coeff;
541 averaged_spec_mat_f0[ 16 + 25 * 6 ] = (6. + offset)* coeff;
542 averaged_spec_mat_f0[ 16 + 25 * 7 ] = (7. + offset)* coeff;
543 averaged_spec_mat_f0[ 16 + 25 * 8 ] = (8. + offset)* coeff;
544 averaged_spec_mat_f0[ 16 + 25 * 9 ] = (9. + offset)* coeff;
545 averaged_spec_mat_f0[ 16 + 25 * 10 ] = (10. + offset)* coeff;
546 averaged_spec_mat_f0[ 16 + 25 * 11 ] = (11. + offset)* coeff;
547 averaged_spec_mat_f0[ 16 + 25 * 12 ] = (12. + offset)* coeff;
548 averaged_spec_mat_f0[ 16 + 25 * 13 ] = (13. + offset)* coeff;
549 averaged_spec_mat_f0[ 16 + 25 * 14 ] = (14. + offset)* coeff;
550
551 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 0 ] = averaged_spec_mat_f0[ 0 ];
552 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 1 ] = averaged_spec_mat_f0[ 1 ];
553 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 2 ] = averaged_spec_mat_f0[ 2 ];
554 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 3 ] = averaged_spec_mat_f0[ 3 ];
555 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 4 ] = averaged_spec_mat_f0[ 4 ];
556 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 5 ] = averaged_spec_mat_f0[ 5 ];
557 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 6 ] = averaged_spec_mat_f0[ 6 ];
558 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 7 ] = averaged_spec_mat_f0[ 7 ];
559 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 8 ] = averaged_spec_mat_f0[ 8 ];
560 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 9 ] = averaged_spec_mat_f0[ 9 ];
561 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 10 ] = averaged_spec_mat_f0[ 10 ];
562 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 11 ] = averaged_spec_mat_f0[ 11 ];
563 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 12 ] = averaged_spec_mat_f0[ 12 ];
564 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 13 ] = averaged_spec_mat_f0[ 13 ];
565 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 14 ] = averaged_spec_mat_f0[ 14 ];
566 averaged_spec_mat_f0[ (TOTAL_SIZE_SM/2) + 15 ] = averaged_spec_mat_f0[ 15 ];
567 }
568
569 void reset_spectral_matrix_regs()
570 {
571 #ifdef GSA
572 #else
573
574 #endif
575 }
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@@ -281,7 +281,7 unsigned char TM_build_header( enum TM_T
281 281 TMHeader->packetLength[0] = (unsigned char) (packetLength>>8);
282 282 TMHeader->packetLength[1] = (unsigned char) packetLength;
283 283 TMHeader->spare1_pusVersion_spare2 = 0x10;
284 TMHeader->destinationID = CCSDS_DESTINATION_ID; // default destination id
284 TMHeader->destinationID = TM_DESTINATION_ID_GROUND; // default destination id
285 285 switch (tm_type){
286 286 case(TM_LFR_TC_EXE_OK):
287 287 TMHeader->packetID[1] = (unsigned char) TM_PACKET_ID_TC_EXE;
@@ -293,6 +293,7 unsigned char TM_build_header( enum TM_T
293 293 TMHeader->packetID[1] = (unsigned char) TM_PACKET_ID_TC_EXE;
294 294 TMHeader->serviceType = TM_TYPE_TC_EXE; // type
295 295 TMHeader->serviceSubType = TM_SUBTYPE_EXE_NOK; // subtype
296 TMHeader->destinationID = tc_sid;
296 297 break;
297 298 case(TM_LFR_HK):
298 299 TMHeader->packetID[1] = (unsigned char) TM_PACKET_ID_HK;
@@ -880,15 +881,17 int stop_current_mode()
880 881 lfrMode = (housekeeping_packet.lfr_status_word[0] & 0xf0) >> 4; // get the current mode
881 882
882 883 // mask all IRQ lines related to signal processing
883 LEON_Mask_interrupt( IRQ_WF ); // mask waveform interrupt (coming from the timer VHDL IP)
884 884 LEON_Mask_interrupt( IRQ_SM ); // mask spectral matrices interrupt (coming from the timer VHDL IP)
885 LEON_Mask_interrupt( IRQ_WAVEFORM_PICKER ); // mask waveform picker interrupt
885 LEON_Clear_interrupt( IRQ_SM ); // clear spectral matrices interrupt (coming from the timer VHDL IP)
886 886
887 // clear all pending interruptions related to signal processing
887 #ifdef GSA
888 LEON_Mask_interrupt( IRQ_WF ); // mask waveform interrupt (coming from the timer VHDL IP)
888 889 LEON_Clear_interrupt( IRQ_WF ); // clear waveform interrupt (coming from the timer VHDL IP)
889 LEON_Clear_interrupt( IRQ_SM ); // clear spectral matrices interrupt (coming from the timer VHDL IP)
890 timer_stop( (gptimer_regs_t*) REGS_ADDR_GPTIMER, TIMER_WF_SIMULATOR );
891 #else
892 LEON_Mask_interrupt( IRQ_WAVEFORM_PICKER ); // mask waveform picker interrupt
890 893 LEON_Clear_interrupt( IRQ_WAVEFORM_PICKER ); // clear waveform picker interrupt
891
894 #endif
892 895 // suspend several tasks
893 896
894 897 if (lfrMode != LFR_MODE_STANDBY) {
@@ -907,7 +910,10 int stop_current_mode()
907 910 }
908 911
909 912 // initialize the registers
913 #ifdef GSA
914 #else
910 915 waveform_picker_regs->burst_enable = 0x00; // initialize
916 #endif
911 917
912 918 return status;
913 919 }
@@ -962,16 +968,21 int enter_normal_mode( ccsdsTelecommandP
962 968 }
963 969
964 970 #ifdef GSA
971 timer_start( (gptimer_regs_t*) REGS_ADDR_GPTIMER, TIMER_WF_SIMULATOR );
972 timer_start( (gptimer_regs_t*) REGS_ADDR_GPTIMER, TIMER_SM_SIMULATOR );
965 973 LEON_Clear_interrupt( IRQ_WF );
966 974 LEON_Unmask_interrupt( IRQ_WF );
975 LEON_Clear_interrupt( IRQ_SM ); // the IRQ_SM seems to be incompatible with the IRQ_WF on the xilinx board
976 LEON_Unmask_interrupt( IRQ_SM );
967 977 #else
968 978 LEON_Clear_interrupt( IRQ_WAVEFORM_PICKER );
969 979 LEON_Unmask_interrupt( IRQ_WAVEFORM_PICKER );
970 980 waveform_picker_regs->burst_enable = 0x07;
971 981 waveform_picker_regs->addr_data_f1 = (int) wf_snap_f1;
972 982 waveform_picker_regs->status = 0x00;
983 LEON_Clear_interrupt( IRQ_SM ); // the IRQ_SM seems to be incompatible with the IRQ_WF on the xilinx board
984 LEON_Unmask_interrupt( IRQ_SM );
973 985 #endif
974 LEON_Unmask_interrupt( IRQ_SM );
975 986
976 987 return status;
977 988 }
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@@ -134,42 +134,20 rtems_isr waveforms_simulator_isr( rtems
134 134 unsigned char lfrMode;
135 135 lfrMode = (housekeeping_packet.lfr_status_word[0] & 0xf0) >> 4;
136 136
137 switch(lfrMode)
138 {
139 //********
140 // STANDBY
141 case(LFR_MODE_STANDBY):
142 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_5 );
143 break;
144
145 //******
146 // NORMAL
147 case(LFR_MODE_NORMAL):
137 switch(lfrMode) {
138 case (LFR_MODE_STANDBY):
139 break;
140 case (LFR_MODE_NORMAL):
141 if (rtems_event_send( Task_id[TASKID_WFRM], RTEMS_EVENT_MODE_NORMAL ) != RTEMS_SUCCESSFUL) {
148 142 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_5 );
149 if (rtems_event_send( Task_id[TASKID_WFRM], RTEMS_EVENT_MODE_NORMAL ) != RTEMS_SUCCESSFUL) {
150 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_5 );
151 }
152 break;
153
154 //******
155 // BURST
156 case(LFR_MODE_BURST):
157 break;
158
159 //*****
160 // SBM1
161 case(LFR_MODE_SBM1):
162 break;
163
164 //*****
165 // SBM2
166 case(LFR_MODE_SBM2):
167 break;
168
169 //********
170 // DEFAULT
171 default:
172 break;
143 }
144 break;
145 case (LFR_MODE_BURST):
146 break;
147 case (LFR_MODE_SBM1):
148 break;
149 case (LFR_MODE_SBM2):
150 break;
173 151 }
174 152 }
175 153
@@ -215,6 +193,8 rtems_task wfrm_task(rtems_task_argument
215 193 break;
216 194 case(LFR_MODE_SBM1):
217 195 send_waveform_sbm1( &headerCWF, &spw_ioctl_send_CWF);
196 #ifdef GSA
197 #else
218 198 param_local.local_sbm1_nb_cwf_sent ++;
219 199 if ( param_local.local_sbm1_nb_cwf_sent == (param_local.local_sbm1_nb_cwf_max-1) ) {
220 200 // send the f1 buffer as a NORM snapshot
@@ -225,9 +205,12 rtems_task wfrm_task(rtems_task_argument
225 205 send_waveform_SWF( &headerSWF, wf_snap_f1, SID_NORM_SWF_F1, &spw_ioctl_send_SWF );
226 206 }
227 207 }
208 #endif
228 209 break;
229 210 case(LFR_MODE_SBM2):
230 211 send_waveform_sbm2( &headerCWF, &spw_ioctl_send_CWF);
212 #ifdef GSA
213 #else
231 214 param_local.local_sbm2_nb_cwf_sent ++;
232 215 if ( param_local.local_sbm2_nb_cwf_sent == (param_local.local_sbm2_nb_cwf_max-1) ) {
233 216 // send the f2 buffer as a NORM snapshot
@@ -238,6 +221,7 rtems_task wfrm_task(rtems_task_argument
238 221 send_waveform_SWF( &headerSWF, wf_snap_f2, SID_NORM_SWF_F2, &spw_ioctl_send_SWF );
239 222 }
240 223 }
224 #endif
241 225 break;
242 226 default:
243 227 break;
@@ -553,7 +537,7 void send_waveform_norm(Header_TM_LFR_SC
553 537 // irq processed, reset the related register of the timer unit
554 538 gptimer_regs->timer[TIMER_WF_SIMULATOR].ctrl = gptimer_regs->timer[TIMER_WF_SIMULATOR].ctrl | 0x00000010;
555 539 // clear the interruption
556 LEON_Clear_interrupt(IRQ_WF);
540 LEON_Unmask_interrupt( IRQ_WF );
557 541 #else
558 542 // irq processed, reset the related register of the waveform picker
559 543 if (lfrMode == LFR_MODE_SBM1) {
@@ -576,8 +560,8 void send_waveform_norm(Header_TM_LFR_SC
576 560 waveform_picker_regs->status = waveform_picker_regs->status & 0x00;
577 561 waveform_picker_regs->burst_enable = 0x07; // [0111] enable f2 f1 f0
578 562 }
563 #endif
579 564
580 #endif
581 565 }
582 566
583 567 void send_waveform_burst(Header_TM_LFR_SCIENCE_CWF_t *header, spw_ioctl_pkt_send *spw_ioctl_send)
@@ -594,12 +578,15 void send_waveform_burst(Header_TM_LFR_S
594 578 // ACQUISITION TIME
595 579
596 580 // F2
581 #ifdef GSA
582 #else
597 583 if (waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2) {
598 584 send_waveform_CWF( header, wf_snap_f2_bis, SID_BURST_CWF_F2, spw_ioctl_send);
599 585 }
600 586 else {
601 587 send_waveform_CWF( header, wf_snap_f2, SID_BURST_CWF_F2, spw_ioctl_send);
602 588 }
589 #endif
603 590 }
604 591
605 592 void send_waveform_sbm1(Header_TM_LFR_SCIENCE_CWF_t *header, spw_ioctl_pkt_send *spw_ioctl_send)
@@ -615,12 +602,15 void send_waveform_sbm1(Header_TM_LFR_SC
615 602 header->time[5] = (unsigned char) (time_management_regs->fine_time);
616 603
617 604 // F1
605 #ifdef GSA
606 #else
618 607 if (waveform_picker_regs->addr_data_f1 == (int) wf_snap_f1) {
619 608 send_waveform_CWF( header, wf_snap_f1_bis, SID_SBM1_CWF_F1, spw_ioctl_send );
620 609 }
621 610 else {
622 611 send_waveform_CWF( header, wf_snap_f1, SID_SBM1_CWF_F1, spw_ioctl_send );
623 612 }
613 #endif
624 614 }
625 615
626 616 void send_waveform_sbm2(Header_TM_LFR_SCIENCE_CWF_t *header, spw_ioctl_pkt_send *spw_ioctl_send)
@@ -636,12 +626,15 void send_waveform_sbm2(Header_TM_LFR_SC
636 626 header->time[5] = (unsigned char) (time_management_regs->fine_time);
637 627
638 628 // F2
629 #ifdef GSA
630 #else
639 631 if (waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2) {
640 632 send_waveform_CWF( header, wf_snap_f2_bis, SID_SBM2_CWF_F2, spw_ioctl_send);
641 633 }
642 634 else {
643 635 send_waveform_CWF( header, wf_snap_f2, SID_SBM2_CWF_F2, spw_ioctl_send);
644 636 }
637 #endif
645 638 }
646 639
647 640 //**************
@@ -650,29 +643,39 void set_wfp_data_shaping(unsigned char
650 643 {
651 644 // get the parameters for the data shaping [BW SP0 SP1 R0 R1] in sy_lfr_common1 and configure the register
652 645 // waveform picker : [R1 R0 SP1 SP0 BW]
646 #ifdef GSA
647 #else
653 648 waveform_picker_regs->data_shaping =
654 649 ( (data_shaping & 0x10) >> 4 ) // BW
655 650 + ( (data_shaping & 0x08) >> 2 ) // SP0
656 651 + ( (data_shaping & 0x04) ) // SP1
657 652 + ( (data_shaping & 0x02) << 2 ) // R0
658 653 + ( (data_shaping & 0x01) << 4 ); // R1
654 #endif
659 655 }
660 656
661 657 void set_wfp_delta_snapshot(unsigned int delta_snapshot)
662 658 {
659 #ifdef GSA
660 #else
663 661 unsigned char aux = 0;
664 662 aux = delta_snapshot / 2 ;
665 663 waveform_picker_regs->delta_snapshot = aux; // max 2 bytes
666 //waveform_picker_regs->delta_snapshot = 0x5; // max 2 bytes
664 #endif
667 665 }
668 666
669 667 void reset_wfp_burst_enable()
670 668 {
669 #ifdef GSA
670 #else
671 671 waveform_picker_regs->burst_enable = 0x00; // burst f2, f1, f0 enable f3, f2, f1, f0
672 #endif
672 673 }
673 674
674 void reset_wfp_regs()
675 void reset_waveform_picker_regs()
675 676 {
677 #ifdef GSA
678 #else
676 679 set_wfp_data_shaping(parameter_dump_packet.bw_sp0_sp1_r0_r1);
677 680 reset_wfp_burst_enable();
678 681 waveform_picker_regs->addr_data_f0 = (int) (wf_snap_f0); //
@@ -687,9 +690,5 void reset_wfp_regs()
687 690 waveform_picker_regs->delta_f2_f0 = 0x17c00; // max 5 bytes
688 691 waveform_picker_regs->nb_burst_available = 0x180; // max 3 bytes, size of the buffer in burst (1 burst = 16 x 4 octets)
689 692 waveform_picker_regs->nb_snapshot_param = 0x7ff; // max 3 octets, 2048 - 1
690 //waveform_picker_regs->delta_snapshot = 0x2; // max 2 bytes, = period / 2
691 //waveform_picker_regs->delta_f2_f1 = 0x2d00; // max 4 bytes
692 //waveform_picker_regs->delta_f2_f0 = 0x2f80; // max 5 bytes
693 //waveform_picker_regs->nb_burst_available = 0x30; // max 3 bytes, size of the buffer in burst (1 burst = 16 x 4 octets)
694 //waveform_picker_regs->nb_snapshot_param = 0xff; // max 3 octets, 256 - 1
693 #endif
695 694 }
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