@@ -1,2 +1,2 | |||||
1 | 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters |
|
1 | 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters | |
2 | 3e4216a0e6981bead8bcb201012ebadb53f60dff header/lfr_common_headers |
|
2 | 6bab694410c69700e3455ffba21ce58dbb4da870 header/lfr_common_headers |
@@ -10,6 +10,30 | |||||
10 | #include "fsw_spacewire.h" |
|
10 | #include "fsw_spacewire.h" | |
11 | #include "lfr_cpu_usage_report.h" |
|
11 | #include "lfr_cpu_usage_report.h" | |
12 |
|
12 | |||
|
13 | #define LFR_RESET_CAUSE_UNKNOWN_CAUSE 0 | |||
|
14 | #define WATCHDOG_LOOP_PRINTF 10 | |||
|
15 | #define WATCHDOG_LOOP_DEBUG 3 | |||
|
16 | ||||
|
17 | #define DUMB_MESSAGE_NB 15 | |||
|
18 | #define NB_RTEMS_EVENTS 32 | |||
|
19 | #define EVENT_12 12 | |||
|
20 | #define EVENT_13 13 | |||
|
21 | #define EVENT_14 14 | |||
|
22 | #define DUMB_MESSAGE_0 "in DUMB *** default" | |||
|
23 | #define DUMB_MESSAGE_1 "in DUMB *** timecode_irq_handler" | |||
|
24 | #define DUMB_MESSAGE_2 "in DUMB *** f3 buffer changed" | |||
|
25 | #define DUMB_MESSAGE_3 "in DUMB *** in SMIQ *** Error sending event to AVF0" | |||
|
26 | #define DUMB_MESSAGE_4 "in DUMB *** spectral_matrices_isr *** Error sending event to SMIQ" | |||
|
27 | #define DUMB_MESSAGE_5 "in DUMB *** waveforms_simulator_isr" | |||
|
28 | #define DUMB_MESSAGE_6 "VHDL SM *** two buffers f0 ready" | |||
|
29 | #define DUMB_MESSAGE_7 "ready for dump" | |||
|
30 | #define DUMB_MESSAGE_8 "VHDL ERR *** spectral matrix" | |||
|
31 | #define DUMB_MESSAGE_9 "tick" | |||
|
32 | #define DUMB_MESSAGE_10 "VHDL ERR *** waveform picker" | |||
|
33 | #define DUMB_MESSAGE_11 "VHDL ERR *** unexpected ready matrix values" | |||
|
34 | #define DUMB_MESSAGE_12 "WATCHDOG timer" | |||
|
35 | #define DUMB_MESSAGE_13 "TIMECODE timer" | |||
|
36 | #define DUMB_MESSAGE_14 "TIMECODE ISR" | |||
13 |
|
37 | |||
14 | enum lfr_reset_cause_t{ |
|
38 | enum lfr_reset_cause_t{ | |
15 | UNKNOWN_CAUSE, |
|
39 | UNKNOWN_CAUSE, | |
@@ -46,8 +70,6 extern gptimer_regs_t *gptimer_regs; | |||||
46 | extern void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int*, unsigned int* ); |
|
70 | extern void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int*, unsigned int* ); | |
47 | extern void CCR_getInstructionAndDataErrorCounters( unsigned int*, unsigned int* ); |
|
71 | extern void CCR_getInstructionAndDataErrorCounters( unsigned int*, unsigned int* ); | |
48 |
|
72 | |||
49 | #define LFR_RESET_CAUSE_UNKNOWN_CAUSE 0 |
|
|||
50 |
|
||||
51 | rtems_name name_hk_rate_monotonic; // name of the HK rate monotonic |
|
73 | rtems_name name_hk_rate_monotonic; // name of the HK rate monotonic | |
52 | rtems_id HK_id; // id of the HK rate monotonic period |
|
74 | rtems_id HK_id; // id of the HK rate monotonic period | |
53 | rtems_name name_avgv_rate_monotonic; // name of the AVGV rate monotonic |
|
75 | rtems_name name_avgv_rate_monotonic; // name of the AVGV rate monotonic |
@@ -13,6 +13,15 | |||||
13 | #include "tc_handler.h" |
|
13 | #include "tc_handler.h" | |
14 | #include "fsw_init.h" |
|
14 | #include "fsw_init.h" | |
15 |
|
15 | |||
|
16 | #define SPW_LINK_OK 5 | |||
|
17 | #define CONF_TCODE_CTRL 0x0909 // [Time Rx : Time Tx : Link error : Tick-out IRQ] | |||
|
18 | #define SPW_BIT_NP 0x00100000 // [NP] set the No port force bit | |||
|
19 | #define SPW_BIT_NP_MASK 0xffdfffff | |||
|
20 | #define SPW_BIT_RE 0x00010000 // [RE] set the RMAP Enable bit | |||
|
21 | #define SPW_BIT_RE_MASK 0xfffdffff | |||
|
22 | #define SPW_LINK_STAT_POS 21 | |||
|
23 | #define SPW_TIMECODE_MAX 63 | |||
|
24 | ||||
16 | extern spw_stats grspw_stats; |
|
25 | extern spw_stats grspw_stats; | |
17 | extern rtems_name timecode_timer_name; |
|
26 | extern rtems_name timecode_timer_name; | |
18 | extern rtems_id timecode_timer_id; |
|
27 | extern rtems_id timecode_timer_id; |
@@ -30,6 +30,18 typedef struct { | |||||
30 | volatile unsigned int unused; |
|
30 | volatile unsigned int unused; | |
31 | } timer_regs_t; |
|
31 | } timer_regs_t; | |
32 |
|
32 | |||
|
33 | //************* | |||
|
34 | //************* | |||
|
35 | // GPTIMER_REGS | |||
|
36 | ||||
|
37 | #define GPTIMER_CLEAR_IRQ 0x00000010 // clear pending IRQ if any | |||
|
38 | #define GPTIMER_LD 0x00000004 // LD load value from the reload register | |||
|
39 | #define GPTIMER_EN 0x00000001 // EN enable the timer | |||
|
40 | #define GPTIMER_EN_MASK 0xfffffffe // EN enable the timer | |||
|
41 | #define GPTIMER_RS 0x00000002 // RS restart | |||
|
42 | #define GPTIMER_IE 0x00000008 // IE interrupt enable | |||
|
43 | #define GPTIMER_IE_MASK 0xffffffef // IE interrupt enable | |||
|
44 | ||||
33 | typedef struct { |
|
45 | typedef struct { | |
34 | volatile unsigned int scaler_value; |
|
46 | volatile unsigned int scaler_value; | |
35 | volatile unsigned int scaler_reload; |
|
47 | volatile unsigned int scaler_reload; | |
@@ -38,6 +50,25 typedef struct { | |||||
38 | timer_regs_t timer[NB_GPTIMER]; |
|
50 | timer_regs_t timer[NB_GPTIMER]; | |
39 | } gptimer_regs_t; |
|
51 | } gptimer_regs_t; | |
40 |
|
52 | |||
|
53 | //********************* | |||
|
54 | //********************* | |||
|
55 | // TIME_MANAGEMENT_REGS | |||
|
56 | ||||
|
57 | #define VAL_SOFTWARE_RESET 0x02 // [0010] software reset | |||
|
58 | #define VAL_LFR_SYNCHRONIZED 0x80000000 | |||
|
59 | #define BIT_SYNCHRONIZATION 31 | |||
|
60 | #define COARSE_TIME_MASK 0x7fffffff | |||
|
61 | #define SYNC_BIT_MASK 0x7f | |||
|
62 | #define SYNC_BIT 0x80 | |||
|
63 | #define BIT_CAL_RELOAD 0x00000010 | |||
|
64 | #define MASK_CAL_RELOAD 0xffffffef // [1110 1111] | |||
|
65 | #define BIT_CAL_ENABLE 0x00000040 | |||
|
66 | #define MASK_CAL_ENABLE 0xffffffbf // [1011 1111] | |||
|
67 | #define BIT_SET_INTERLEAVED 0x00000020 // [0010 0000] | |||
|
68 | #define MASK_SET_INTERLEAVED 0xffffffdf // [1101 1111] | |||
|
69 | #define BIT_SOFT_RESET 0x00000004 // [0100] | |||
|
70 | #define MASK_SOFT_RESET 0xfffffffb // [1011] | |||
|
71 | ||||
41 | typedef struct { |
|
72 | typedef struct { | |
42 | volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time |
|
73 | volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time | |
43 | // bit 1 is the soft reset for the time management module |
|
74 | // bit 1 is the soft reset for the time management module | |
@@ -57,6 +88,45 typedef struct { | |||||
57 | volatile unsigned int calData; |
|
88 | volatile unsigned int calData; | |
58 | } time_management_regs_t; |
|
89 | } time_management_regs_t; | |
59 |
|
90 | |||
|
91 | //********************* | |||
|
92 | //********************* | |||
|
93 | // WAVEFORM_PICKER_REGS | |||
|
94 | ||||
|
95 | #define BITS_WFP_STATUS_F3 0xc0 // [1100 0000] check the f3 full bits | |||
|
96 | #define BIT_WFP_BUF_F3_0 0x40 // [0100 0000] f3 buffer 0 is full | |||
|
97 | #define BIT_WFP_BUF_F3_1 0x80 // [1000 0000] f3 buffer 1 is full | |||
|
98 | #define RST_WFP_F3_0 0x00008840 // [1000 1000 0100 0000] | |||
|
99 | #define RST_WFP_F3_1 0x00008880 // [1000 1000 1000 0000] | |||
|
100 | ||||
|
101 | #define BITS_WFP_STATUS_F2 0x30 // [0011 0000] get the status bits for f2 | |||
|
102 | #define SHIFT_WFP_STATUS_F2 4 | |||
|
103 | #define BIT_WFP_BUF_F2_0 0x10 // [0001 0000] f2 buffer 0 is full | |||
|
104 | #define BIT_WFP_BUF_F2_1 0x20 // [0010 0000] f2 buffer 1 is full | |||
|
105 | #define RST_WFP_F2_0 0x00004410 // [0100 0100 0001 0000] | |||
|
106 | #define RST_WFP_F2_1 0x00004420 // [0100 0100 0010 0000] | |||
|
107 | ||||
|
108 | #define BITS_WFP_STATUS_F1 0x0c // [0000 1100] check the f1 full bits | |||
|
109 | #define BIT_WFP_BUF_F1_0 0x04 // [0000 0100] f1 buffer 0 is full | |||
|
110 | #define BIT_WFP_BUF_F1_1 0x08 // [0000 1000] f1 buffer 1 is full | |||
|
111 | #define RST_WFP_F1_0 0x00002204 // [0010 0010 0000 0100] f1 bits = 0 | |||
|
112 | #define RST_WFP_F1_1 0x00002208 // [0010 0010 0000 1000] f1 bits = 0 | |||
|
113 | ||||
|
114 | #define BITS_WFP_STATUS_F0 0x03 // [0000 0011] check the f0 full bits | |||
|
115 | #define RST_WFP_F0_0 0x00001101 // [0001 0001 0000 0001] | |||
|
116 | #define RST_WFP_F0_1 0x00001102 // [0001 0001 0000 0010] | |||
|
117 | ||||
|
118 | #define BIT_WFP_BUFFER_0 0x01 | |||
|
119 | #define BIT_WFP_BUFFER_1 0x02 | |||
|
120 | ||||
|
121 | #define RST_BITS_RUN_BURST_EN 0x80 // [1000 0000] burst f2, f1, f0 enable f3, f2, f1, f0 | |||
|
122 | #define RUN_BURST_ENABLE_SBM2 0x60 // [0110 0000] enable f2 and f1 burst | |||
|
123 | #define RUN_BURST_ENABLE_BURST 0x40 // [0100 0000] f2 burst enabled | |||
|
124 | ||||
|
125 | #define DFLT_WFP_NB_DATA_BY_BUFFER 0xa7f // 0x30 *** 2688 - 1 => nb samples -1 | |||
|
126 | #define DFLT_WFP_SNAPSHOT_PARAM 0xa80 // 0x34 *** 2688 => nb samples | |||
|
127 | #define DFLT_WFP_BUFFER_LENGTH 0x1f8 // buffer length in burst = 3 * 2688 / 16 = 504 = 0x1f8 | |||
|
128 | #define DFLT_WFP_DELTA_F0_2 0x30 // 48 = 11 0000, max 7 bits | |||
|
129 | ||||
60 | // PDB >= 0.1.28, 0x80000f54 |
|
130 | // PDB >= 0.1.28, 0x80000f54 | |
61 | typedef struct{ |
|
131 | typedef struct{ | |
62 | int data_shaping; // 0x00 00 *** R2 R1 R0 SP1 SP0 BW |
|
132 | int data_shaping; // 0x00 00 *** R2 R1 R0 SP1 SP0 BW | |
@@ -106,6 +176,29 typedef struct{ | |||||
106 | volatile unsigned int e2; // 0x98 |
|
176 | volatile unsigned int e2; // 0x98 | |
107 | } waveform_picker_regs_0_1_18_t; |
|
177 | } waveform_picker_regs_0_1_18_t; | |
108 |
|
178 | |||
|
179 | //********************* | |||
|
180 | //********************* | |||
|
181 | // SPECTRAL_MATRIX_REGS | |||
|
182 | ||||
|
183 | #define BITS_STATUS_F0 0x03 // [0011] | |||
|
184 | #define BITS_STATUS_F1 0x0c // [1100] | |||
|
185 | #define BITS_STATUS_F2 0x30 // [0011 0000] | |||
|
186 | #define BITS_HK_AA_SM 0x780 // [0111 1000 0000] | |||
|
187 | #define BITS_SM_ERR 0x7c0 // [0111 1100 0000] | |||
|
188 | #define BITS_STATUS_REG 0x7ff // [0111 1111 1111] | |||
|
189 | #define BIT_READY_0 0x1 // [01] | |||
|
190 | #define BIT_READY_1 0x2 // [10] | |||
|
191 | #define BIT_READY_0_1 0x3 // [11] | |||
|
192 | #define BIT_STATUS_F1_0 0x04 // [0100] | |||
|
193 | #define BIT_STATUS_F1_1 0x08 // [1000] | |||
|
194 | #define BIT_STATUS_F2_0 0x10 // [0001 0000] | |||
|
195 | #define BIT_STATUS_F2_1 0x20 // [0010 0000] | |||
|
196 | #define DEFAULT_MATRIX_LENGTH 0xc8 // 25 * 128 / 16 = 200 = 0xc8 | |||
|
197 | #define BIT_IRQ_ON_NEW_MATRIX 0x01 | |||
|
198 | #define MASK_IRQ_ON_NEW_MATRIX 0xfffffffe | |||
|
199 | #define BIT_IRQ_ON_ERROR 0x02 | |||
|
200 | #define MASK_IRQ_ON_ERROR 0xfffffffd | |||
|
201 | ||||
109 | typedef struct { |
|
202 | typedef struct { | |
110 | volatile int config; // 0x00 |
|
203 | volatile int config; // 0x00 | |
111 | volatile int status; // 0x04 |
|
204 | volatile int status; // 0x04 |
@@ -29,4 +29,8 | |||||
29 |
|
29 | |||
30 | unsigned char lfr_rtems_cpu_usage_report( void ); |
|
30 | unsigned char lfr_rtems_cpu_usage_report( void ); | |
31 |
|
31 | |||
|
32 | #define CONST_100 100 | |||
|
33 | #define CONST_1000 1000 | |||
|
34 | #define CONST_100000 100000 | |||
|
35 | ||||
32 | #endif // LFR_CPU_USAGE_REPORT_H |
|
36 | #endif // LFR_CPU_USAGE_REPORT_H |
@@ -11,6 +11,10 | |||||
11 |
|
11 | |||
12 | #include "fsw_params.h" |
|
12 | #include "fsw_params.h" | |
13 |
|
13 | |||
|
14 | #define SBM_COEFF_PER_NORM_COEFF 2 | |||
|
15 | #define MAX_SRC_DATA 780 // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1] | |||
|
16 | #define MAX_SRC_DATA_WITH_SPARE 143 // 13 bins * 11 Bytes | |||
|
17 | ||||
14 | typedef struct ring_node_asm |
|
18 | typedef struct ring_node_asm | |
15 | { |
|
19 | { | |
16 | struct ring_node_asm *next; |
|
20 | struct ring_node_asm *next; | |
@@ -24,24 +28,24 typedef struct | |||||
24 | unsigned char protocolIdentifier; |
|
28 | unsigned char protocolIdentifier; | |
25 | unsigned char reserved; |
|
29 | unsigned char reserved; | |
26 | unsigned char userApplication; |
|
30 | unsigned char userApplication; | |
27 |
unsigned char packetID[ |
|
31 | unsigned char packetID[BYTES_PER_PACKETID]; | |
28 |
unsigned char packetSequenceControl[ |
|
32 | unsigned char packetSequenceControl[BYTES_PER_SEQ_CTRL]; | |
29 |
unsigned char packetLength[ |
|
33 | unsigned char packetLength[BYTES_PER_PKT_LEN]; | |
30 | // DATA FIELD HEADER |
|
34 | // DATA FIELD HEADER | |
31 | unsigned char spare1_pusVersion_spare2; |
|
35 | unsigned char spare1_pusVersion_spare2; | |
32 | unsigned char serviceType; |
|
36 | unsigned char serviceType; | |
33 | unsigned char serviceSubType; |
|
37 | unsigned char serviceSubType; | |
34 | unsigned char destinationID; |
|
38 | unsigned char destinationID; | |
35 |
unsigned char time[ |
|
39 | unsigned char time[BYTES_PER_TIME]; | |
36 | // AUXILIARY HEADER |
|
40 | // AUXILIARY HEADER | |
37 | unsigned char sid; |
|
41 | unsigned char sid; | |
38 | unsigned char pa_bia_status_info; |
|
42 | unsigned char pa_bia_status_info; | |
39 | unsigned char sy_lfr_common_parameters_spare; |
|
43 | unsigned char sy_lfr_common_parameters_spare; | |
40 | unsigned char sy_lfr_common_parameters; |
|
44 | unsigned char sy_lfr_common_parameters; | |
41 |
unsigned char acquisitionTime[ |
|
45 | unsigned char acquisitionTime[BYTES_PER_TIME]; | |
42 |
unsigned char pa_lfr_bp_blk_nr[ |
|
46 | unsigned char pa_lfr_bp_blk_nr[BYTES_PER_BLKNR]; | |
43 | // SOURCE DATA |
|
47 | // SOURCE DATA | |
44 |
unsigned char data[ |
|
48 | unsigned char data[ MAX_SRC_DATA ]; // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1] | |
45 | } bp_packet; |
|
49 | } bp_packet; | |
46 |
|
50 | |||
47 | typedef struct |
|
51 | typedef struct | |
@@ -50,25 +54,25 typedef struct | |||||
50 | unsigned char protocolIdentifier; |
|
54 | unsigned char protocolIdentifier; | |
51 | unsigned char reserved; |
|
55 | unsigned char reserved; | |
52 | unsigned char userApplication; |
|
56 | unsigned char userApplication; | |
53 |
unsigned char packetID[ |
|
57 | unsigned char packetID[BYTES_PER_PACKETID]; | |
54 |
unsigned char packetSequenceControl[ |
|
58 | unsigned char packetSequenceControl[BYTES_PER_SEQ_CTRL]; | |
55 |
unsigned char packetLength[ |
|
59 | unsigned char packetLength[BYTES_PER_PKT_LEN]; | |
56 | // DATA FIELD HEADER |
|
60 | // DATA FIELD HEADER | |
57 | unsigned char spare1_pusVersion_spare2; |
|
61 | unsigned char spare1_pusVersion_spare2; | |
58 | unsigned char serviceType; |
|
62 | unsigned char serviceType; | |
59 | unsigned char serviceSubType; |
|
63 | unsigned char serviceSubType; | |
60 | unsigned char destinationID; |
|
64 | unsigned char destinationID; | |
61 |
unsigned char time[ |
|
65 | unsigned char time[BYTES_PER_TIME]; | |
62 | // AUXILIARY HEADER |
|
66 | // AUXILIARY HEADER | |
63 | unsigned char sid; |
|
67 | unsigned char sid; | |
64 | unsigned char pa_bia_status_info; |
|
68 | unsigned char pa_bia_status_info; | |
65 | unsigned char sy_lfr_common_parameters_spare; |
|
69 | unsigned char sy_lfr_common_parameters_spare; | |
66 | unsigned char sy_lfr_common_parameters; |
|
70 | unsigned char sy_lfr_common_parameters; | |
67 |
unsigned char acquisitionTime[ |
|
71 | unsigned char acquisitionTime[BYTES_PER_TIME]; | |
68 | unsigned char source_data_spare; |
|
72 | unsigned char source_data_spare; | |
69 |
unsigned char pa_lfr_bp_blk_nr[ |
|
73 | unsigned char pa_lfr_bp_blk_nr[BYTES_PER_BLKNR]; | |
70 | // SOURCE DATA |
|
74 | // SOURCE DATA | |
71 |
unsigned char data[ |
|
75 | unsigned char data[ MAX_SRC_DATA_WITH_SPARE ]; // 13 bins * 11 Bytes | |
72 | } bp_packet_with_spare; // only for TM_LFR_SCIENCE_NORMAL_BP1_F0 and F1 |
|
76 | } bp_packet_with_spare; // only for TM_LFR_SCIENCE_NORMAL_BP1_F0 and F1 | |
73 |
|
77 | |||
74 | typedef struct asm_msg |
|
78 | typedef struct asm_msg | |
@@ -99,8 +103,8 extern Packet_TM_LFR_PARAMETER_DUMP_t pa | |||||
99 | extern time_management_regs_t *time_management_regs; |
|
103 | extern time_management_regs_t *time_management_regs; | |
100 | extern volatile spectral_matrix_regs_t *spectral_matrix_regs; |
|
104 | extern volatile spectral_matrix_regs_t *spectral_matrix_regs; | |
101 |
|
105 | |||
102 |
extern rtems_name misc_name[ |
|
106 | extern rtems_name misc_name[]; | |
103 |
extern rtems_id Task_id[ |
|
107 | extern rtems_id Task_id[]; /* array of task ids */ | |
104 |
|
108 | |||
105 | ring_node * getRingNodeForAveraging( unsigned char frequencyChannel); |
|
109 | ring_node * getRingNodeForAveraging( unsigned char frequencyChannel); | |
106 | // ISR |
|
110 | // ISR | |
@@ -173,7 +177,7 void SM_average( float *averaged_spec_ma | |||||
173 | float sum; |
|
177 | float sum; | |
174 | unsigned int i; |
|
178 | unsigned int i; | |
175 | unsigned int k; |
|
179 | unsigned int k; | |
176 |
unsigned char incomingSMIsValid[ |
|
180 | unsigned char incomingSMIsValid[NB_SM_BEFORE_AVF0_F1]; | |
177 | unsigned int numberOfValidSM; |
|
181 | unsigned int numberOfValidSM; | |
178 | unsigned char isValid; |
|
182 | unsigned char isValid; | |
179 |
|
183 | |||
@@ -181,7 +185,7 void SM_average( float *averaged_spec_ma | |||||
181 | // PAS FILTERING |
|
185 | // PAS FILTERING | |
182 | // check acquisitionTime of the incoming data |
|
186 | // check acquisitionTime of the incoming data | |
183 | numberOfValidSM = 0; |
|
187 | numberOfValidSM = 0; | |
184 |
for (k=0; k< |
|
188 | for (k=0; k<NB_SM_BEFORE_AVF0_F1; k++) | |
185 | { |
|
189 | { | |
186 | isValid = acquisitionTimeIsValid( ring_node_tab[k]->coarseTime, ring_node_tab[k]->fineTime, channel ); |
|
190 | isValid = acquisitionTimeIsValid( ring_node_tab[k]->coarseTime, ring_node_tab[k]->fineTime, channel ); | |
187 | incomingSMIsValid[k] = isValid; |
|
191 | incomingSMIsValid[k] = isValid; | |
@@ -201,14 +205,14 void SM_average( float *averaged_spec_ma | |||||
201 | // + ( (int *) (ring_node_tab[6]->buffer_address) ) [ i ] |
|
205 | // + ( (int *) (ring_node_tab[6]->buffer_address) ) [ i ] | |
202 | // + ( (int *) (ring_node_tab[7]->buffer_address) ) [ i ]; |
|
206 | // + ( (int *) (ring_node_tab[7]->buffer_address) ) [ i ]; | |
203 |
|
207 | |||
204 |
sum = ( |
|
208 | sum = ( incomingSMIsValid[0] * ((int *)(ring_node_tab[0]->buffer_address) )[ i ] ) | |
205 |
+ ( |
|
209 | + ( incomingSMIsValid[1] * ((int *)(ring_node_tab[1]->buffer_address) )[ i ] ) | |
206 |
+ ( |
|
210 | + ( incomingSMIsValid[2] * ((int *)(ring_node_tab[2]->buffer_address) )[ i ] ) | |
207 |
+ ( |
|
211 | + ( incomingSMIsValid[3] * ((int *)(ring_node_tab[3]->buffer_address) )[ i ] ) | |
208 |
+ ( |
|
212 | + ( incomingSMIsValid[4] * ((int *)(ring_node_tab[4]->buffer_address) )[ i ] ) | |
209 |
+ ( |
|
213 | + ( incomingSMIsValid[5] * ((int *)(ring_node_tab[5]->buffer_address) )[ i ] ) | |
210 |
+ ( |
|
214 | + ( incomingSMIsValid[6] * ((int *)(ring_node_tab[6]->buffer_address) )[ i ] ) | |
211 |
+ ( |
|
215 | + ( incomingSMIsValid[7] * ((int *)(ring_node_tab[7]->buffer_address) )[ i ] ); | |
212 |
|
216 | |||
213 | if ( (nbAverageNORM == 0) && (nbAverageSBM == 0) ) |
|
217 | if ( (nbAverageNORM == 0) && (nbAverageSBM == 0) ) | |
214 | { |
|
218 | { | |
@@ -278,13 +282,19 void ASM_reorganize_and_divide( float *a | |||||
278 | for( frequencyBin = 0; frequencyBin < NB_BINS_PER_SM; frequencyBin++ ) |
|
282 | for( frequencyBin = 0; frequencyBin < NB_BINS_PER_SM; frequencyBin++ ) | |
279 | { |
|
283 | { | |
280 | offsetASMReorganized = |
|
284 | offsetASMReorganized = | |
281 | frequencyBin * NB_VALUES_PER_SM |
|
285 | (frequencyBin * NB_VALUES_PER_SM) | |
282 | + asmComponent; |
|
286 | + asmComponent; | |
283 | offsetASM = |
|
287 | offsetASM = | |
284 | asmComponent * NB_BINS_PER_SM |
|
288 | (asmComponent * NB_BINS_PER_SM) | |
285 | + frequencyBin; |
|
289 | + frequencyBin; | |
286 | averaged_spec_mat_reorganized[offsetASMReorganized ] = |
|
290 | if ( divider != INIT_FLOAT ) | |
287 | (divider != 0.0) ? averaged_spec_mat[ offsetASM ] / divider : 0.0; |
|
291 | { | |
|
292 | averaged_spec_mat_reorganized[offsetASMReorganized ] = averaged_spec_mat[ offsetASM ] / divider; | |||
|
293 | } | |||
|
294 | else | |||
|
295 | { | |||
|
296 | averaged_spec_mat_reorganized[offsetASMReorganized ] = INIT_FLOAT; | |||
|
297 | } | |||
288 | } |
|
298 | } | |
289 | } |
|
299 | } | |
290 | } |
|
300 | } | |
@@ -304,12 +314,12 void ASM_compress_reorganize_and_divide( | |||||
304 | for( frequencyBin = 0; frequencyBin < nbBinsCompressedMatrix; frequencyBin++ ) |
|
314 | for( frequencyBin = 0; frequencyBin < nbBinsCompressedMatrix; frequencyBin++ ) | |
305 | { |
|
315 | { | |
306 | offsetCompressed = // NO TIME OFFSET |
|
316 | offsetCompressed = // NO TIME OFFSET | |
307 | frequencyBin * NB_VALUES_PER_SM |
|
317 | (frequencyBin * NB_VALUES_PER_SM) | |
308 | + asmComponent; |
|
318 | + asmComponent; | |
309 | offsetASM = // NO TIME OFFSET |
|
319 | offsetASM = // NO TIME OFFSET | |
310 | asmComponent * NB_BINS_PER_SM |
|
320 | (asmComponent * NB_BINS_PER_SM) | |
311 | + ASMIndexStart |
|
321 | + ASMIndexStart | |
312 | + frequencyBin * nbBinsToAverage; |
|
322 | + (frequencyBin * nbBinsToAverage); | |
313 | compressed_spec_mat[ offsetCompressed ] = 0; |
|
323 | compressed_spec_mat[ offsetCompressed ] = 0; | |
314 | for ( k = 0; k < nbBinsToAverage; k++ ) |
|
324 | for ( k = 0; k < nbBinsToAverage; k++ ) | |
315 | { |
|
325 | { | |
@@ -340,8 +350,8 void ASM_convert( volatile float *input_ | |||||
340 | { |
|
350 | { | |
341 | for ( asmComponent=0; asmComponent<NB_VALUES_PER_SM; asmComponent++) |
|
351 | for ( asmComponent=0; asmComponent<NB_VALUES_PER_SM; asmComponent++) | |
342 | { |
|
352 | { | |
343 | offsetInput = (frequencyBin*NB_VALUES_PER_SM) + asmComponent ; |
|
353 | offsetInput = (frequencyBin*NB_VALUES_PER_SM) + asmComponent ; | |
344 |
offsetOutput = |
|
354 | offsetOutput = SM_BYTES_PER_VAL * ( (frequencyBin*NB_VALUES_PER_SM) + asmComponent ) ; | |
345 | pt_char_input = (char*) &input_matrix [ offsetInput ]; |
|
355 | pt_char_input = (char*) &input_matrix [ offsetInput ]; | |
346 | pt_char_output = (char*) &output_matrix[ offsetOutput ]; |
|
356 | pt_char_output = (char*) &output_matrix[ offsetOutput ]; | |
347 | pt_char_output[0] = pt_char_input[0]; // bits 31 downto 24 of the float |
|
357 | pt_char_output[0] = pt_char_input[0]; // bits 31 downto 24 of the float |
@@ -1,9 +1,28 | |||||
1 | #ifndef TC_ACCEPTANCE_H_INCLUDED |
|
1 | #ifndef TC_ACCEPTANCE_H_INCLUDED | |
2 | #define TC_ACCEPTANCE_H_INCLUDED |
|
2 | #define TC_ACCEPTANCE_H_INCLUDED | |
3 |
|
3 | |||
4 | //#include "tm_lfr_tc_exe.h" |
|
|||
5 | #include "fsw_params.h" |
|
4 | #include "fsw_params.h" | |
6 |
|
5 | |||
|
6 | #define BIT_0 0x01 | |||
|
7 | #define BIT_1 0x02 | |||
|
8 | #define BIT_2 0x04 | |||
|
9 | #define BIT_3 0x08 | |||
|
10 | #define BIT_4 0x10 | |||
|
11 | #define BIT_5 0x20 | |||
|
12 | #define BIT_6 0x40 | |||
|
13 | #define BIT_7 0x80 | |||
|
14 | ||||
|
15 | #define CONST_CRC_0 0x1021 | |||
|
16 | #define CONST_CRC_1 0x2042 | |||
|
17 | #define CONST_CRC_2 0x4084 | |||
|
18 | #define CONST_CRC_3 0x8108 | |||
|
19 | #define CONST_CRC_4 0x1231 | |||
|
20 | #define CONST_CRC_5 0x2462 | |||
|
21 | #define CONST_CRC_6 0x48c4 | |||
|
22 | #define CONST_CRC_7 0x9188 | |||
|
23 | ||||
|
24 | #define CRC_RESET 0xffff | |||
|
25 | ||||
7 | //********************** |
|
26 | //********************** | |
8 | // GENERAL USE FUNCTIONS |
|
27 | // GENERAL USE FUNCTIONS | |
9 | unsigned int Crc_opt( unsigned char D, unsigned int Chk); |
|
28 | unsigned int Crc_opt( unsigned char D, unsigned int Chk); |
@@ -12,6 +12,36 | |||||
12 |
|
12 | |||
13 | #include "lfr_cpu_usage_report.h" |
|
13 | #include "lfr_cpu_usage_report.h" | |
14 |
|
14 | |||
|
15 | #define MAX_DELTA_COARSE_TIME 3 | |||
|
16 | #define NB_SCIENCE_TASKS 10 | |||
|
17 | #define NB_ASM_TASKS 6 | |||
|
18 | #define STATUS_0 0 | |||
|
19 | #define STATUS_1 1 | |||
|
20 | #define STATUS_2 2 | |||
|
21 | #define STATUS_3 3 | |||
|
22 | #define STATUS_4 4 | |||
|
23 | #define STATUS_5 5 | |||
|
24 | #define STATUS_6 6 | |||
|
25 | #define STATUS_7 7 | |||
|
26 | #define STATUS_8 8 | |||
|
27 | #define STATUS_9 9 | |||
|
28 | ||||
|
29 | #define CAL_F0 625 | |||
|
30 | #define CAL_F1 10000 | |||
|
31 | #define CAL_FS 160256.410 | |||
|
32 | #define CAL_SCALE_FACTOR (0.250 / 0.000654) // 191, 500 mVpp, 2 sinus waves => 500 mVpp each, amplitude = 250 mV | |||
|
33 | #define CAL_NB_PTS 256 | |||
|
34 | #define CAL_DATA_MASK 0xfff | |||
|
35 | #define CAL_F_DIVISOR 38 // 25 MHz => 160 256 (39 - 1) | |||
|
36 | // INTERLEAVED MODE | |||
|
37 | #define CAL_FS_INTER 240384.615 | |||
|
38 | #define CAL_NB_PTS_INTER 384 | |||
|
39 | #define CAL_DATA_MASK_INTER 0x3f | |||
|
40 | #define CAL_DATA_SHIFT_INTER 12 | |||
|
41 | #define BYTES_FOR_2_SAMPLES 3 // one need 3 bytes = 24 bits to store 3 samples of 12 bits in interleaved mode | |||
|
42 | #define STEPS_FOR_STORAGE_INTER 128 | |||
|
43 | #define CAL_F_DIVISOR_INTER 26 // 25 MHz => 240 384 | |||
|
44 | ||||
15 | extern unsigned int lastValidEnterModeTime; |
|
45 | extern unsigned int lastValidEnterModeTime; | |
16 | extern unsigned char oneTcLfrUpdateTimeReceived; |
|
46 | extern unsigned char oneTcLfrUpdateTimeReceived; | |
17 |
|
47 |
@@ -11,7 +11,25 | |||||
11 | #include "basic_parameters_params.h" |
|
11 | #include "basic_parameters_params.h" | |
12 | #include "avf0_prc0.h" |
|
12 | #include "avf0_prc0.h" | |
13 |
|
13 | |||
14 | #define FLOAT_EQUAL_ZERO 0.001 |
|
14 | #define FLOAT_EQUAL_ZERO 0.001 | |
|
15 | #define NB_BINS_TO_REMOVE 3 | |||
|
16 | #define FI_INTERVAL_COEFF 0.285 | |||
|
17 | #define BIN_MIN 0 | |||
|
18 | #define BIN_MAX 127 | |||
|
19 | #define DELTAF_F0 96. | |||
|
20 | #define DELTAF_F1 16. | |||
|
21 | #define DELTAF_F2 1. | |||
|
22 | ||||
|
23 | #define BIT_RW1_F1 0x80 | |||
|
24 | #define BIT_RW1_F2 0x40 | |||
|
25 | #define BIT_RW2_F1 0x20 | |||
|
26 | #define BIT_RW2_F2 0x10 | |||
|
27 | #define BIT_RW3_F1 0x08 | |||
|
28 | #define BIT_RW3_F2 0x04 | |||
|
29 | #define BIT_RW4_F1 0x02 | |||
|
30 | #define BIT_RW4_F2 0x01 | |||
|
31 | ||||
|
32 | #define SBM_KCOEFF_PER_NORM_KCOEFF 2 | |||
15 |
|
33 | |||
16 | extern unsigned short sequenceCounterParameterDump; |
|
34 | extern unsigned short sequenceCounterParameterDump; | |
17 | extern unsigned short sequenceCounters_TM_DUMP[]; |
|
35 | extern unsigned short sequenceCounters_TM_DUMP[]; |
@@ -11,6 +11,33 | |||||
11 | #include "fsw_params_wf_handler.h" |
|
11 | #include "fsw_params_wf_handler.h" | |
12 |
|
12 | |||
13 | #define pi 3.14159265359 |
|
13 | #define pi 3.14159265359 | |
|
14 | #define T0_IN_FINETIME ( 65536. / 24576. ) | |||
|
15 | #define T1_IN_FINETIME ( 65536. / 4096. ) | |||
|
16 | #define T2_IN_FINETIME ( 65536. / 256. ) | |||
|
17 | #define T3_IN_FINETIME ( 65536. / 16. ) | |||
|
18 | ||||
|
19 | #define TICKS_PER_T1 16 | |||
|
20 | #define TICKS_PER_T2 256 | |||
|
21 | #define TICKS_PER_S 65536. | |||
|
22 | #define MS_PER_S 1000. | |||
|
23 | ||||
|
24 | #define FREQ_F0 24576. | |||
|
25 | #define FREQ_F1 4096. | |||
|
26 | #define FREQ_F2 256. | |||
|
27 | #define FREQ_F3 16. | |||
|
28 | ||||
|
29 | #define DELTAT_F0 2731 // (2048. / 24576. / 2.) * 65536. = 2730.667; | |||
|
30 | #define DELTAT_F1 16384 // (2048. / 4096. / 2.) * 65536. = 16384; | |||
|
31 | #define DELTAT_F2 262144 // (2048. / 256. / 2.) * 65536. = 262144; | |||
|
32 | ||||
|
33 | #define OFFSET_2_BYTES 2 | |||
|
34 | ||||
|
35 | #define ONE_TICK_CORR_INTERVAL_0_MIN 0.5 | |||
|
36 | #define ONE_TICK_CORR_INTERVAL_0_MAX 1.0 | |||
|
37 | #define ONE_TICK_CORR_INTERVAL_1_MIN -1.0 | |||
|
38 | #define ONE_TICK_CORR_INTERVAL_1_MAX -0.5 | |||
|
39 | #define ONE_TICK_CORR 1 | |||
|
40 | #define CORR_MULT 2 | |||
14 |
|
41 | |||
15 | extern int fdSPW; |
|
42 | extern int fdSPW; | |
16 |
|
43 | |||
@@ -30,7 +57,7 extern struct param_local_str param_loca | |||||
30 | extern unsigned short sequenceCounters_SCIENCE_NORMAL_BURST; |
|
57 | extern unsigned short sequenceCounters_SCIENCE_NORMAL_BURST; | |
31 | extern unsigned short sequenceCounters_SCIENCE_SBM1_SBM2; |
|
58 | extern unsigned short sequenceCounters_SCIENCE_SBM1_SBM2; | |
32 |
|
59 | |||
33 |
extern rtems_id Task_id[ |
|
60 | extern rtems_id Task_id[]; /* array of task ids */ | |
34 |
|
61 | |||
35 | extern unsigned char lfrCurrentMode; |
|
62 | extern unsigned char lfrCurrentMode; | |
36 |
|
63 |
@@ -1,15 +1,16 | |||||
1 | #include <drvmgr/ambapp_bus.h> |
|
1 | #include <drvmgr/ambapp_bus.h> | |
2 | #include <drvmgr/drvmgr.h> |
|
2 | #include <drvmgr/drvmgr.h> | |
|
3 | #include <ccsds_types.h> | |||
3 |
|
4 | |||
4 | // GRSPW0 resources |
|
5 | // GRSPW0 resources | |
5 | struct drvmgr_key grlib_grspw_0n1_res[] = |
|
6 | struct drvmgr_key grlib_grspw_0n1_res[] = | |
6 | { |
|
7 | { | |
7 |
|
|
8 | {"txBdCnt", KEY_TYPE_INT, {(unsigned int)TXBDCNT}}, // 7 SWF_F0, 7 SWF_F1, 7 SWF_F2, 7 CWF_F3, 7 CWF_F1 ou 7 CWF_F2 | |
8 |
|
|
9 | {"rxBdCnt", KEY_TYPE_INT, {(unsigned int)RXBDCNT}}, | |
9 |
|
|
10 | {"txDataSize", KEY_TYPE_INT, {(unsigned int)TXDATASIZE}}, | |
10 |
|
|
11 | {"txHdrSize", KEY_TYPE_INT, {(unsigned int)TXHDRSIZE}}, | |
11 |
|
|
12 | {"rxPktSize", KEY_TYPE_INT, {(unsigned int)RXPKTSIZE}}, | |
12 |
|
|
13 | KEY_EMPTY | |
13 | }; |
|
14 | }; | |
14 |
|
15 | |||
15 | // If RTEMS_DRVMGR_STARTUP is defined we override the "weak defaults" that is defined by the LEON3 BSP. |
|
16 | // If RTEMS_DRVMGR_STARTUP is defined we override the "weak defaults" that is defined by the LEON3 BSP. |
@@ -22,10 +22,13 | |||||
22 | #include "fsw_params.h" |
|
22 | #include "fsw_params.h" | |
23 | #include "fsw_params_wf_handler.h" |
|
23 | #include "fsw_params_wf_handler.h" | |
24 |
|
24 | |||
|
25 | #define NB_OF_TASKS 20 | |||
|
26 | #define NB_OF_MISC_NAMES 5 | |||
|
27 | ||||
25 | // RTEMS GLOBAL VARIABLES |
|
28 | // RTEMS GLOBAL VARIABLES | |
26 |
rtems_name misc_name[ |
|
29 | rtems_name misc_name[NB_OF_MISC_NAMES]; | |
27 |
rtems_name Task_name[ |
|
30 | rtems_name Task_name[NB_OF_TASKS]; /* array of task names */ | |
28 |
rtems_id Task_id[ |
|
31 | rtems_id Task_id[NB_OF_TASKS]; /* array of task ids */ | |
29 | rtems_name timecode_timer_name; |
|
32 | rtems_name timecode_timer_name; | |
30 | rtems_id timecode_timer_id; |
|
33 | rtems_id timecode_timer_id; | |
31 | int fdSPW = 0; |
|
34 | int fdSPW = 0; | |
@@ -95,4 +98,5 float cp_rpw_sc_rw4_f2; | |||||
95 | filterPar_t filterPar; |
|
98 | filterPar_t filterPar; | |
96 |
|
99 | |||
97 | fbins_masks_t fbins_masks; |
|
100 | fbins_masks_t fbins_masks; | |
98 |
unsigned int acquisitionDurations[ |
|
101 | unsigned int acquisitionDurations[NB_ACQUISITION_DURATION] | |
|
102 | = {ACQUISITION_DURATION_F0, ACQUISITION_DURATION_F1, ACQUISITION_DURATION_F2}; |
@@ -164,16 +164,16 rtems_task Init( rtems_task_argument ign | |||||
164 | init_k_coefficients_prc0(); |
|
164 | init_k_coefficients_prc0(); | |
165 | init_k_coefficients_prc1(); |
|
165 | init_k_coefficients_prc1(); | |
166 | init_k_coefficients_prc2(); |
|
166 | init_k_coefficients_prc2(); | |
167 |
pa_bia_status_info = |
|
167 | pa_bia_status_info = INIT_CHAR; | |
168 |
cp_rpw_sc_rw_f_flags = |
|
168 | cp_rpw_sc_rw_f_flags = INIT_CHAR; | |
169 |
cp_rpw_sc_rw1_f1 = |
|
169 | cp_rpw_sc_rw1_f1 = INIT_FLOAT; | |
170 |
cp_rpw_sc_rw1_f2 = |
|
170 | cp_rpw_sc_rw1_f2 = INIT_FLOAT; | |
171 |
cp_rpw_sc_rw2_f1 = |
|
171 | cp_rpw_sc_rw2_f1 = INIT_FLOAT; | |
172 |
cp_rpw_sc_rw2_f2 = |
|
172 | cp_rpw_sc_rw2_f2 = INIT_FLOAT; | |
173 |
cp_rpw_sc_rw3_f1 = |
|
173 | cp_rpw_sc_rw3_f1 = INIT_FLOAT; | |
174 |
cp_rpw_sc_rw3_f2 = |
|
174 | cp_rpw_sc_rw3_f2 = INIT_FLOAT; | |
175 |
cp_rpw_sc_rw4_f1 = |
|
175 | cp_rpw_sc_rw4_f1 = INIT_FLOAT; | |
176 |
cp_rpw_sc_rw4_f2 = |
|
176 | cp_rpw_sc_rw4_f2 = INIT_FLOAT; | |
177 | // initialize filtering parameters |
|
177 | // initialize filtering parameters | |
178 | filterPar.spare_sy_lfr_pas_filter_enabled = DEFAULT_SY_LFR_PAS_FILTER_ENABLED; |
|
178 | filterPar.spare_sy_lfr_pas_filter_enabled = DEFAULT_SY_LFR_PAS_FILTER_ENABLED; | |
179 | filterPar.sy_lfr_pas_filter_modulus = DEFAULT_SY_LFR_PAS_FILTER_MODULUS; |
|
179 | filterPar.sy_lfr_pas_filter_modulus = DEFAULT_SY_LFR_PAS_FILTER_MODULUS; | |
@@ -319,17 +319,17 void init_local_mode_parameters( void ) | |||||
319 |
|
319 | |||
320 | for(i = 0; i<SEQ_CNT_NB_DEST_ID; i++) |
|
320 | for(i = 0; i<SEQ_CNT_NB_DEST_ID; i++) | |
321 | { |
|
321 | { | |
322 |
sequenceCounters_TC_EXE[i] = |
|
322 | sequenceCounters_TC_EXE[i] = INIT_CHAR; | |
323 |
sequenceCounters_TM_DUMP[i] = |
|
323 | sequenceCounters_TM_DUMP[i] = INIT_CHAR; | |
324 | } |
|
324 | } | |
325 |
sequenceCounters_SCIENCE_NORMAL_BURST = |
|
325 | sequenceCounters_SCIENCE_NORMAL_BURST = INIT_CHAR; | |
326 |
sequenceCounters_SCIENCE_SBM1_SBM2 = |
|
326 | sequenceCounters_SCIENCE_SBM1_SBM2 = INIT_CHAR; | |
327 |
sequenceCounterHK = TM_PACKET_SEQ_CTRL_STANDALONE << |
|
327 | sequenceCounterHK = TM_PACKET_SEQ_CTRL_STANDALONE << TM_PACKET_SEQ_SHIFT; | |
328 | } |
|
328 | } | |
329 |
|
329 | |||
330 | void reset_local_time( void ) |
|
330 | void reset_local_time( void ) | |
331 | { |
|
331 | { | |
332 |
time_management_regs->ctrl = time_management_regs->ctrl | |
|
332 | time_management_regs->ctrl = time_management_regs->ctrl | VAL_SOFTWARE_RESET; // [0010] software reset, coarse time = 0x80000000 | |
333 | } |
|
333 | } | |
334 |
|
334 | |||
335 | void create_names( void ) // create all names for tasks and queues |
|
335 | void create_names( void ) // create all names for tasks and queues | |
@@ -403,7 +403,7 int create_all_tasks( void ) // create a | |||||
403 | if (status == RTEMS_SUCCESSFUL) // SEND |
|
403 | if (status == RTEMS_SUCCESSFUL) // SEND | |
404 | { |
|
404 | { | |
405 | status = rtems_task_create( |
|
405 | status = rtems_task_create( | |
406 |
Task_name[TASKID_SEND], TASK_PRIORITY_SEND, RTEMS_MINIMUM_STACK_SIZE * |
|
406 | Task_name[TASKID_SEND], TASK_PRIORITY_SEND, RTEMS_MINIMUM_STACK_SIZE * STACK_SIZE_MULT, | |
407 | RTEMS_DEFAULT_MODES, |
|
407 | RTEMS_DEFAULT_MODES, | |
408 | RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_SEND] |
|
408 | RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_SEND] | |
409 | ); |
|
409 | ); | |
@@ -446,7 +446,7 int create_all_tasks( void ) // create a | |||||
446 | if (status == RTEMS_SUCCESSFUL) // PRC0 |
|
446 | if (status == RTEMS_SUCCESSFUL) // PRC0 | |
447 | { |
|
447 | { | |
448 | status = rtems_task_create( |
|
448 | status = rtems_task_create( | |
449 |
Task_name[TASKID_PRC0], TASK_PRIORITY_PRC0, RTEMS_MINIMUM_STACK_SIZE * |
|
449 | Task_name[TASKID_PRC0], TASK_PRIORITY_PRC0, RTEMS_MINIMUM_STACK_SIZE * STACK_SIZE_MULT, | |
450 | RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT, |
|
450 | RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT, | |
451 | RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC0] |
|
451 | RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC0] | |
452 | ); |
|
452 | ); | |
@@ -462,7 +462,7 int create_all_tasks( void ) // create a | |||||
462 | if (status == RTEMS_SUCCESSFUL) // PRC1 |
|
462 | if (status == RTEMS_SUCCESSFUL) // PRC1 | |
463 | { |
|
463 | { | |
464 | status = rtems_task_create( |
|
464 | status = rtems_task_create( | |
465 |
Task_name[TASKID_PRC1], TASK_PRIORITY_PRC1, RTEMS_MINIMUM_STACK_SIZE * |
|
465 | Task_name[TASKID_PRC1], TASK_PRIORITY_PRC1, RTEMS_MINIMUM_STACK_SIZE * STACK_SIZE_MULT, | |
466 | RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT, |
|
466 | RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT, | |
467 | RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC1] |
|
467 | RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC1] | |
468 | ); |
|
468 | ); | |
@@ -478,7 +478,7 int create_all_tasks( void ) // create a | |||||
478 | if (status == RTEMS_SUCCESSFUL) // PRC2 |
|
478 | if (status == RTEMS_SUCCESSFUL) // PRC2 | |
479 | { |
|
479 | { | |
480 | status = rtems_task_create( |
|
480 | status = rtems_task_create( | |
481 |
Task_name[TASKID_PRC2], TASK_PRIORITY_PRC2, RTEMS_MINIMUM_STACK_SIZE * |
|
481 | Task_name[TASKID_PRC2], TASK_PRIORITY_PRC2, RTEMS_MINIMUM_STACK_SIZE * STACK_SIZE_MULT, | |
482 | RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT, |
|
482 | RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT, | |
483 | RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC2] |
|
483 | RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC2] | |
484 | ); |
|
484 | ); | |
@@ -913,10 +913,10 void init_ring(ring_node ring[], unsigne | |||||
913 | // BUFFER ADDRESS |
|
913 | // BUFFER ADDRESS | |
914 | for(i=0; i<nbNodes; i++) |
|
914 | for(i=0; i<nbNodes; i++) | |
915 | { |
|
915 | { | |
916 |
ring[i].coarseTime = |
|
916 | ring[i].coarseTime = INT32_ALL_F; | |
917 |
ring[i].fineTime = |
|
917 | ring[i].fineTime = INT32_ALL_F; | |
918 |
ring[i].sid = |
|
918 | ring[i].sid = INIT_CHAR; | |
919 |
ring[i].status = |
|
919 | ring[i].status = INIT_CHAR; | |
920 | ring[i].buffer_address = (int) &buffer[ i * bufferSize ]; |
|
920 | ring[i].buffer_address = (int) &buffer[ i * bufferSize ]; | |
921 | } |
|
921 | } | |
922 |
|
922 |
@@ -25,7 +25,7 void timer_configure(unsigned char timer | |||||
25 | rtems_status_code status; |
|
25 | rtems_status_code status; | |
26 | rtems_isr_entry old_isr_handler; |
|
26 | rtems_isr_entry old_isr_handler; | |
27 |
|
27 | |||
28 |
gptimer_regs->timer[timer].ctrl = |
|
28 | gptimer_regs->timer[timer].ctrl = INIT_CHAR; // reset the control register | |
29 |
|
29 | |||
30 | status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels |
|
30 | status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels | |
31 | if (status!=RTEMS_SUCCESSFUL) |
|
31 | if (status!=RTEMS_SUCCESSFUL) | |
@@ -45,11 +45,11 void timer_start(unsigned char timer) | |||||
45 | * |
|
45 | * | |
46 | */ |
|
46 | */ | |
47 |
|
47 | |||
48 |
gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | |
|
48 | gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ; | |
49 |
gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | |
|
49 | gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_LD; | |
50 |
gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | |
|
50 | gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_EN; | |
51 |
gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | |
|
51 | gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_RS; | |
52 |
gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | |
|
52 | gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_IE; | |
53 | } |
|
53 | } | |
54 |
|
54 | |||
55 | void timer_stop(unsigned char timer) |
|
55 | void timer_stop(unsigned char timer) | |
@@ -61,9 +61,9 void timer_stop(unsigned char timer) | |||||
61 | * |
|
61 | * | |
62 | */ |
|
62 | */ | |
63 |
|
63 | |||
64 |
gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & |
|
64 | gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_EN_MASK; | |
65 |
gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & |
|
65 | gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_IE_MASK; | |
66 |
gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | |
|
66 | gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ; | |
67 | } |
|
67 | } | |
68 |
|
68 | |||
69 | void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider) |
|
69 | void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider) | |
@@ -127,7 +127,7 void watchdog_reload(void) | |||||
127 | * |
|
127 | * | |
128 | */ |
|
128 | */ | |
129 |
|
129 | |||
130 |
gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | |
|
130 | gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD; | |
131 | } |
|
131 | } | |
132 |
|
132 | |||
133 | void watchdog_start(void) |
|
133 | void watchdog_start(void) | |
@@ -141,10 +141,10 void watchdog_start(void) | |||||
141 |
|
141 | |||
142 | LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); |
|
142 | LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); | |
143 |
|
143 | |||
144 |
gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | |
|
144 | gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_CLEAR_IRQ; | |
145 |
gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | |
|
145 | gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD; | |
146 |
gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | |
|
146 | gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_EN; | |
147 |
gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | |
|
147 | gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_IE; | |
148 |
|
148 | |||
149 | LEON_Unmask_interrupt( IRQ_GPTIMER_WATCHDOG ); |
|
149 | LEON_Unmask_interrupt( IRQ_GPTIMER_WATCHDOG ); | |
150 |
|
150 | |||
@@ -210,14 +210,14 rtems_task load_task(rtems_task_argument | |||||
210 | status = rtems_rate_monotonic_period( watchdog_period_id, WATCHDOG_PERIOD ); |
|
210 | status = rtems_rate_monotonic_period( watchdog_period_id, WATCHDOG_PERIOD ); | |
211 | watchdog_reload(); |
|
211 | watchdog_reload(); | |
212 | i = i + 1; |
|
212 | i = i + 1; | |
213 |
if ( i == |
|
213 | if ( i == WATCHDOG_LOOP_PRINTF ) | |
214 | { |
|
214 | { | |
215 | i = 0; |
|
215 | i = 0; | |
216 | j = j + 1; |
|
216 | j = j + 1; | |
217 | PRINTF1("%d\n", j) |
|
217 | PRINTF1("%d\n", j) | |
218 | } |
|
218 | } | |
219 | #ifdef DEBUG_WATCHDOG |
|
219 | #ifdef DEBUG_WATCHDOG | |
220 |
if (j == |
|
220 | if (j == WATCHDOG_LOOP_DEBUG ) | |
221 | { |
|
221 | { | |
222 | status = rtems_task_delete(RTEMS_SELF); |
|
222 | status = rtems_task_delete(RTEMS_SELF); | |
223 |