##// END OF EJS Templates
AVGV modified...
paul -
r352:c07c16776bd4 R3++ draft
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@@ -1,2 +1,2
1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
2 e01ac8bd125a79a7af38b0e3ba0330f5be1a3c92 header/lfr_common_headers
2 7ee7da2ed42fbc9cd673ae7f3a865345cea0f83f header/lfr_common_headers
@@ -1,238 +1,235
1 #ifndef GRLIB_REGS_H_INCLUDED
1 #ifndef GRLIB_REGS_H_INCLUDED
2 #define GRLIB_REGS_H_INCLUDED
2 #define GRLIB_REGS_H_INCLUDED
3
3
4 #define NB_GPTIMER 3
4 #define NB_GPTIMER 3
5
5
6 #include <stdint.h>
6 #include <stdint.h>
7
7
8 struct apbuart_regs_str{
8 struct apbuart_regs_str{
9 volatile unsigned int data;
9 volatile unsigned int data;
10 volatile unsigned int status;
10 volatile unsigned int status;
11 volatile unsigned int ctrl;
11 volatile unsigned int ctrl;
12 volatile unsigned int scaler;
12 volatile unsigned int scaler;
13 volatile unsigned int fifoDebug;
13 volatile unsigned int fifoDebug;
14 };
14 };
15
15
16 struct grgpio_regs_str{
16 struct grgpio_regs_str{
17 volatile int io_port_data_register;
17 volatile int io_port_data_register;
18 int io_port_output_register;
18 int io_port_output_register;
19 int io_port_direction_register;
19 int io_port_direction_register;
20 int interrupt_mak_register;
20 int interrupt_mak_register;
21 int interrupt_polarity_register;
21 int interrupt_polarity_register;
22 int interrupt_edge_register;
22 int interrupt_edge_register;
23 int bypass_register;
23 int bypass_register;
24 int reserved;
24 int reserved;
25 // 0x20-0x3c interrupt map register(s)
25 // 0x20-0x3c interrupt map register(s)
26 };
26 };
27
27
28 typedef struct {
28 typedef struct {
29 volatile unsigned int counter;
29 volatile unsigned int counter;
30 volatile unsigned int reload;
30 volatile unsigned int reload;
31 volatile unsigned int ctrl;
31 volatile unsigned int ctrl;
32 volatile unsigned int unused;
32 volatile unsigned int unused;
33 } timer_regs_t;
33 } timer_regs_t;
34
34
35 //*************
35 //*************
36 //*************
36 //*************
37 // GPTIMER_REGS
37 // GPTIMER_REGS
38
38
39 #define GPTIMER_CLEAR_IRQ 0x00000010 // clear pending IRQ if any
39 #define GPTIMER_CLEAR_IRQ 0x00000010 // clear pending IRQ if any
40 #define GPTIMER_LD 0x00000004 // LD load value from the reload register
40 #define GPTIMER_LD 0x00000004 // LD load value from the reload register
41 #define GPTIMER_EN 0x00000001 // EN enable the timer
41 #define GPTIMER_EN 0x00000001 // EN enable the timer
42 #define GPTIMER_EN_MASK 0xfffffffe // EN enable the timer
42 #define GPTIMER_EN_MASK 0xfffffffe // EN enable the timer
43 #define GPTIMER_RS 0x00000002 // RS restart
43 #define GPTIMER_RS 0x00000002 // RS restart
44 #define GPTIMER_IE 0x00000008 // IE interrupt enable
44 #define GPTIMER_IE 0x00000008 // IE interrupt enable
45 #define GPTIMER_IE_MASK 0xffffffef // IE interrupt enable
45 #define GPTIMER_IE_MASK 0xffffffef // IE interrupt enable
46
46
47 typedef struct {
47 typedef struct {
48 volatile unsigned int scaler_value;
48 volatile unsigned int scaler_value;
49 volatile unsigned int scaler_reload;
49 volatile unsigned int scaler_reload;
50 volatile unsigned int conf;
50 volatile unsigned int conf;
51 volatile unsigned int unused0;
51 volatile unsigned int unused0;
52 timer_regs_t timer[NB_GPTIMER];
52 timer_regs_t timer[NB_GPTIMER];
53 } gptimer_regs_t;
53 } gptimer_regs_t;
54
54
55 //*********************
55 //*********************
56 //*********************
56 //*********************
57 // TIME_MANAGEMENT_REGS
57 // TIME_MANAGEMENT_REGS
58
58
59 #define VAL_SOFTWARE_RESET 0x02 // [0010] software reset
59 #define VAL_SOFTWARE_RESET 0x02 // [0010] software reset
60 #define VAL_LFR_SYNCHRONIZED 0x80000000
60 #define VAL_LFR_SYNCHRONIZED 0x80000000
61 #define BIT_SYNCHRONIZATION 31
61 #define BIT_SYNCHRONIZATION 31
62 #define COARSE_TIME_MASK 0x7fffffff
62 #define COARSE_TIME_MASK 0x7fffffff
63 #define SYNC_BIT_MASK 0x7f
63 #define SYNC_BIT_MASK 0x7f
64 #define SYNC_BIT 0x80
64 #define SYNC_BIT 0x80
65 #define BIT_CAL_RELOAD 0x00000010
65 #define BIT_CAL_RELOAD 0x00000010
66 #define MASK_CAL_RELOAD 0xffffffef // [1110 1111]
66 #define MASK_CAL_RELOAD 0xffffffef // [1110 1111]
67 #define BIT_CAL_ENABLE 0x00000040
67 #define BIT_CAL_ENABLE 0x00000040
68 #define MASK_CAL_ENABLE 0xffffffbf // [1011 1111]
68 #define MASK_CAL_ENABLE 0xffffffbf // [1011 1111]
69 #define BIT_SET_INTERLEAVED 0x00000020 // [0010 0000]
69 #define BIT_SET_INTERLEAVED 0x00000020 // [0010 0000]
70 #define MASK_SET_INTERLEAVED 0xffffffdf // [1101 1111]
70 #define MASK_SET_INTERLEAVED 0xffffffdf // [1101 1111]
71 #define BIT_SOFT_RESET 0x00000004 // [0100]
71 #define BIT_SOFT_RESET 0x00000004 // [0100]
72 #define MASK_SOFT_RESET 0xfffffffb // [1011]
72 #define MASK_SOFT_RESET 0xfffffffb // [1011]
73
73
74 typedef struct {
74 typedef struct {
75 volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time
75 volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time
76 // bit 1 is the soft reset for the time management module
76 // bit 1 is the soft reset for the time management module
77 // bit 2 is the soft reset for the waveform picker and the spectral matrix modules, set to 1 after HW reset
77 // bit 2 is the soft reset for the waveform picker and the spectral matrix modules, set to 1 after HW reset
78 volatile int coarse_time_load;
78 volatile int coarse_time_load;
79 volatile int coarse_time;
79 volatile int coarse_time;
80 volatile int fine_time;
80 volatile int fine_time;
81 // TEMPERATURES
81 // TEMPERATURES
82 volatile int temp_pcb; // SEL1 = 0 SEL0 = 0
82 volatile int temp_pcb; // SEL1 = 0 SEL0 = 0
83 volatile int temp_fpga; // SEL1 = 0 SEL0 = 1
83 volatile int temp_fpga; // SEL1 = 0 SEL0 = 1
84 volatile int temp_scm; // SEL1 = 1 SEL0 = 0
84 volatile int temp_scm; // SEL1 = 1 SEL0 = 0
85 // CALIBRATION
85 // CALIBRATION
86 volatile unsigned int calDACCtrl;
86 volatile unsigned int calDACCtrl;
87 volatile unsigned int calPrescaler;
87 volatile unsigned int calPrescaler;
88 volatile unsigned int calDivisor;
88 volatile unsigned int calDivisor;
89 volatile unsigned int calDataPtr;
89 volatile unsigned int calDataPtr;
90 volatile unsigned int calData;
90 volatile unsigned int calData;
91 } time_management_regs_t;
91 } time_management_regs_t;
92
92
93 //*********************
93 //*********************
94 //*********************
94 //*********************
95 // WAVEFORM_PICKER_REGS
95 // WAVEFORM_PICKER_REGS
96
96
97 #define BITS_WFP_STATUS_F3 0xc0 // [1100 0000] check the f3 full bits
97 #define BITS_WFP_STATUS_F3 0xc0 // [1100 0000] check the f3 full bits
98 #define BIT_WFP_BUF_F3_0 0x40 // [0100 0000] f3 buffer 0 is full
98 #define BIT_WFP_BUF_F3_0 0x40 // [0100 0000] f3 buffer 0 is full
99 #define BIT_WFP_BUF_F3_1 0x80 // [1000 0000] f3 buffer 1 is full
99 #define BIT_WFP_BUF_F3_1 0x80 // [1000 0000] f3 buffer 1 is full
100 #define RST_WFP_F3_0 0x00008840 // [1000 1000 0100 0000]
100 #define RST_WFP_F3_0 0x00008840 // [1000 1000 0100 0000]
101 #define RST_WFP_F3_1 0x00008880 // [1000 1000 1000 0000]
101 #define RST_WFP_F3_1 0x00008880 // [1000 1000 1000 0000]
102
102
103 #define BITS_WFP_STATUS_F2 0x30 // [0011 0000] get the status bits for f2
103 #define BITS_WFP_STATUS_F2 0x30 // [0011 0000] get the status bits for f2
104 #define SHIFT_WFP_STATUS_F2 4
104 #define SHIFT_WFP_STATUS_F2 4
105 #define BIT_WFP_BUF_F2_0 0x10 // [0001 0000] f2 buffer 0 is full
105 #define BIT_WFP_BUF_F2_0 0x10 // [0001 0000] f2 buffer 0 is full
106 #define BIT_WFP_BUF_F2_1 0x20 // [0010 0000] f2 buffer 1 is full
106 #define BIT_WFP_BUF_F2_1 0x20 // [0010 0000] f2 buffer 1 is full
107 #define RST_WFP_F2_0 0x00004410 // [0100 0100 0001 0000]
107 #define RST_WFP_F2_0 0x00004410 // [0100 0100 0001 0000]
108 #define RST_WFP_F2_1 0x00004420 // [0100 0100 0010 0000]
108 #define RST_WFP_F2_1 0x00004420 // [0100 0100 0010 0000]
109
109
110 #define BITS_WFP_STATUS_F1 0x0c // [0000 1100] check the f1 full bits
110 #define BITS_WFP_STATUS_F1 0x0c // [0000 1100] check the f1 full bits
111 #define BIT_WFP_BUF_F1_0 0x04 // [0000 0100] f1 buffer 0 is full
111 #define BIT_WFP_BUF_F1_0 0x04 // [0000 0100] f1 buffer 0 is full
112 #define BIT_WFP_BUF_F1_1 0x08 // [0000 1000] f1 buffer 1 is full
112 #define BIT_WFP_BUF_F1_1 0x08 // [0000 1000] f1 buffer 1 is full
113 #define RST_WFP_F1_0 0x00002204 // [0010 0010 0000 0100] f1 bits = 0
113 #define RST_WFP_F1_0 0x00002204 // [0010 0010 0000 0100] f1 bits = 0
114 #define RST_WFP_F1_1 0x00002208 // [0010 0010 0000 1000] f1 bits = 0
114 #define RST_WFP_F1_1 0x00002208 // [0010 0010 0000 1000] f1 bits = 0
115
115
116 #define BITS_WFP_STATUS_F0 0x03 // [0000 0011] check the f0 full bits
116 #define BITS_WFP_STATUS_F0 0x03 // [0000 0011] check the f0 full bits
117 #define RST_WFP_F0_0 0x00001101 // [0001 0001 0000 0001]
117 #define RST_WFP_F0_0 0x00001101 // [0001 0001 0000 0001]
118 #define RST_WFP_F0_1 0x00001102 // [0001 0001 0000 0010]
118 #define RST_WFP_F0_1 0x00001102 // [0001 0001 0000 0010]
119
119
120 #define BIT_WFP_BUFFER_0 0x01
120 #define BIT_WFP_BUFFER_0 0x01
121 #define BIT_WFP_BUFFER_1 0x02
121 #define BIT_WFP_BUFFER_1 0x02
122
122
123 #define RST_BITS_RUN_BURST_EN 0x80 // [1000 0000] burst f2, f1, f0 enable f3, f2, f1, f0
123 #define RST_BITS_RUN_BURST_EN 0x80 // [1000 0000] burst f2, f1, f0 enable f3, f2, f1, f0
124 #define BITS_WFP_ENABLE_ALL 0x0f // [0000 1111] enable f3, f2, f1, f0
124 #define BITS_WFP_ENABLE_ALL 0x0f // [0000 1111] enable f3, f2, f1, f0
125 #define BITS_WFP_ENABLE_BURST 0x0c // [0000 1100] enable f3, f2
125 #define BITS_WFP_ENABLE_BURST 0x0c // [0000 1100] enable f3, f2
126 #define RUN_BURST_ENABLE_SBM2 0x60 // [0110 0000] enable f2 and f1 burst
126 #define RUN_BURST_ENABLE_SBM2 0x60 // [0110 0000] enable f2 and f1 burst
127 #define RUN_BURST_ENABLE_BURST 0x40 // [0100 0000] f2 burst enabled
127 #define RUN_BURST_ENABLE_BURST 0x40 // [0100 0000] f2 burst enabled
128
128
129 #define DFLT_WFP_NB_DATA_BY_BUFFER 0xa7f // 0x30 *** 2688 - 1 => nb samples -1
129 #define DFLT_WFP_NB_DATA_BY_BUFFER 0xa7f // 0x30 *** 2688 - 1 => nb samples -1
130 #define DFLT_WFP_SNAPSHOT_PARAM 0xa80 // 0x34 *** 2688 => nb samples
130 #define DFLT_WFP_SNAPSHOT_PARAM 0xa80 // 0x34 *** 2688 => nb samples
131 #define DFLT_WFP_BUFFER_LENGTH 0x1f8 // buffer length in burst = 3 * 2688 / 16 = 504 = 0x1f8
131 #define DFLT_WFP_BUFFER_LENGTH 0x1f8 // buffer length in burst = 3 * 2688 / 16 = 504 = 0x1f8
132 #define DFLT_WFP_DELTA_F0_2 0x30 // 48 = 11 0000, max 7 bits
132 #define DFLT_WFP_DELTA_F0_2 0x30 // 48 = 11 0000, max 7 bits
133
133
134 // PDB >= 0.1.28, 0x80000f54
134 // PDB >= 0.1.28, 0x80000f54
135 typedef struct{
135 typedef struct{
136 int data_shaping; // 0x00 00 *** R2 R1 R0 SP1 SP0 BW
136 int data_shaping; // 0x00 00 *** R2 R1 R0 SP1 SP0 BW
137 int run_burst_enable; // 0x04 01 *** [run *** burst f2, f1, f0 *** enable f3, f2, f1, f0 ]
137 int run_burst_enable; // 0x04 01 *** [run *** burst f2, f1, f0 *** enable f3, f2, f1, f0 ]
138 int addr_data_f0_0; // 0x08
138 int addr_data_f0_0; // 0x08
139 int addr_data_f0_1; // 0x0c
139 int addr_data_f0_1; // 0x0c
140 int addr_data_f1_0; // 0x10
140 int addr_data_f1_0; // 0x10
141 int addr_data_f1_1; // 0x14
141 int addr_data_f1_1; // 0x14
142 int addr_data_f2_0; // 0x18
142 int addr_data_f2_0; // 0x18
143 int addr_data_f2_1; // 0x1c
143 int addr_data_f2_1; // 0x1c
144 int addr_data_f3_0; // 0x20
144 int addr_data_f3_0; // 0x20
145 int addr_data_f3_1; // 0x24
145 int addr_data_f3_1; // 0x24
146 volatile int status; // 0x28
146 volatile int status; // 0x28
147 volatile int delta_snapshot; // 0x2c
147 volatile int delta_snapshot; // 0x2c
148 int delta_f0; // 0x30
148 int delta_f0; // 0x30
149 int delta_f0_2; // 0x34
149 int delta_f0_2; // 0x34
150 int delta_f1; // 0x38
150 int delta_f1; // 0x38
151 int delta_f2; // 0x3c
151 int delta_f2; // 0x3c
152 int nb_data_by_buffer; // 0x40 number of samples in a buffer = 2688
152 int nb_data_by_buffer; // 0x40 number of samples in a buffer = 2688
153 int snapshot_param; // 0x44
153 int snapshot_param; // 0x44
154 int start_date; // 0x48
154 int start_date; // 0x48
155 //
155 //
156 volatile unsigned int f0_0_coarse_time; // 0x4c
156 volatile unsigned int f0_0_coarse_time; // 0x4c
157 volatile unsigned int f0_0_fine_time; // 0x50
157 volatile unsigned int f0_0_fine_time; // 0x50
158 volatile unsigned int f0_1_coarse_time; // 0x54
158 volatile unsigned int f0_1_coarse_time; // 0x54
159 volatile unsigned int f0_1_fine_time; // 0x58
159 volatile unsigned int f0_1_fine_time; // 0x58
160 //
160 //
161 volatile unsigned int f1_0_coarse_time; // 0x5c
161 volatile unsigned int f1_0_coarse_time; // 0x5c
162 volatile unsigned int f1_0_fine_time; // 0x60
162 volatile unsigned int f1_0_fine_time; // 0x60
163 volatile unsigned int f1_1_coarse_time; // 0x64
163 volatile unsigned int f1_1_coarse_time; // 0x64
164 volatile unsigned int f1_1_fine_time; // 0x68
164 volatile unsigned int f1_1_fine_time; // 0x68
165 //
165 //
166 volatile unsigned int f2_0_coarse_time; // 0x6c
166 volatile unsigned int f2_0_coarse_time; // 0x6c
167 volatile unsigned int f2_0_fine_time; // 0x70
167 volatile unsigned int f2_0_fine_time; // 0x70
168 volatile unsigned int f2_1_coarse_time; // 0x74
168 volatile unsigned int f2_1_coarse_time; // 0x74
169 volatile unsigned int f2_1_fine_time; // 0x78
169 volatile unsigned int f2_1_fine_time; // 0x78
170 //
170 //
171 volatile unsigned int f3_0_coarse_time; // 0x7c => 0x7c + 0xf54 = 0xd0
171 volatile unsigned int f3_0_coarse_time; // 0x7c => 0x7c + 0xf54 = 0xd0
172 volatile unsigned int f3_0_fine_time; // 0x80
172 volatile unsigned int f3_0_fine_time; // 0x80
173 volatile unsigned int f3_1_coarse_time; // 0x84
173 volatile unsigned int f3_1_coarse_time; // 0x84
174 volatile unsigned int f3_1_fine_time; // 0x88
174 volatile unsigned int f3_1_fine_time; // 0x88
175 //
175 //
176 unsigned int buffer_length; // 0x8c = buffer length in burst 2688 / 16 = 168
176 unsigned int buffer_length; // 0x8c = buffer length in burst 2688 / 16 = 168
177 //
177 //
178 volatile int16_t v_dummy; // 0x90
178 volatile int v; // 0x90
179 volatile int16_t v; // 0x90
179 volatile int e1; // 0x94
180 volatile int16_t e1_dummy; // 0x94
180 volatile int e2; // 0x98
181 volatile int16_t e1; // 0x94
182 volatile int16_t e2_dummy; // 0x98
183 volatile int16_t e2; // 0x98
184 } waveform_picker_regs_0_1_18_t;
181 } waveform_picker_regs_0_1_18_t;
185
182
186 //*********************
183 //*********************
187 //*********************
184 //*********************
188 // SPECTRAL_MATRIX_REGS
185 // SPECTRAL_MATRIX_REGS
189
186
190 #define BITS_STATUS_F0 0x03 // [0011]
187 #define BITS_STATUS_F0 0x03 // [0011]
191 #define BITS_STATUS_F1 0x0c // [1100]
188 #define BITS_STATUS_F1 0x0c // [1100]
192 #define BITS_STATUS_F2 0x30 // [0011 0000]
189 #define BITS_STATUS_F2 0x30 // [0011 0000]
193 #define BITS_HK_AA_SM 0x780 // [0111 1000 0000]
190 #define BITS_HK_AA_SM 0x780 // [0111 1000 0000]
194 #define BITS_SM_ERR 0x7c0 // [0111 1100 0000]
191 #define BITS_SM_ERR 0x7c0 // [0111 1100 0000]
195 #define BITS_STATUS_REG 0x7ff // [0111 1111 1111]
192 #define BITS_STATUS_REG 0x7ff // [0111 1111 1111]
196 #define BIT_READY_0 0x1 // [01]
193 #define BIT_READY_0 0x1 // [01]
197 #define BIT_READY_1 0x2 // [10]
194 #define BIT_READY_1 0x2 // [10]
198 #define BIT_READY_0_1 0x3 // [11]
195 #define BIT_READY_0_1 0x3 // [11]
199 #define BIT_STATUS_F1_0 0x04 // [0100]
196 #define BIT_STATUS_F1_0 0x04 // [0100]
200 #define BIT_STATUS_F1_1 0x08 // [1000]
197 #define BIT_STATUS_F1_1 0x08 // [1000]
201 #define BIT_STATUS_F2_0 0x10 // [0001 0000]
198 #define BIT_STATUS_F2_0 0x10 // [0001 0000]
202 #define BIT_STATUS_F2_1 0x20 // [0010 0000]
199 #define BIT_STATUS_F2_1 0x20 // [0010 0000]
203 #define DEFAULT_MATRIX_LENGTH 0xc8 // 25 * 128 / 16 = 200 = 0xc8
200 #define DEFAULT_MATRIX_LENGTH 0xc8 // 25 * 128 / 16 = 200 = 0xc8
204 #define BIT_IRQ_ON_NEW_MATRIX 0x01
201 #define BIT_IRQ_ON_NEW_MATRIX 0x01
205 #define MASK_IRQ_ON_NEW_MATRIX 0xfffffffe
202 #define MASK_IRQ_ON_NEW_MATRIX 0xfffffffe
206 #define BIT_IRQ_ON_ERROR 0x02
203 #define BIT_IRQ_ON_ERROR 0x02
207 #define MASK_IRQ_ON_ERROR 0xfffffffd
204 #define MASK_IRQ_ON_ERROR 0xfffffffd
208
205
209 typedef struct {
206 typedef struct {
210 volatile int config; // 0x00
207 volatile int config; // 0x00
211 volatile int status; // 0x04
208 volatile int status; // 0x04
212 volatile int f0_0_address; // 0x08
209 volatile int f0_0_address; // 0x08
213 volatile int f0_1_address; // 0x0C
210 volatile int f0_1_address; // 0x0C
214 //
211 //
215 volatile int f1_0_address; // 0x10
212 volatile int f1_0_address; // 0x10
216 volatile int f1_1_address; // 0x14
213 volatile int f1_1_address; // 0x14
217 volatile int f2_0_address; // 0x18
214 volatile int f2_0_address; // 0x18
218 volatile int f2_1_address; // 0x1C
215 volatile int f2_1_address; // 0x1C
219 //
216 //
220 volatile unsigned int f0_0_coarse_time; // 0x20
217 volatile unsigned int f0_0_coarse_time; // 0x20
221 volatile unsigned int f0_0_fine_time; // 0x24
218 volatile unsigned int f0_0_fine_time; // 0x24
222 volatile unsigned int f0_1_coarse_time; // 0x28
219 volatile unsigned int f0_1_coarse_time; // 0x28
223 volatile unsigned int f0_1_fine_time; // 0x2C
220 volatile unsigned int f0_1_fine_time; // 0x2C
224 //
221 //
225 volatile unsigned int f1_0_coarse_time; // 0x30
222 volatile unsigned int f1_0_coarse_time; // 0x30
226 volatile unsigned int f1_0_fine_time; // 0x34
223 volatile unsigned int f1_0_fine_time; // 0x34
227 volatile unsigned int f1_1_coarse_time; // 0x38
224 volatile unsigned int f1_1_coarse_time; // 0x38
228 volatile unsigned int f1_1_fine_time; // 0x3C
225 volatile unsigned int f1_1_fine_time; // 0x3C
229 //
226 //
230 volatile unsigned int f2_0_coarse_time; // 0x40
227 volatile unsigned int f2_0_coarse_time; // 0x40
231 volatile unsigned int f2_0_fine_time; // 0x44
228 volatile unsigned int f2_0_fine_time; // 0x44
232 volatile unsigned int f2_1_coarse_time; // 0x48
229 volatile unsigned int f2_1_coarse_time; // 0x48
233 volatile unsigned int f2_1_fine_time; // 0x4C
230 volatile unsigned int f2_1_fine_time; // 0x4C
234 //
231 //
235 unsigned int matrix_length; // 0x50, length of a spectral matrix in burst 3200 / 16 = 200 = 0xc8
232 unsigned int matrix_length; // 0x50, length of a spectral matrix in burst 3200 / 16 = 200 = 0xc8
236 } spectral_matrix_regs_t;
233 } spectral_matrix_regs_t;
237
234
238 #endif // GRLIB_REGS_H_INCLUDED
235 #endif // GRLIB_REGS_H_INCLUDED
@@ -1,122 +1,124
1 #ifndef TC_LOAD_DUMP_PARAMETERS_H
1 #ifndef TC_LOAD_DUMP_PARAMETERS_H
2 #define TC_LOAD_DUMP_PARAMETERS_H
2 #define TC_LOAD_DUMP_PARAMETERS_H
3
3
4 #include <rtems.h>
4 #include <rtems.h>
5 #include <stdio.h>
5 #include <stdio.h>
6
6
7 #include "fsw_params.h"
7 #include "fsw_params.h"
8 #include "wf_handler.h"
8 #include "wf_handler.h"
9 #include "tm_lfr_tc_exe.h"
9 #include "tm_lfr_tc_exe.h"
10 #include "fsw_misc.h"
10 #include "fsw_misc.h"
11 #include "basic_parameters_params.h"
11 #include "basic_parameters_params.h"
12 #include "avf0_prc0.h"
12 #include "avf0_prc0.h"
13
13
14 #define FLOAT_EQUAL_ZERO 0.001
14 #define FLOAT_EQUAL_ZERO 0.001
15 #define NB_BINS_TO_REMOVE 3
15 #define NB_BINS_TO_REMOVE 3
16 #define FI_INTERVAL_COEFF 0.285
16 #define FI_INTERVAL_COEFF 0.285
17 #define BIN_MIN 0
17 #define BIN_MIN 0
18 #define BIN_MAX 127
18 #define BIN_MAX 127
19 #define DELTAF_F0 96.
19 #define DELTAF_F0 96.
20 #define DELTAF_F1 16.
20 #define DELTAF_F1 16.
21 #define DELTAF_F2 1.
21 #define DELTAF_F2 1.
22 #define DELTAF_DIV 2.
22 #define DELTAF_DIV 2.
23
23
24 #define BIT_RW1_F1 0x80
24 #define BIT_RW1_F1 0x80
25 #define BIT_RW1_F2 0x40
25 #define BIT_RW1_F2 0x40
26 #define BIT_RW2_F1 0x20
26 #define BIT_RW2_F1 0x20
27 #define BIT_RW2_F2 0x10
27 #define BIT_RW2_F2 0x10
28 #define BIT_RW3_F1 0x08
28 #define BIT_RW3_F1 0x08
29 #define BIT_RW3_F2 0x04
29 #define BIT_RW3_F2 0x04
30 #define BIT_RW4_F1 0x02
30 #define BIT_RW4_F1 0x02
31 #define BIT_RW4_F2 0x01
31 #define BIT_RW4_F2 0x01
32
32
33 #define WHEEL_1 1
33 #define WHEEL_1 1
34 #define WHEEL_2 2
34 #define WHEEL_2 2
35 #define WHEEL_3 3
35 #define WHEEL_3 3
36 #define WHEEL_4 4
36 #define WHEEL_4 4
37 #define FREQ_1 1
37 #define FREQ_1 1
38 #define FREQ_2 2
38 #define FREQ_2 2
39 #define FREQ_3 3
39 #define FREQ_3 3
40 #define FREQ_4 4
40 #define FREQ_4 4
41 #define FLAG_OFFSET_WHEELS_1_3 8
41 #define FLAG_OFFSET_WHEELS_1_3 8
42 #define FLAG_OFFSET_WHEELS_2_4 4
42 #define FLAG_OFFSET_WHEELS_2_4 4
43
43
44 #define FLAG_NAN 0 // Not A NUMBER
44 #define FLAG_NAN 0 // Not A NUMBER
45 #define FLAG_IAN 1 // Is A Number
45 #define FLAG_IAN 1 // Is A Number
46
46
47 #define SBM_KCOEFF_PER_NORM_KCOEFF 2
47 #define SBM_KCOEFF_PER_NORM_KCOEFF 2
48
48
49 extern unsigned short sequenceCounterParameterDump;
49 extern unsigned short sequenceCounterParameterDump;
50 extern unsigned short sequenceCounters_TM_DUMP[];
50 extern unsigned short sequenceCounters_TM_DUMP[];
51 extern float k_coeff_intercalib_f0_norm[ ];
51 extern float k_coeff_intercalib_f0_norm[ ];
52 extern float k_coeff_intercalib_f0_sbm[ ];
52 extern float k_coeff_intercalib_f0_sbm[ ];
53 extern float k_coeff_intercalib_f1_norm[ ];
53 extern float k_coeff_intercalib_f1_norm[ ];
54 extern float k_coeff_intercalib_f1_sbm[ ];
54 extern float k_coeff_intercalib_f1_sbm[ ];
55 extern float k_coeff_intercalib_f2[ ];
55 extern float k_coeff_intercalib_f2[ ];
56 extern fbins_masks_t fbins_masks;
56 extern fbins_masks_t fbins_masks;
57
57
58 int action_load_common_par( ccsdsTelecommandPacket_t *TC );
58 int action_load_common_par( ccsdsTelecommandPacket_t *TC );
59 int action_load_normal_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
59 int action_load_normal_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
60 int action_load_burst_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
60 int action_load_burst_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
61 int action_load_sbm1_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
61 int action_load_sbm1_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
62 int action_load_sbm2_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
62 int action_load_sbm2_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
63 int action_load_kcoefficients(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
63 int action_load_kcoefficients(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
64 int action_load_fbins_mask(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
64 int action_load_fbins_mask(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
65 int action_load_filter_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
65 int action_load_filter_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
66 int action_dump_kcoefficients(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
66 int action_dump_kcoefficients(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
67 int action_dump_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id );
67 int action_dump_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id );
68
68
69 // NORMAL
69 // NORMAL
70 int check_normal_par_consistency( ccsdsTelecommandPacket_t *TC, rtems_id queue_id );
70 int check_normal_par_consistency( ccsdsTelecommandPacket_t *TC, rtems_id queue_id );
71 int set_sy_lfr_n_swf_l( ccsdsTelecommandPacket_t *TC );
71 int set_sy_lfr_n_swf_l( ccsdsTelecommandPacket_t *TC );
72 int set_sy_lfr_n_swf_p( ccsdsTelecommandPacket_t *TC );
72 int set_sy_lfr_n_swf_p( ccsdsTelecommandPacket_t *TC );
73 int set_sy_lfr_n_asm_p( ccsdsTelecommandPacket_t *TC );
73 int set_sy_lfr_n_asm_p( ccsdsTelecommandPacket_t *TC );
74 int set_sy_lfr_n_bp_p0( ccsdsTelecommandPacket_t *TC );
74 int set_sy_lfr_n_bp_p0( ccsdsTelecommandPacket_t *TC );
75 int set_sy_lfr_n_bp_p1( ccsdsTelecommandPacket_t *TC );
75 int set_sy_lfr_n_bp_p1( ccsdsTelecommandPacket_t *TC );
76 int set_sy_lfr_n_cwf_long_f3( ccsdsTelecommandPacket_t *TC );
76 int set_sy_lfr_n_cwf_long_f3( ccsdsTelecommandPacket_t *TC );
77
77
78 // BURST
78 // BURST
79 int set_sy_lfr_b_bp_p0( ccsdsTelecommandPacket_t *TC );
79 int set_sy_lfr_b_bp_p0( ccsdsTelecommandPacket_t *TC );
80 int set_sy_lfr_b_bp_p1( ccsdsTelecommandPacket_t *TC );
80 int set_sy_lfr_b_bp_p1( ccsdsTelecommandPacket_t *TC );
81
81
82 // SBM1
82 // SBM1
83 int set_sy_lfr_s1_bp_p0( ccsdsTelecommandPacket_t *TC );
83 int set_sy_lfr_s1_bp_p0( ccsdsTelecommandPacket_t *TC );
84 int set_sy_lfr_s1_bp_p1( ccsdsTelecommandPacket_t *TC );
84 int set_sy_lfr_s1_bp_p1( ccsdsTelecommandPacket_t *TC );
85
85
86 // SBM2
86 // SBM2
87 int set_sy_lfr_s2_bp_p0( ccsdsTelecommandPacket_t *TC );
87 int set_sy_lfr_s2_bp_p0( ccsdsTelecommandPacket_t *TC );
88 int set_sy_lfr_s2_bp_p1( ccsdsTelecommandPacket_t *TC );
88 int set_sy_lfr_s2_bp_p1( ccsdsTelecommandPacket_t *TC );
89
89
90 // TC_LFR_UPDATE_INFO
90 // TC_LFR_UPDATE_INFO
91 unsigned int check_update_info_hk_lfr_mode( unsigned char mode );
91 unsigned int check_update_info_hk_lfr_mode( unsigned char mode );
92 unsigned int check_update_info_hk_tds_mode( unsigned char mode );
92 unsigned int check_update_info_hk_tds_mode( unsigned char mode );
93 unsigned int check_update_info_hk_thr_mode( unsigned char mode );
93 unsigned int check_update_info_hk_thr_mode( unsigned char mode );
94 void set_hk_lfr_sc_rw_f_flag( unsigned char wheel, unsigned char freq, float value );
94 void set_hk_lfr_sc_rw_f_flag( unsigned char wheel, unsigned char freq, float value );
95 void set_hk_lfr_sc_rw_f_flags( void );
95 void set_hk_lfr_sc_rw_f_flags( void );
96 int check_sy_lfr_rw_f( ccsdsTelecommandPacket_t *TC, int offset, int* pos, float* value );
97 int check_all_sy_lfr_rw_f( ccsdsTelecommandPacket_t *TC, int *pos, float*value );
96 void getReactionWheelsFrequencies( ccsdsTelecommandPacket_t *TC );
98 void getReactionWheelsFrequencies( ccsdsTelecommandPacket_t *TC );
97 void setFBinMask(unsigned char *fbins_mask, float rw_f, unsigned char deltaFreq, float sy_lfr_rw_k );
99 void setFBinMask(unsigned char *fbins_mask, float rw_f, unsigned char deltaFreq, float sy_lfr_rw_k );
98 void build_sy_lfr_rw_mask( unsigned int channel );
100 void build_sy_lfr_rw_mask( unsigned int channel );
99 void build_sy_lfr_rw_masks();
101 void build_sy_lfr_rw_masks();
100 void merge_fbins_masks( void );
102 void merge_fbins_masks( void );
101
103
102 // FBINS_MASK
104 // FBINS_MASK
103 int set_sy_lfr_fbins( ccsdsTelecommandPacket_t *TC );
105 int set_sy_lfr_fbins( ccsdsTelecommandPacket_t *TC );
104
106
105 // TC_LFR_LOAD_PARS_FILTER_PAR
107 // TC_LFR_LOAD_PARS_FILTER_PAR
106 int check_sy_lfr_rw_k( ccsdsTelecommandPacket_t *TC, int offset, int* pos, float* value );
108 int check_sy_lfr_rw_k( ccsdsTelecommandPacket_t *TC, int offset, int* pos, float* value );
107 int check_all_sy_lfr_rw_k( ccsdsTelecommandPacket_t *TC, int *pos, float*value );
109 int check_all_sy_lfr_rw_k( ccsdsTelecommandPacket_t *TC, int *pos, float*value );
108 int check_sy_lfr_filter_parameters( ccsdsTelecommandPacket_t *TC, rtems_id queue_id );
110 int check_sy_lfr_filter_parameters( ccsdsTelecommandPacket_t *TC, rtems_id queue_id );
109
111
110 // KCOEFFICIENTS
112 // KCOEFFICIENTS
111 int set_sy_lfr_kcoeff(ccsdsTelecommandPacket_t *TC , rtems_id queue_id);
113 int set_sy_lfr_kcoeff(ccsdsTelecommandPacket_t *TC , rtems_id queue_id);
112 void copyFloatByChar( unsigned char *destination, unsigned char *source );
114 void copyFloatByChar( unsigned char *destination, unsigned char *source );
113 void copyInt32ByChar( unsigned char *destination, unsigned char *source );
115 void copyInt32ByChar( unsigned char *destination, unsigned char *source );
114 void copyInt16ByChar( unsigned char *destination, unsigned char *source );
116 void copyInt16ByChar( unsigned char *destination, unsigned char *source );
115 void floatToChar( float value, unsigned char* ptr);
117 void floatToChar( float value, unsigned char* ptr);
116
118
117 void init_parameter_dump( void );
119 void init_parameter_dump( void );
118 void init_kcoefficients_dump( void );
120 void init_kcoefficients_dump( void );
119 void init_kcoefficients_dump_packet( Packet_TM_LFR_KCOEFFICIENTS_DUMP_t *kcoefficients_dump, unsigned char pkt_nr, unsigned char blk_nr );
121 void init_kcoefficients_dump_packet( Packet_TM_LFR_KCOEFFICIENTS_DUMP_t *kcoefficients_dump, unsigned char pkt_nr, unsigned char blk_nr );
120 void increment_seq_counter_destination_id_dump( unsigned char *packet_sequence_control, unsigned char destination_id );
122 void increment_seq_counter_destination_id_dump( unsigned char *packet_sequence_control, unsigned char destination_id );
121
123
122 #endif // TC_LOAD_DUMP_PARAMETERS_H
124 #endif // TC_LOAD_DUMP_PARAMETERS_H
@@ -1,98 +1,98
1 /** Global variables of the LFR flight software.
1 /** Global variables of the LFR flight software.
2 *
2 *
3 * @file
3 * @file
4 * @author P. LEROY
4 * @author P. LEROY
5 *
5 *
6 * Among global variables, there are:
6 * Among global variables, there are:
7 * - RTEMS names and id.
7 * - RTEMS names and id.
8 * - APB configuration registers.
8 * - APB configuration registers.
9 * - waveforms global buffers, used by the waveform picker hardware module to store data.
9 * - waveforms global buffers, used by the waveform picker hardware module to store data.
10 * - spectral matrices buffesr, used by the hardware module to store data.
10 * - spectral matrices buffesr, used by the hardware module to store data.
11 * - variable related to LFR modes parameters.
11 * - variable related to LFR modes parameters.
12 * - the global HK packet buffer.
12 * - the global HK packet buffer.
13 * - the global dump parameter buffer.
13 * - the global dump parameter buffer.
14 *
14 *
15 */
15 */
16
16
17 #include <rtems.h>
17 #include <rtems.h>
18 #include <grspw.h>
18 #include <grspw.h>
19
19
20 #include "ccsds_types.h"
20 #include "ccsds_types.h"
21 #include "grlib_regs.h"
21 #include "grlib_regs.h"
22 #include "fsw_params.h"
22 #include "fsw_params.h"
23 #include "fsw_params_wf_handler.h"
23 #include "fsw_params_wf_handler.h"
24
24
25 #define NB_OF_TASKS 20
25 #define NB_OF_TASKS 20
26 #define NB_OF_MISC_NAMES 5
26 #define NB_OF_MISC_NAMES 5
27
27
28 // RTEMS GLOBAL VARIABLES
28 // RTEMS GLOBAL VARIABLES
29 rtems_name misc_name[NB_OF_MISC_NAMES] = {0};
29 rtems_name misc_name[NB_OF_MISC_NAMES] = {0};
30 rtems_name Task_name[NB_OF_TASKS] = {0}; /* array of task names */
30 rtems_name Task_name[NB_OF_TASKS] = {0}; /* array of task names */
31 rtems_id Task_id[NB_OF_TASKS] = {0}; /* array of task ids */
31 rtems_id Task_id[NB_OF_TASKS] = {0}; /* array of task ids */
32 rtems_name timecode_timer_name = 0;
32 rtems_name timecode_timer_name = 0;
33 rtems_id timecode_timer_id = RTEMS_ID_NONE;
33 rtems_id timecode_timer_id = RTEMS_ID_NONE;
34 rtems_name name_hk_rate_monotonic = 0; // name of the HK rate monotonic
34 rtems_name name_hk_rate_monotonic = 0; // name of the HK rate monotonic
35 rtems_id HK_id = RTEMS_ID_NONE;// id of the HK rate monotonic period
35 rtems_id HK_id = RTEMS_ID_NONE;// id of the HK rate monotonic period
36 rtems_name name_avgv_rate_monotonic = 0; // name of the AVGV rate monotonic
36 rtems_name name_avgv_rate_monotonic = 0; // name of the AVGV rate monotonic
37 rtems_id AVGV_id = RTEMS_ID_NONE;// id of the AVGV rate monotonic period
37 rtems_id AVGV_id = RTEMS_ID_NONE;// id of the AVGV rate monotonic period
38 int fdSPW = 0;
38 int fdSPW = 0;
39 int fdUART = 0;
39 int fdUART = 0;
40 unsigned char lfrCurrentMode = 0;
40 unsigned char lfrCurrentMode = 0;
41 unsigned char pa_bia_status_info = 0;
41 unsigned char pa_bia_status_info = 0;
42 unsigned char thisIsAnASMRestart = 0;
42 unsigned char thisIsAnASMRestart = 0;
43 unsigned char oneTcLfrUpdateTimeReceived = 0;
43 unsigned char oneTcLfrUpdateTimeReceived = 0;
44
44
45 // WAVEFORMS GLOBAL VARIABLES // 2048 * 3 * 4 + 2 * 4 = 24576 + 8 bytes = 24584
45 // WAVEFORMS GLOBAL VARIABLES // 2048 * 3 * 4 + 2 * 4 = 24576 + 8 bytes = 24584
46 // 97 * 256 = 24832 => delta = 248 bytes = 62 words
46 // 97 * 256 = 24832 => delta = 248 bytes = 62 words
47 // WAVEFORMS GLOBAL VARIABLES // 2688 * 3 * 4 + 2 * 4 = 32256 + 8 bytes = 32264
47 // WAVEFORMS GLOBAL VARIABLES // 2688 * 3 * 4 + 2 * 4 = 32256 + 8 bytes = 32264
48 // 127 * 256 = 32512 => delta = 248 bytes = 62 words
48 // 127 * 256 = 32512 => delta = 248 bytes = 62 words
49 // F0 F1 F2 F3
49 // F0 F1 F2 F3
50 volatile int wf_buffer_f0[ NB_RING_NODES_F0 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
50 volatile int wf_buffer_f0[ NB_RING_NODES_F0 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
51 volatile int wf_buffer_f1[ NB_RING_NODES_F1 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
51 volatile int wf_buffer_f1[ NB_RING_NODES_F1 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
52 volatile int wf_buffer_f2[ NB_RING_NODES_F2 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
52 volatile int wf_buffer_f2[ NB_RING_NODES_F2 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
53 volatile int wf_buffer_f3[ NB_RING_NODES_F3 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
53 volatile int wf_buffer_f3[ NB_RING_NODES_F3 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
54
54
55 //***********************************
55 //***********************************
56 // SPECTRAL MATRICES GLOBAL VARIABLES
56 // SPECTRAL MATRICES GLOBAL VARIABLES
57
57
58 // alignment constraints for the spectral matrices buffers => the first data after the time (8 bytes) shall be aligned on 0x00
58 // alignment constraints for the spectral matrices buffers => the first data after the time (8 bytes) shall be aligned on 0x00
59 volatile int sm_f0[ NB_RING_NODES_SM_F0 * TOTAL_SIZE_SM ] __attribute__((aligned(0x100))) = {0};
59 volatile int sm_f0[ NB_RING_NODES_SM_F0 * TOTAL_SIZE_SM ] __attribute__((aligned(0x100))) = {0};
60 volatile int sm_f1[ NB_RING_NODES_SM_F1 * TOTAL_SIZE_SM ] __attribute__((aligned(0x100))) = {0};
60 volatile int sm_f1[ NB_RING_NODES_SM_F1 * TOTAL_SIZE_SM ] __attribute__((aligned(0x100))) = {0};
61 volatile int sm_f2[ NB_RING_NODES_SM_F2 * TOTAL_SIZE_SM ] __attribute__((aligned(0x100))) = {0};
61 volatile int sm_f2[ NB_RING_NODES_SM_F2 * TOTAL_SIZE_SM ] __attribute__((aligned(0x100))) = {0};
62
62
63 // APB CONFIGURATION REGISTERS
63 // APB CONFIGURATION REGISTERS
64 time_management_regs_t *time_management_regs = (time_management_regs_t*) REGS_ADDR_TIME_MANAGEMENT;
64 time_management_regs_t *time_management_regs = (time_management_regs_t*) REGS_ADDR_TIME_MANAGEMENT;
65 gptimer_regs_t *gptimer_regs = (gptimer_regs_t *) REGS_ADDR_GPTIMER;
65 gptimer_regs_t *gptimer_regs = (gptimer_regs_t *) REGS_ADDR_GPTIMER;
66 waveform_picker_regs_0_1_18_t *waveform_picker_regs = (waveform_picker_regs_0_1_18_t*) REGS_ADDR_WAVEFORM_PICKER;
66 waveform_picker_regs_0_1_18_t *waveform_picker_regs = (waveform_picker_regs_0_1_18_t*) REGS_ADDR_WAVEFORM_PICKER;
67 spectral_matrix_regs_t *spectral_matrix_regs = (spectral_matrix_regs_t*) REGS_ADDR_SPECTRAL_MATRIX;
67 spectral_matrix_regs_t *spectral_matrix_regs = (spectral_matrix_regs_t*) REGS_ADDR_SPECTRAL_MATRIX;
68
68
69 // MODE PARAMETERS
69 // MODE PARAMETERS
70 Packet_TM_LFR_PARAMETER_DUMP_t parameter_dump_packet = {0};
70 Packet_TM_LFR_PARAMETER_DUMP_t parameter_dump_packet = {0};
71 struct param_local_str param_local = {0};
71 struct param_local_str param_local = {0};
72 unsigned int lastValidEnterModeTime = {0};
72 unsigned int lastValidEnterModeTime = {0};
73
73
74 // HK PACKETS
74 // HK PACKETS
75 Packet_TM_LFR_HK_t housekeeping_packet = {0};
75 Packet_TM_LFR_HK_t housekeeping_packet = {0};
76 // message queues occupancy
76 // message queues occupancy
77 unsigned char hk_lfr_q_sd_fifo_size_max = 0;
77 unsigned char hk_lfr_q_sd_fifo_size_max = 0;
78 unsigned char hk_lfr_q_rv_fifo_size_max = 0;
78 unsigned char hk_lfr_q_rv_fifo_size_max = 0;
79 unsigned char hk_lfr_q_p0_fifo_size_max = 0;
79 unsigned char hk_lfr_q_p0_fifo_size_max = 0;
80 unsigned char hk_lfr_q_p1_fifo_size_max = 0;
80 unsigned char hk_lfr_q_p1_fifo_size_max = 0;
81 unsigned char hk_lfr_q_p2_fifo_size_max = 0;
81 unsigned char hk_lfr_q_p2_fifo_size_max = 0;
82 // sequence counters are incremented by APID (PID + CAT) and destination ID
82 // sequence counters are incremented by APID (PID + CAT) and destination ID
83 unsigned short sequenceCounters_SCIENCE_NORMAL_BURST = 0;
83 unsigned short sequenceCounters_SCIENCE_NORMAL_BURST __attribute__((aligned(0x4))) = 0;
84 unsigned short sequenceCounters_SCIENCE_SBM1_SBM2 = 0;
84 unsigned short sequenceCounters_SCIENCE_SBM1_SBM2 __attribute__((aligned(0x4))) = 0;
85 unsigned short sequenceCounters_TC_EXE[SEQ_CNT_NB_DEST_ID] = {0};
85 unsigned short sequenceCounters_TC_EXE[SEQ_CNT_NB_DEST_ID] __attribute__((aligned(0x4))) = {0};
86 unsigned short sequenceCounters_TM_DUMP[SEQ_CNT_NB_DEST_ID] = {0};
86 unsigned short sequenceCounters_TM_DUMP[SEQ_CNT_NB_DEST_ID] __attribute__((aligned(0x4))) = {0};
87 unsigned short sequenceCounterHK = {0};
87 unsigned short sequenceCounterHK __attribute__((aligned(0x4))) = {0};
88 spw_stats grspw_stats = {0};
88 spw_stats grspw_stats __attribute__((aligned(0x4))) = {0};
89
89
90 // TC_LFR_UPDATE_INFO
90 // TC_LFR_UPDATE_INFO
91 rw_f_t rw_f;
91 rw_f_t rw_f;
92
92
93 // TC_LFR_LOAD_FILTER_PAR
93 // TC_LFR_LOAD_FILTER_PAR
94 filterPar_t filterPar = {0};
94 filterPar_t filterPar = {0};
95
95
96 fbins_masks_t fbins_masks = {0};
96 fbins_masks_t fbins_masks = {0};
97 unsigned int acquisitionDurations[NB_ACQUISITION_DURATION]
97 unsigned int acquisitionDurations[NB_ACQUISITION_DURATION]
98 = {ACQUISITION_DURATION_F0, ACQUISITION_DURATION_F1, ACQUISITION_DURATION_F2};
98 = {ACQUISITION_DURATION_F0, ACQUISITION_DURATION_F1, ACQUISITION_DURATION_F2};
@@ -1,972 +1,972
1 /** This is the RTEMS initialization module.
1 /** This is the RTEMS initialization module.
2 *
2 *
3 * @file
3 * @file
4 * @author P. LEROY
4 * @author P. LEROY
5 *
5 *
6 * This module contains two very different information:
6 * This module contains two very different information:
7 * - specific instructions to configure the compilation of the RTEMS executive
7 * - specific instructions to configure the compilation of the RTEMS executive
8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
9 *
9 *
10 */
10 */
11
11
12 //*************************
12 //*************************
13 // GPL reminder to be added
13 // GPL reminder to be added
14 //*************************
14 //*************************
15
15
16 #include <rtems.h>
16 #include <rtems.h>
17
17
18 /* configuration information */
18 /* configuration information */
19
19
20 #define CONFIGURE_INIT
20 #define CONFIGURE_INIT
21
21
22 #include <bsp.h> /* for device driver prototypes */
22 #include <bsp.h> /* for device driver prototypes */
23
23
24 /* configuration information */
24 /* configuration information */
25
25
26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
28
28
29 #define CONFIGURE_MAXIMUM_TASKS 21 // number of tasks concurrently active including INIT
29 #define CONFIGURE_MAXIMUM_TASKS 21 // number of tasks concurrently active including INIT
30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
36 #define CONFIGURE_MAXIMUM_DRIVERS 16
36 #define CONFIGURE_MAXIMUM_DRIVERS 16
37 #define CONFIGURE_MAXIMUM_PERIODS 5 // [hous] [load] [avgv]
37 #define CONFIGURE_MAXIMUM_PERIODS 6 // [hous] [load] [avgv]
38 #define CONFIGURE_MAXIMUM_TIMERS 5 // [spiq] [link] [spacewire_reset_link]
38 #define CONFIGURE_MAXIMUM_TIMERS 6 // [spiq] [link] [spacewire_reset_link]
39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
40 #ifdef PRINT_STACK_REPORT
40 #ifdef PRINT_STACK_REPORT
41 #define CONFIGURE_STACK_CHECKER_ENABLED
41 #define CONFIGURE_STACK_CHECKER_ENABLED
42 #endif
42 #endif
43
43
44 #include <rtems/confdefs.h>
44 #include <rtems/confdefs.h>
45
45
46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
47 #ifdef RTEMS_DRVMGR_STARTUP
47 #ifdef RTEMS_DRVMGR_STARTUP
48 #ifdef LEON3
48 #ifdef LEON3
49 /* Add Timer and UART Driver */
49 /* Add Timer and UART Driver */
50
50
51 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
51 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
52 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
52 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
53 #endif
53 #endif
54
54
55 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
55 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
56 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
56 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
57 #endif
57 #endif
58
58
59 #endif
59 #endif
60 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
60 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
61
61
62 #include <drvmgr/drvmgr_confdefs.h>
62 #include <drvmgr/drvmgr_confdefs.h>
63 #endif
63 #endif
64
64
65 #include "fsw_init.h"
65 #include "fsw_init.h"
66 #include "fsw_config.c"
66 #include "fsw_config.c"
67 #include "GscMemoryLPP.hpp"
67 #include "GscMemoryLPP.hpp"
68
68
69 void initCache()
69 void initCache()
70 {
70 {
71 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
71 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
72 // These should only be read and written using 32-bit LDA/STA instructions.
72 // These should only be read and written using 32-bit LDA/STA instructions.
73 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
73 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
74 // The table below shows the register addresses:
74 // The table below shows the register addresses:
75 // 0x00 Cache control register
75 // 0x00 Cache control register
76 // 0x04 Reserved
76 // 0x04 Reserved
77 // 0x08 Instruction cache configuration register
77 // 0x08 Instruction cache configuration register
78 // 0x0C Data cache configuration register
78 // 0x0C Data cache configuration register
79
79
80 // Cache Control Register Leon3 / Leon3FT
80 // Cache Control Register Leon3 / Leon3FT
81 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
81 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
82 // RFT PS TB DS FD FI FT ST IB
82 // RFT PS TB DS FD FI FT ST IB
83 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
83 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
84 // IP DP ITE IDE DTE DDE DF IF DCS ICS
84 // IP DP ITE IDE DTE DDE DF IF DCS ICS
85
85
86 unsigned int cacheControlRegister;
86 unsigned int cacheControlRegister;
87
87
88 CCR_resetCacheControlRegister();
88 CCR_resetCacheControlRegister();
89 ASR16_resetRegisterProtectionControlRegister();
89 ASR16_resetRegisterProtectionControlRegister();
90
90
91 cacheControlRegister = CCR_getValue();
91 cacheControlRegister = CCR_getValue();
92 PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister);
92 PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister);
93 PRINTF1("(0) ASR16 = %x\n", *asr16Ptr);
93 PRINTF1("(0) ASR16 = %x\n", *asr16Ptr);
94
94
95 CCR_enableInstructionCache(); // ICS bits
95 CCR_enableInstructionCache(); // ICS bits
96 CCR_enableDataCache(); // DCS bits
96 CCR_enableDataCache(); // DCS bits
97 CCR_enableInstructionBurstFetch(); // IB bit
97 CCR_enableInstructionBurstFetch(); // IB bit
98
98
99 faultTolerantScheme();
99 faultTolerantScheme();
100
100
101 cacheControlRegister = CCR_getValue();
101 cacheControlRegister = CCR_getValue();
102 PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister);
102 PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister);
103 PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr);
103 PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr);
104
104
105 PRINTF("\n");
105 PRINTF("\n");
106 }
106 }
107
107
108 rtems_task Init( rtems_task_argument ignored )
108 rtems_task Init( rtems_task_argument ignored )
109 {
109 {
110 /** This is the RTEMS INIT taks, it is the first task launched by the system.
110 /** This is the RTEMS INIT taks, it is the first task launched by the system.
111 *
111 *
112 * @param unused is the starting argument of the RTEMS task
112 * @param unused is the starting argument of the RTEMS task
113 *
113 *
114 * The INIT task create and run all other RTEMS tasks.
114 * The INIT task create and run all other RTEMS tasks.
115 *
115 *
116 */
116 */
117
117
118 //***********
118 //***********
119 // INIT CACHE
119 // INIT CACHE
120
120
121 unsigned char *vhdlVersion;
121 unsigned char *vhdlVersion;
122
122
123 reset_lfr();
123 reset_lfr();
124
124
125 reset_local_time();
125 reset_local_time();
126
126
127 rtems_cpu_usage_reset();
127 rtems_cpu_usage_reset();
128
128
129 rtems_status_code status;
129 rtems_status_code status;
130 rtems_status_code status_spw;
130 rtems_status_code status_spw;
131 rtems_isr_entry old_isr_handler;
131 rtems_isr_entry old_isr_handler;
132
132
133 old_isr_handler = NULL;
133 old_isr_handler = NULL;
134
134
135 // UART settings
135 // UART settings
136 enable_apbuart_transmitter();
136 enable_apbuart_transmitter();
137 set_apbuart_scaler_reload_register(REGS_ADDR_APBUART, APBUART_SCALER_RELOAD_VALUE);
137 set_apbuart_scaler_reload_register(REGS_ADDR_APBUART, APBUART_SCALER_RELOAD_VALUE);
138
138
139 DEBUG_PRINTF("\n\n\n\n\nIn INIT *** Now the console is on port COM1\n")
139 DEBUG_PRINTF("\n\n\n\n\nIn INIT *** Now the console is on port COM1\n")
140