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/***********************************************************************//**
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* @file : lpc17xx_clkpwr.h
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* @brief : Contains all macro definitions and function prototypes
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* support for Clock and Power Control firmware library on LPC17xx
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* @version : 1.0
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* @date : 18. Mar. 2009
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* @author : HieuNguyen
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**************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**************************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup CLKPWR
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* @ingroup LPC1700CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef LPC17XX_CLKPWR_H_
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#define LPC17XX_CLKPWR_H_
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/* Includes ------------------------------------------------------------------- */
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#include "lpc17xx.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Private Macros ------------------------------------------------------------- */
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/** @defgroup CLKPWR_Private_Macros
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* @{
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*/
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/** @defgroup CLKPPWR_REGISTER_BIT_DEFINITIONS
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* @{
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*/
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/* Clock source selection multiplexer definition */
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/** Internal RC oscillator */
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#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
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/** Main oscillator */
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#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
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/** RTC oscillator */
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#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
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/** Clock source selection bit mask */
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#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
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/* Clock Output Configuration register definition */
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/** Selects the CPU clock as the CLKOUT source */
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#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
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/** Selects the main oscillator as the CLKOUT source */
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#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
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/** Selects the Internal RC oscillator as the CLKOUT source */
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#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
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/** Selects the USB clock as the CLKOUT source */
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#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
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/** Selects the RTC oscillator as the CLKOUT source */
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#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
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/** Integer value to divide the output clock by, minus one */
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#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
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/** CLKOUT enable control */
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#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
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/** CLKOUT activity indication */
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#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
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/** Clock source selection bit mask */
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#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
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/* PLL 0 control definition */
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/** PLL 0 control enable */
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#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
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/** PLL 0 control connect */
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#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
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/** PLL 0 control bit mask */
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#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
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/* PLL 0 Configuration register definition */
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/** PLL 0 Configuration MSEL field */
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#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
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/** PLL 0 Configuration NSEL field */
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#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
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/** PLL 0 Configuration bit mask */
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#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
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/* PLL 0 status definition */
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/** PLL 0 MSEL value */
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#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
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/** PLL NSEL get value */
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#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
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/** PLL status enable bit */
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#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
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/** PLL status Connect bit */
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#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
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/** PLL status lock */
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#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
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/* PLL0 Feed register definition */
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/** PLL0 Feed bit mask */
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#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
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/* USB PLL control definition */
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/** USB PLL control enable */
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#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
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/** USB PLL control connect */
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#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
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/** USB PLL control bit mask */
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#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
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/* USB PLL configuration definition */
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/** USB PLL MSEL set value */
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#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
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/** USB PLL PSEL set value */
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#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
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/** USB PLL configuration bit mask */
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#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
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/* USB PLL status definition */
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/** USB PLL MSEL get value */
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#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
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/** USB PLL PSEL get value */
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#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
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/** USB PLL status enable bit */
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#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
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/** USB PLL status Connect bit */
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#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
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/** USB PLL status lock */
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#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
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/* PLL1 Feed register definition */
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/** PLL1 Feed bit mask */
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#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
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/* CPU Clock Configuration register definition */
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/** CPU Clock configuration bit mask */
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#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
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/* USB Clock Configuration register definition */
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/** USB Clock Configuration bit mask */
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#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
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/* IRC Trim register definition */
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/** IRC Trim bit mask */
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#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
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/* Peripheral clock divider bit position definition */
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/** Peripheral Clock Selection 0 mask bit */
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#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
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/** Peripheral Clock Selection 1 mask bit */
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#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
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/** Macro to set peripheral clock of each type
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* p: position of two bits that hold divider of peripheral clock
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* n: value of divider of peripheral clock to be set */
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#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
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/** Macro to mask peripheral clock of each type */
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#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
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/** Macro to get peripheral clock of each type */
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#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
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/* Power Mode Control register definition */
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/** Power mode control bit 0 */
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#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
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/** Power mode control bit 1 */
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#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
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/** Brown-Out Reduced Power Mode */
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#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
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/** Brown-Out Global Disable */
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#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
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/** Brown Out Reset Disable */
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#define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
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/** Sleep Mode entry flag */
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#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
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/** Deep Sleep entry flag */
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#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
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/** Power-down entry flag */
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#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
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/** Deep Power-down entry flag */
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#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
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/** Power Control for Peripherals bit mask */
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#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Public Macros -------------------------------------------------------------- */
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/** @defgroup CLKPWR_Public_Macros
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* @{
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*/
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/**********************************************************************
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* Peripheral Clock Selection Definitions
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**********************************************************************/
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/** Peripheral clock divider bit position for WDT */
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#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
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/** Peripheral clock divider bit position for TIMER0 */
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#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
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/** Peripheral clock divider bit position for TIMER1 */
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#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
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/** Peripheral clock divider bit position for UART0 */
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#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
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/** Peripheral clock divider bit position for UART1 */
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#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
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/** Peripheral clock divider bit position for PWM1 */
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#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
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/** Peripheral clock divider bit position for I2C0 */
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#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
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/** Peripheral clock divider bit position for SPI */
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#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
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/** Peripheral clock divider bit position for SSP1 */
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#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
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/** Peripheral clock divider bit position for DAC */
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#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
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/** Peripheral clock divider bit position for ADC */
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#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
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/** Peripheral clock divider bit position for CAN1 */
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#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
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/** Peripheral clock divider bit position for CAN2 */
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#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
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/** Peripheral clock divider bit position for ACF */
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#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
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/** Peripheral clock divider bit position for QEI */
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#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
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/** Peripheral clock divider bit position for PCB */
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#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
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/** Peripheral clock divider bit position for I2C1 */
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#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
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/** Peripheral clock divider bit position for SSP0 */
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#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
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/** Peripheral clock divider bit position for TIMER2 */
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#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
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/** Peripheral clock divider bit position for TIMER3 */
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#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
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/** Peripheral clock divider bit position for UART2 */
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#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
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/** Peripheral clock divider bit position for UART3 */
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#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
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/** Peripheral clock divider bit position for I2C2 */
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#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
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/** Peripheral clock divider bit position for I2S */
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#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
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/** Peripheral clock divider bit position for RIT */
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#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
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/** Peripheral clock divider bit position for SYSCON */
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#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
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/** Peripheral clock divider bit position for MC */
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#define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
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/** Macro for Peripheral Clock Selection register bit values
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* Note: When CCLK_DIV_8, Peripheral�s clock is selected to
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* PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
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* when �11�selects PCLK_xyz = CCLK/6 */
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/* Peripheral clock divider is set to 4 from CCLK */
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#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
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/** Peripheral clock divider is the same with CCLK */
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#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
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/** Peripheral clock divider is set to 2 from CCLK */
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#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
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/********************************************************************
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* Power Control for Peripherals Definitions
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**********************************************************************/
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/** Timer/Counter 0 power/clock control bit */
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#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
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/* Timer/Counter 1 power/clock control bit */
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#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
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/** UART0 power/clock control bit */
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#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
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/** UART1 power/clock control bit */
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#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
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/** PWM1 power/clock control bit */
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#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
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/** The I2C0 interface power/clock control bit */
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#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
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/** The SPI interface power/clock control bit */
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#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
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/** The RTC power/clock control bit */
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#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
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/** The SSP1 interface power/clock control bit */
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#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
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/** A/D converter 0 (ADC0) power/clock control bit */
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#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
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/** CAN Controller 1 power/clock control bit */
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#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
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/** CAN Controller 2 power/clock control bit */
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#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
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/** GPIO power/clock control bit */
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#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
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/** Repetitive Interrupt Timer power/clock control bit */
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#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
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/** Motor Control PWM */
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#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
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/** Quadrature Encoder Interface power/clock control bit */
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#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
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/** The I2C1 interface power/clock control bit */
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#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
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/** The SSP0 interface power/clock control bit */
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#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
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/** Timer 2 power/clock control bit */
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#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
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/** Timer 3 power/clock control bit */
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#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
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/** UART 2 power/clock control bit */
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#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
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/** UART 3 power/clock control bit */
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#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
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/** I2C interface 2 power/clock control bit */
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#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
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/** I2S interface power/clock control bit*/
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#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
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/** GP DMA function power/clock control bit*/
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#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
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/** Ethernet block power/clock control bit*/
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#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
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/** USB interface power/clock control bit*/
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#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @defgroup CLKPWR_Public_Functions
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* @{
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*/
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void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
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uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
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uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
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void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
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void CLKPWR_Sleep(void);
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void CLKPWR_DeepSleep(void);
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void CLKPWR_PowerDown(void);
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void CLKPWR_DeepPowerDown(void);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* LPC17XX_CLKPWR_H_ */
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/**
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* @}
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*/
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/* --------------------------------- End Of File ------------------------------ */
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