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jeandet@pc-de-jeandet3.LAB-LPP.LOCAL -
r25:b4b05488cb5e default
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@@ -57,6 +57,7 extern void bsp_uart_init();
57 extern void bsp_iic_init();
57 extern void bsp_iic_init();
58 extern void bsp_spi_init();
58 extern void bsp_spi_init();
59 extern void bsp_SD_init();
59 extern void bsp_SD_init();
60 extern void bsp_FSMC_init();
60
61
61 /* VS1053 */
62 /* VS1053 */
62 extern void clearXCS();
63 extern void clearXCS();
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@@ -25,6 +25,7
25 #include <gpio.h>
25 #include <gpio.h>
26 #include <uart.h>
26 #include <uart.h>
27 #include <stdio.h>
27 #include <stdio.h>
28 #include <stm32f4xx_gpio.h>
28 uint32_t OSC0 =8000000;
29 uint32_t OSC0 =8000000;
29 uint32_t INTOSC =16000000;
30 uint32_t INTOSC =16000000;
30 uint32_t RTCOSC =32768;
31 uint32_t RTCOSC =32768;
@@ -81,15 +82,32 void bsp_uart_init()
81 {
82 {
82 if(__opnfiles__[1]==NULL)
83 if(__opnfiles__[1]==NULL)
83 {
84 {
84 uart_t* uart1 = (uart_t*)malloc(sizeof(uart_t));
85 //uart_t* uart1 = (uart_t*)malloc(sizeof(uart_t));
85 streamdevice* fd1 = (streamdevice*)malloc(sizeof(streamdevice));
86 streamdevice* fd1 = (streamdevice*)malloc(sizeof(streamdevice));
86 uartopenandconfig(0,uart1,uartparitynone | uart8bits | uartonestop,115200,PA9,PA10,-1,-1);
87 uart_t uart = uartopenandconfig(uart1,uartparitynone | uart8bits | uartonestop,115200,PA9,PA10,-1,-1);
87 uartmkstreamdev(uart1,fd1);
88 uartmkstreamdev(uart,fd1);
88 __opnfiles__[1] = fd1;
89 __opnfiles__[1] = fd1;
89 }
90 }
90 else
91 else
91 {
92 {
92 uartopenandconfig(0,(uart_t*)__opnfiles__[1]->_stream,uartparitynone | uart8bits | uartonestop,115200,PA9,PA10,-1,-1);
93 uartopenandconfig(0,uartparitynone | uart8bits | uartonestop,115200,PA9,PA10,-1,-1);
94 }
95 }
96
97
98 void bsp_FSMC_init()
99 {
100 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
101 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
102
103 gpio_t LCD_DBxList[]={PD14,PD15,PD0,PD1,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15\
104 ,PD8,PD9,PD10,PD4,PD5,PD7,PE4};
105 for(int i=0;i<20;i++)
106 {
107 gpio_t LCD_DBx = gpioopen(LCD_DBxList[i]);
108 LCD_DBx |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
109 gpiosetconfig(&LCD_DBx);
110 GPIO_PinAFConfig(GPIOGETPORT(LCD_DBx), (uint8_t)(LCD_DBx & 0xF), GPIO_AF_FSMC);
93 }
111 }
94 }
112 }
95
113
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@@ -70,15 +70,15 void bsp_uart_init()
70 {
70 {
71 if(__opnfiles__[1]==NULL)
71 if(__opnfiles__[1]==NULL)
72 {
72 {
73 uart_t* uart1 = (uart_t*)malloc(sizeof(uart_t));
73 //uart_t* uart1 = (uart_t*)malloc(sizeof(uart_t));
74 streamdevice* fd1 = (streamdevice*)malloc(sizeof(streamdevice));
74 streamdevice* fd1 = (streamdevice*)malloc(sizeof(streamdevice));
75 uartopenandconfig(2,uart1,uartparitynone | uart8bits | uartonestop,115200,PB10,PB11,-1,-1);
75 uart_t uart = uartopenandconfig(uart3,uartparitynone | uart8bits | uartonestop,115200,PB10,PB11,-1,-1);
76 uartmkstreamdev(uart1,fd1);
76 uartmkstreamdev(uart,fd1);
77 __opnfiles__[1] = fd1;
77 __opnfiles__[1] = fd1;
78 }
78 }
79 else
79 else
80 {
80 {
81 uartopenandconfig(2,(uart_t*)__opnfiles__[1]->_stream,uartparitynone | uart8bits | uartonestop,115200,PB10,PB11,-1,-1);
81 uartopenandconfig(2,uartparitynone | uart8bits | uartonestop,115200,PB10,PB11,-1,-1);
82 }
82 }
83 }
83 }
84
84
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@@ -59,29 +59,33 void bsp_GPIO_init()
59 gpio_t gpio2 = gpioopen(PD13);//gpioopen(LED2);
59 gpio_t gpio2 = gpioopen(PD13);//gpioopen(LED2);
60 gpio_t gpio3 = gpioopen(PD14);//gpioopen(LED2);
60 gpio_t gpio3 = gpioopen(PD14);//gpioopen(LED2);
61 gpio_t gpio4 = gpioopen(PD15);//gpioopen(LED2);
61 gpio_t gpio4 = gpioopen(PD15);//gpioopen(LED2);
62 gpio_t dacRst=gpioopen(PD4);
62 gpiosetspeed(&gpio1,gpiohighspeed);
63 gpiosetspeed(&gpio1,gpiohighspeed);
63 gpiosetspeed(&gpio2,gpiohighspeed);
64 gpiosetspeed(&gpio2,gpiohighspeed);
64 gpiosetspeed(&gpio3,gpiohighspeed);
65 gpiosetspeed(&gpio3,gpiohighspeed);
65 gpiosetspeed(&gpio4,gpiohighspeed);
66 gpiosetspeed(&gpio4,gpiohighspeed);
67 gpiosetspeed(&dacRst,gpiohighspeed);
66 gpiosetdir(&gpio1,gpiooutdir);
68 gpiosetdir(&gpio1,gpiooutdir);
67 gpiosetdir(&gpio3,gpiooutdir);
69 gpiosetdir(&gpio3,gpiooutdir);
68 gpiosetdir(&gpio2,gpiooutdir);
70 gpiosetdir(&gpio2,gpiooutdir);
69 gpiosetdir(&gpio4,gpiooutdir);
71 gpiosetdir(&gpio4,gpiooutdir);
72 gpiosetdir(&dacRst,gpiooutdir);
73 gpioset(dacRst);
70 }
74 }
71
75
72 void bsp_uart_init()
76 void bsp_uart_init()
73 {
77 {
74 if(__opnfiles__[1]==NULL)
78 if(__opnfiles__[1]==NULL)
75 {
79 {
76 uart_t* uart1 = (uart_t*)malloc(sizeof(uart_t));
80 //uart_t* uart1 = (uart_t*)malloc(sizeof(uart_t));
77 streamdevice* fd1 = (streamdevice*)malloc(sizeof(streamdevice));
81 streamdevice* fd1 = (streamdevice*)malloc(sizeof(streamdevice));
78 uartopenandconfig(2,uart1,uartparitynone | uart8bits | uartonestop,115200,PB10,PB11,-1,-1);
82 uart_t uart = uartopenandconfig(uart3,uartparitynone | uart8bits | uartonestop,115200,PB10,PB11,-1,-1);
79 uartmkstreamdev(uart1,fd1);
83 uartmkstreamdev(uart,fd1);
80 __opnfiles__[1] = fd1;
84 __opnfiles__[1] = fd1;
81 }
85 }
82 else
86 else
83 {
87 {
84 uartopenandconfig(2,(uart_t*)__opnfiles__[1]->_stream,uartparitynone | uart8bits | uartonestop,115200,PB10,PB11,-1,-1);
88 uartopenandconfig(2,uartparitynone | uart8bits | uartonestop,115200,PB10,PB11,-1,-1);
85 }
89 }
86 }
90 }
87
91
@@ -95,6 +99,8 void bsp_iic_init()
95 {
99 {
96 if(0==i2copenandconfig(i2c1,0,400000,PB9,PB6))printf("I2C1 opened\n\r");
100 if(0==i2copenandconfig(i2c1,0,400000,PB9,PB6))printf("I2C1 opened\n\r");
97 i2cenable(i2c1);
101 i2cenable(i2c1);
102 if(0==i2copenandconfig(i2c3,0,400000,PC9,PA8))printf("I2C3 opened\n\r");
103 i2cenable(i2c3);
98 }
104 }
99
105
100 void bsp_SD_init()
106 void bsp_SD_init()
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@@ -70,16 +70,16 void bsp_uart_init()
70 {
70 {
71 if(__opnfiles__[1]==NULL)
71 if(__opnfiles__[1]==NULL)
72 {
72 {
73 uart_t* uart1 = (uart_t*)malloc(sizeof(uart_t));
73 //uart_t* uart1 = (uart_t*)malloc(sizeof(uart_t));
74 streamdevice* fd1 = (streamdevice*)malloc(sizeof(streamdevice));
74 streamdevice* fd1 = (streamdevice*)malloc(sizeof(streamdevice));
75 uartopenandconfig(2,uart1,uartparitynone | uart8bits | uartonestop,19200,PB10,PB11,-1,-1);
75 uart_t uart = uartopenandconfig(uart3,uartparitynone | uart8bits | uartonestop,19200,PB10,PB11,-1,-1);
76 uartmkstreamdev(uart1,fd1);
76 uartmkstreamdev(uart,fd1);
77 __opnfiles__[1] = fd1; //stdo
77 __opnfiles__[1] = fd1; //stdo
78 __opnfiles__[0] = fd1; //stdi
78 __opnfiles__[0] = fd1; //stdi
79 }
79 }
80 else
80 else
81 {
81 {
82 uartopenandconfig(2,(uart_t*)__opnfiles__[1]->_stream,uartparitynone | uart8bits | uartonestop,115200,PB10,PB11,-1,-1);
82 uartopenandconfig(2,uartparitynone | uart8bits | uartonestop,115200,PB10,PB11,-1,-1);
83 }
83 }
84 }
84 }
85
85
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@@ -11,16 +11,6 extern streamdevice* __opnfiles__[];
11
11
12 int main()
12 int main()
13 {
13 {
14 //gpioset(PSU_DISABLE);
15 gpio_t dacRst=gpioopen(PD4);
16 gpiosetspeed(&dacRst,gpiohighspeed);
17 gpiosetdir(&dacRst,gpiooutdir);
18 gpioset(dacRst);
19 printf("i2C Control register 1 (I2C_CR1) = %x\n\r",I2C1->CR1);
20 printf("i2C Control register 2 (I2C_CR2) = %x\n\r",I2C1->CR2);
21 printf("i2C Status register 1 (I2C_SR1) = %x\n\r",I2C1->SR1);
22 printf("i2C Status register 2 (I2C_SR2) = %x\n\r",I2C1->SR2);
23 printf("i2C Clock control register (I2C_CCR) = %x\n\r",I2C1->CCR);
24 while(1)
14 while(1)
25 {
15 {
26 for(volatile int i=0;i<1024*2048;i++);
16 for(volatile int i=0;i<1024*2048;i++);
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@@ -18,11 +18,10 int main()
18 //sdcardmakeblkdev(&dev);
18 //sdcardmakeblkdev(&dev);
19
19
20 // mbropen(&dev,&part,1);
20 // mbropen(&dev,&part,1);
21 spi_t spi1;
21 spi_t spi = spiopenandconfig(spi2,spi8bits | spimaster |spiclkinhlow | spiclkfirstedge | spimsbfirst,10000,PB15,PB14,PB13,-1);
22 spiopenandconfig(1,&spi1,spi8bits | spimaster |spiclkinhlow | spiclkfirstedge | spimsbfirst,10000,PB15,PB14,PB13,-1);
23 while(1)
22 while(1)
24 {
23 {
25 spiputw(&spi1,0x15);
24 spiputw(spi,0x15);
26 for(volatile int i=0;i<1024*1024;i++);
25 for(volatile int i=0;i<1024*1024;i++);
27 }
26 }
28 printf("Hello world from project 'SDCARD'! %f\n\r",2.986*4.565);
27 printf("Hello world from project 'SDCARD'! %f\n\r",2.986*4.565);
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@@ -34,13 +34,25
34 extern "C" {
34 extern "C" {
35 #endif
35 #endif
36
36
37
37 /*
38 typedef struct spi_t
38 typedef struct spi_t
39 {
39 {
40 void* _dev;
40 void* _dev;
41 int cfg;
41 int cfg;
42 int speed;
42 int speed;
43 }spi_t;
43 }spi_t;*/
44
45 typedef int spi_t;
46
47 #define spi1 0
48 #define spi2 1
49 #define spi3 2
50 #define spi4 3
51 #define spi5 4
52 #define spi6 5
53 #define spi7 6
54 #define spi8 7
55 #define spi9 8
44
56
45
57
46 typedef enum
58 typedef enum
@@ -96,27 +108,27 typedef enum
96 #define SPIBITORDERMASK 0x80
108 #define SPIBITORDERMASK 0x80
97
109
98
110
99 extern int spiopen(int count,spi_t* spidev);
111 extern spi_t spiopen(int count);
100 extern int spiopenandconfig(int count,spi_t* spidev,uint32_t cfg,uint32_t speed,uint32_t MOSIpin,uint32_t MISOpin,uint32_t SCKpin,uint32_t SCSpin);
112 extern spi_t spiopenandconfig(int count,uint32_t cfg,uint32_t speed,uint32_t MOSIpin,uint32_t MISOpin,uint32_t SCKpin,uint32_t SCSpin);
101 extern int spiclose(spi_t* spidev);
113 extern int spiclose(spi_t spidev);
102 extern int spisetpins(spi_t* spidev,uint32_t MOSIpin,uint32_t MISOpin,uint32_t SCKpin,uint32_t SCSpin);
114 extern int spisetpins(spi_t spidev,uint32_t MOSIpin,uint32_t MISOpin,uint32_t SCKpin,uint32_t SCSpin);
103 extern int spienable(spi_t* spidev);
115 extern int spienable(spi_t spidev);
104 extern int spidisable(spi_t* spidev);
116 extern int spidisable(spi_t spidev);
105 extern int spisetconfig(spi_t* spidev);
117 extern int spisetconfig(spi_t spidev,uint32_t config,uint32_t speed);
106 extern int spisetspeed(spi_t* spidev, uint32_t speed);
118 extern int spisetspeed(spi_t spidev, uint32_t speed);
107 extern int spisetbitorder(spi_t* spidev,spibitorder_t order);
119 extern int spisetbitorder(spi_t spidev,spibitorder_t order);
108 extern int spisetdatabits(spi_t* spidev,spibits_t bitscnt);
120 extern int spisetdatabits(spi_t spidev,spibits_t bitscnt);
109 extern int spisetclkinhlevel(spi_t* spidev,spiclkinhlvl_t level);
121 extern int spisetclkinhlevel(spi_t spidev,spiclkinhlvl_t level);
110 extern int spisetclkphase(spi_t* spidev,spiclkphase_t phase);
122 extern int spisetclkphase(spi_t spidev,spiclkphase_t phase);
111 extern int spiputw(spi_t* spidev,uint16_t data);
123 extern int spiputw(spi_t spidev,uint16_t data);
112 extern uint16_t spigetw(spi_t* spidev);
124 extern uint16_t spigetw(spi_t spidev);
113 extern int spiputs(spi_t* spidev,char* s);
125 extern int spiputs(spi_t spidev,char* s);
114 extern int spigets(spi_t* spidev,char* s);
126 extern int spigets(spi_t spidev,char* s);
115 extern int spiputnw(spi_t* spidev,uint16_t* w,int n);
127 extern int spiputnw(spi_t spidev,uint16_t* w,int n);
116 extern int spigetnw(spi_t* spidev,uint16_t* w,int n);
128 extern int spigetnw(spi_t spidev,uint16_t* w,int n);
117 extern int spiputnc(spi_t* spidev,char* c,int n);
129 extern int spiputnc(spi_t spidev,char* c,int n);
118 extern int spigetnc(spi_t* spidev,char* c,int n);
130 extern int spigetnc(spi_t spidev,char* c,int n);
119 extern int spiavailiabledata(spi_t* spidev);
131 extern int spiavailiabledata(spi_t spidev);
120
132
121 #ifdef __cplusplus
133 #ifdef __cplusplus
122 }
134 }
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@@ -26,31 +26,44
26 #include <streamdevices.h>
26 #include <streamdevices.h>
27
27
28 #ifdef __cplusplus
28 #ifdef __cplusplus
29 extern "C" {
29 extern "C" {
30 #endif
30 #endif
31
31
32
32 /*
33 typedef volatile struct uart_t
33 typedef volatile struct uart_t
34 {
34 {
35 volatile void* _dev;
35 volatile void* _dev;
36 volatile int cfg;
36 volatile int cfg;
37 volatile int speed;
37 volatile int speed;
38 }uart_t;
38 }uart_t;
39 */
40
41 typedef int uart_t;
42 #define uart1 0
43 #define uart2 1
44 #define uart3 2
45 #define uart4 3
46 #define uart5 4
47 #define uart6 5
48 #define uart7 6
49 #define uart8 7
50 #define uart9 8
51
39
52
40 typedef enum
53 typedef enum
41 {
54 {
42 uartparitynone = 0x1,
55 uartparitynone = 0x1,
43 uartparityeven = 0x2,
56 uartparityeven = 0x2,
44 uartparityodd = 0x3
57 uartparityodd = 0x3
45 }uartparity_t;
58 }uartparity_t;
46
59
47 #define UARTPARITYMASK 0x3
60 #define UARTPARITYMASK 0x3
48
61
49 typedef enum
62 typedef enum
50 {
63 {
51 uart7bits = 0x4,
64 uart7bits = 0x4,
52 uart8bits = 0x8,
65 uart8bits = 0x8,
53 uart9bits = 0xC
66 uart9bits = 0xC
54 }uartbits_t;
67 }uartbits_t;
55
68
56 #define UARTBITSMASK 0xC
69 #define UARTBITSMASK 0xC
@@ -58,37 +71,37 typedef enum
58
71
59 typedef enum
72 typedef enum
60 {
73 {
61 uarthalfstop = 0x10,
74 uarthalfstop = 0x10,
62 uartonestop = 0x20,
75 uartonestop = 0x20,
63 uartonehalfstop = 0x30,
76 uartonehalfstop = 0x30,
64 uarttwostop = 0x40
77 uarttwostop = 0x40
65 }uartstopbits_t;
78 }uartstopbits_t;
66
79
67 #define UARTSTOPBITSMASK 0x70
80 #define UARTSTOPBITSMASK 0x70
68
81
69 extern int uartopen(int count ,uart_t* uart);
82 extern uart_t uartopen(int count);
70 extern int uartopenandconfig(int count ,uart_t* uart,uint32_t cfg,uint32_t speed,uint32_t TXpin,uint32_t RXpin,uint32_t RTSpin,uint32_t CTSpin);
83 extern uart_t uartopenandconfig(int count ,uint32_t cfg,uint32_t speed,uint32_t TXpin,uint32_t RXpin,uint32_t RTSpin,uint32_t CTSpin);
71 extern int uartclose(uart_t* uart);
84 extern int uartclose(uart_t uart);
72 extern int uartsetpins(uart_t* uart,uint32_t TXpin,uint32_t RXpin,uint32_t RTSpin,uint32_t CTSpin);
85 extern int uartsetpins(uart_t uart,uint32_t TXpin,uint32_t RXpin,uint32_t RTSpin,uint32_t CTSpin);
73 extern int uartenable(uart_t* uart);
86 extern int uartenable(uart_t uart);
74 extern int uartdisable(uart_t* uart);
87 extern int uartdisable(uart_t uart);
75 extern int uartsetconfig(uart_t* uart);
88 extern int uartsetconfig(uart_t uart,uint32_t cfg,uint32_t speed);
76 extern int uartsetspeed(uart_t* uart,int speed);
89 extern int uartsetspeed(uart_t uart,uint32_t speed);
77 extern int uartsetparity(uart_t* uart,uartparity_t parity);
90 extern int uartsetparity(uart_t uart,uartparity_t parity);
78 extern int uartsetdatabits(uart_t* uart,uartbits_t databits);
91 extern int uartsetdatabits(uart_t uart,uartbits_t databits);
79 extern int uartsetstopbits(uart_t* uart,uartstopbits_t stopbits);
92 extern int uartsetstopbits(uart_t uart,uartstopbits_t stopbits);
80 extern int uartputc(uart_t* uart,char c);
93 extern int uartputc(uart_t uart,char c);
81 extern char uartgetc(uart_t* uart);
94 extern char uartgetc(uart_t uart);
82 extern int uartputs(uart_t* uart,char* s);
95 extern int uartputs(uart_t uart,char* s);
83 extern int uartgets(uart_t* uart,char* s);
96 extern int uartgets(uart_t uart,char* s);
84 extern int uartputnc(uart_t* uart,char* c,int n);
97 extern int uartputnc(uart_t uart,char* c,int n);
85 extern int uartgetnc(uart_t* uart,char* c,int n);
98 extern int uartgetnc(uart_t uart,char* c,int n);
86 extern int uartavailiabledata(uart_t* uart);
99 extern int uartavailiabledata(uart_t uart);
87
100
88 extern int uartmkstreamdev(uart_t* uart,streamdevice* strdev);
101 extern int uartmkstreamdev(uart_t uart,streamdevice* strdev);
89
102
90 #ifdef __cplusplus
103 #ifdef __cplusplus
91 }
104 }
92 #endif
105 #endif
93 #endif //SPI_H
106 #endif //SPI_H
94
107
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@@ -1,6 +1,7
1 TEMPLATE = dir
1 TEMPLATE = dir
2 SUBDIRS += HEXVIEWER \
2 SUBDIRS += HEXVIEWER \
3 FILE_SYSTEM
3 FILE_SYSTEM \
4 CS43L22
4
5
5
6
6
7
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@@ -3,7 +3,8 CONFIG += ordered
3
3
4 SUBDIRS += stm32f4
4 SUBDIRS += stm32f4
5
5
6 SUBDIRS += common/FILE_SYSTEM
6 SUBDIRS += common/FILE_SYSTEM \
7 common/AUDIO
7
8
8 # common/STREAMDEVICES \
9 # common/STREAMDEVICES \
9 # common/STRINGS \
10 # common/STRINGS \
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This diff has been collapsed as it changes many lines, (606 lines changed) Show them Hide them
@@ -27,340 +27,396
27 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
27 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
28 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
28 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
29
29
30 int spiopen(int count,spi_t* spidev)
30
31 SPI_TypeDef* _spi_dev_table[3]={SPI1,SPI2,SPI3};
32
33 spi_t spiopen(int count)
31 {
34 {
32
35 #define _INIT_DEV(_RCC_) \
33 switch(count)
36 RCC_APB1PeriphClockCmd(_RCC_, ENABLE); \
34 {
37 RCC_APB1PeriphResetCmd(_RCC_, ENABLE); \
35 case 0:
38 RCC_APB1PeriphResetCmd(_RCC_, DISABLE); \
36 spidev->_dev = (void*)SPI1;
39 RCC_APB1PeriphClockCmd(_RCC_, ENABLE);
37 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
40
38 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
41 switch(count)
39 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
42 {
40 break;
43 case 0:
41 case 1:
44 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
42 spidev->_dev = (void*)SPI2;
45 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
43 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
46 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
44 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
47 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
45 RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
48 return (spi_t) 0;
46 break;
49 break;
47 case 2:
50 case 1:
48 spidev->_dev = (void*)SPI3;
51 _INIT_DEV(RCC_APB1Periph_SPI2);
49 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
52 return (spi_t) 1;
50 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
53 break;
51 RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
54 case 2:
52 break;
55 _INIT_DEV(RCC_APB1Periph_SPI3);
53 default:
56 return (spi_t) 2;
54 break;
57 break;
55 }
58 default:
56 spienable(spidev);
59 break;
57 return 1;
60 }
61 return -1;
58 }
62 }
59 int spiopenandconfig(int count,spi_t* spidev,uint32_t cfg,uint32_t speed,uint32_t MOSIpin,uint32_t MISOpin,uint32_t SCKpin,uint32_t SCSpin)
63
64 spi_t spiopenandconfig(int count, uint32_t cfg, uint32_t speed, uint32_t MOSIpin, uint32_t MISOpin, uint32_t SCKpin, uint32_t SCSpin)
60 {
65 {
61 spiopen(count ,spidev);
66 spi_t dev = spiopen(count);
62 spidev->cfg = cfg;
67 if(dev!=-1)
63 spidev->speed = speed;
68 {
64 spidisable(spidev);
69 spidisable(dev);
65 spisetpins(spidev,MOSIpin, MISOpin, SCKpin, SCSpin);
70 spisetpins(dev,MOSIpin, MISOpin, SCKpin, SCSpin);
66 spienable(spidev);
71 spienable(dev);
67 spisetconfig(spidev);
72 spisetconfig(dev,cfg,speed);
68 return 1;
73 }
74 return dev;
69 }
75 }
70
76
71
77
72 int spiclose(spi_t* spidev)
78 int spiclose(spi_t spidev)
73 {
79 {
74 switch((int)spidev->_dev)
80 if((spidev<3)&&(spidev>=0))
75 {
81 {
76 case (int)(void*)SPI1:
82 switch(spidev)
77 spidev->_dev = (void*)SPI1;
83 {
78 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
84 case 0:
79 break;
85 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
80 case (int)(void*)SPI2:
86 break;
81 spidev->_dev = (void*)SPI2;
87 case 1:
82 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
88 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
83 break;
89 break;
84 case (int)(void*)SPI3:
90 case 2:
85 spidev->_dev = (void*)SPI3;
91 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
86 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
92 break;
87 break;
93 default:
88 default:
94 return -1;
89 break;
95 break;
90 }
96 }
91 return 1;
97 return 1;
98 }
99 return -1;
92 }
100 }
93
101
94 int spisetpins(spi_t* spidev,uint32_t MOSIpin,uint32_t MISOpin,uint32_t SCKpin,uint32_t SCSpin)
102 int spisetpins(spi_t spidev,uint32_t MOSIpin,uint32_t MISOpin,uint32_t SCKpin,uint32_t SCSpin)
95 {
103 {
96 gpio_t MISO,MOSI,SCK,SCS;
104 if((spidev<3)&&(spidev>=0))
97 uint8_t gpioAFspix = GPIO_AF_SPI1;
105 {
98 switch((int)spidev->_dev)
106 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
99 {
107 gpio_t MISO,MOSI,SCK,SCS;
100 case (int)(void*)SPI1:
108 uint8_t gpioAFspix = GPIO_AF_SPI1;
101 gpioAFspix = GPIO_AF_SPI1;
109 switch(spidev)
102 break;
110 {
103 case (int)(void*)SPI2:
111 case 0:
104 gpioAFspix = GPIO_AF_SPI2;
112 gpioAFspix = GPIO_AF_SPI1;
105 break;
113 break;
106 case (int)(void*)SPI3:
114 case 1:
107 gpioAFspix = GPIO_AF_SPI3;
115 gpioAFspix = GPIO_AF_SPI2;
108 break;
116 break;
109 default:
117 case 2:
110 break;
118 gpioAFspix = GPIO_AF_SPI3;
111 }
119 break;
112 if(MISOpin!=-1)
120 default:
113 {
121 break;
114 MISO = gpioopen(MISOpin);
122 }
115 MISO |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
123 if(MISOpin!=-1)
116 gpiosetconfig(&MISO);
124 {
117 GPIO_PinAFConfig(GPIOGETPORT(MISO), (uint8_t)(MISO & 0xF), gpioAFspix);
125 MISO = gpioopen(MISOpin);
118 }
126 MISO |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
119 if(MOSIpin!=-1)
127 gpiosetconfig(&MISO);
120 {
128 GPIO_PinAFConfig(GPIOGETPORT(MISO), (uint8_t)(MISO & 0xF), gpioAFspix);
121 MOSI = gpioopen(MOSIpin);
129 }
122 MOSI |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
130 if(MOSIpin!=-1)
123 gpiosetconfig(&MOSI);
131 {
124 GPIO_PinAFConfig(GPIOGETPORT(MOSI), (uint8_t)(MOSI & 0xF), gpioAFspix);
132 MOSI = gpioopen(MOSIpin);
125 }
133 MOSI |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
126
134 gpiosetconfig(&MOSI);
127 if(SCKpin!=-1)
135 GPIO_PinAFConfig(GPIOGETPORT(MOSI), (uint8_t)(MOSI & 0xF), gpioAFspix);
128 {
136 }
129 SCK = gpioopen(SCKpin);
130 SCK |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
131 gpiosetconfig(&SCK);
132 GPIO_PinAFConfig(GPIOGETPORT(SCK), (uint8_t)(SCK & 0xF), gpioAFspix);
133 }
134
137
135 if(SCSpin!=-1)
138 if(SCKpin!=-1)
136 {
139 {
137 SCS = gpioopen(SCSpin);
140 SCK = gpioopen(SCKpin);
138 SCS |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
141 SCK |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
139 gpiosetconfig(&SCS);
142 gpiosetconfig(&SCK);
140 GPIO_PinAFConfig(GPIOGETPORT(SCS), (uint8_t)(SCS & 0xF), gpioAFspix);
143 GPIO_PinAFConfig(GPIOGETPORT(SCK), (uint8_t)(SCK & 0xF), gpioAFspix);
141 ((SPI_TypeDef *)(spidev->_dev))->CR2 |= (1<<2);
144 }
142 }
145
143 else
146 if(SCSpin!=-1)
144 {
147 {
145 ((SPI_TypeDef *)(spidev->_dev))->CR2 &= ~(1<<2);
148 SCS = gpioopen(SCSpin);
146 }
149 SCS |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
147 return 1;
150 gpiosetconfig(&SCS);
151 GPIO_PinAFConfig(GPIOGETPORT(SCS), (uint8_t)(SCS & 0xF), gpioAFspix);
152 _dev_->CR2 |= (1<<2);
153 }
154 else
155 {
156 _dev_->CR2 &= ~(1<<2);
157 }
158 return 1;
159 }
160 return -1;
148 }
161 }
149
162
150
163
151 int spienable(spi_t* spidev)
164 int spienable(spi_t spidev)
152 {
165 {
153 ((SPI_TypeDef *)(spidev->_dev))->CR1 |= (1<<6);
166 if((spidev<3)&&(spidev>=0))
154 return 1;
167 {
168 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
169 _dev_->CR1 |= (1<<6);
170 return 1;
171 }
172 return -1;
155 }
173 }
156
174
157
175
158 int spidisable(spi_t* spidev)
176 int spidisable(spi_t spidev)
159 {
177 {
160 ((SPI_TypeDef *)(spidev->_dev))->CR1 &= ~(1<<6);
178 if((spidev<3)&&(spidev>=0))
161 return 1;
179 {
180 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
181 _dev_->CR1 &= ~(1<<6);
182 return 1;
183 }
184 return -1;
162 }
185 }
163
186
164 int spisetconfig(spi_t* spidev)
187 int spisetconfig(spi_t spidev, uint32_t config, uint32_t speed)
165 {
188 {
166 ((SPI_TypeDef *)(spidev->_dev))->CR2 |= (1<<2);
189 if((spidev<3)&&(spidev>=0))
167 ((SPI_TypeDef *)(spidev->_dev))->CR1 |= (1<<2);
190 {
168
191 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
169 spisetspeed(spidev,spidev->speed);
192 _dev_->CR2 |= (1<<2);
170 spisetdatabits(spidev,spidev->cfg & SPIBITSMASK);
193 _dev_->CR1 |= (1<<2);
171 spisetbitorder(spidev,spidev->cfg & SPIBITORDERMASK);
194 spisetspeed(spidev,speed);
172 spisetclkinhlevel(spidev,spidev->cfg & SPICLKINHLVLMASK);
195 spisetdatabits(spidev,config & SPIBITSMASK);
173 spisetclkphase(spidev,spidev->cfg & SPICLKPHASEMASK);
196 spisetbitorder(spidev,config & SPIBITORDERMASK);
174
197 spisetclkinhlevel(spidev,config & SPICLKINHLVLMASK);
175 return 1;
198 spisetclkphase(spidev,config & SPICLKPHASEMASK);
199 return 0;
200 }
201 return 1;
176 }
202 }
177
203
178 int spisetspeed(spi_t* spidev, uint32_t speed)
204 int spisetspeed(spi_t spidev, uint32_t speed)
179 {
205 {
180 spidev->speed = speed;
206 if((spidev<3)&&(spidev>=0))
181 uint32_t apbclock = 0x00;
207 {
182 /*uint32_t tmpreg = 0x00;
208 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
183 uint32_t integerdivider = 0x00;
209 uint32_t apbclock = 0x00;
184 uint32_t fractionaldivider = 0x00;*/
210 RCC_ClocksTypeDef RCC_ClocksStatus;
185 RCC_ClocksTypeDef RCC_ClocksStatus;
211 RCC_GetClocksFreq(&RCC_ClocksStatus);
186 RCC_GetClocksFreq(&RCC_ClocksStatus);
212 if (_dev_ == SPI1)
187 if ((SPI_TypeDef *)(spidev->_dev) == SPI1)
213 {
188 {
214 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
189 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
215 }
190 }
216 else
191 else
217 {
192 {
218 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
193 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
219 }
194 }
220 int32_t speederror = 0x7FFFFFFF; //max error
195 int32_t speederror = 0x7FFFFFFF; //max error
221 int32_t prev_speederror = 0x7FFFFFFF;
196 int32_t prev_speederror = 0x7FFFFFFF;
222 int32_t realspeed = 0;
197 int32_t realspeed = 0;
223 unsigned char divider = 0;
198 unsigned char divider = 0;
224 do
199 do
225 {
200 {
226 divider ++;
201 divider ++;
227 prev_speederror = speederror;
202 prev_speederror = speederror;
228 realspeed = apbclock>>(divider);
203 realspeed = apbclock>>(divider);
229 speederror = realspeed - speed;
204 speederror = realspeed - speed;
230 if(speederror<0)speederror=-speederror;
205 if(speederror<0)speederror=-speederror;
231 if(divider>8)break;
206 if(divider>8)break;
232 }while(speederror<prev_speederror);
207 }while(speederror<prev_speederror);
233 speed = apbclock>>(divider-1);
208 spidev->speed = apbclock>>(divider-1);
234 divider-=2;
209 divider-=2;
235 _dev_->CR1 &= 0xFFD7; // clear prescaler bits 3:5
210 ((SPI_TypeDef *)(spidev->_dev))->CR1 &= 0xFFD7; // clear prescaler bits 3:5
236 _dev_->CR1 |= ((0x7 & divider)<<3);
211 ((SPI_TypeDef *)(spidev->_dev))->CR1 |= ((0x7 & divider)<<3);
237 return 1;
212 //((SPI_TypeDef *)(spidev->_dev))->CR1 |= ((0x7 & 7)<<3);
238 }
213 return 1;
239 return -1;
214 }
240 }
215
241
216
242
217 int spisetdatabits(spi_t* spidev,spibits_t bitscnt)
243 int spisetdatabits(spi_t spidev,spibits_t bitscnt)
218 {
244 {
219 int result = 0;
245 if((spidev<3)&&(spidev>=0))
220 switch(bitscnt)
246 {
221 {
247 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
222 case spi8bits:
248 int result = 0;
223 ((SPI_TypeDef *)(spidev->_dev))->CR1 &= ~(1<<11);
249 switch(bitscnt)
224 result = 1;
250 {
225 break;
251 case spi8bits:
226 case spi16bits:
252 _dev_->CR1 &= ~(1<<11);
227 ((SPI_TypeDef *)(spidev->_dev))->CR1 |= (1<<11);
253 result = 1;
228 result = 1;
254 break;
229 break;
255 case spi16bits:
230 default:
256 _dev_->CR1 |= (1<<11);
231 break;
257 result = 1;
232 }
258 break;
233 return result;
259 default:
260 result =-1;
261 break;
262 }
263 return result;
264 }
265 return -1;
234 }
266 }
235
267
236 int spisetbitorder(spi_t* spidev,spibitorder_t order)
268 int spisetbitorder(spi_t spidev,spibitorder_t order)
237 {
269 {
238 if(order==spimsbfirst)
270 if((spidev<3)&&(spidev>=0))
239 {
271 {
240 ((SPI_TypeDef *)(spidev->_dev))->CR1 &= ~(1<<7);
272 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
241 return 1;
273 if(order==spimsbfirst)
242 }
274 {
243 else
275 _dev_->CR1 &= ~(1<<7);
244 {
276 return 1;
245 if(order==spilsbfirst)
277 }
246 {
278 else
247 ((SPI_TypeDef *)(spidev->_dev))->CR1 |= (1<<7);
279 {
248 return 1;
280 if(order==spilsbfirst)
249 }
281 {
250 else return 0;
282 _dev_->CR1 |= (1<<7);
251 }
283 return 1;
252
284 }
285 else return -1;
286 }
287 }
288 return -1;
253 }
289 }
254
290
255 int spisetclkinhlevel(spi_t* spidev,spiclkinhlvl_t level)
291 int spisetclkinhlevel(spi_t spidev,spiclkinhlvl_t level)
256 {
292 {
257 if(level==spiclkinhlow)
293 if((spidev<3)&&(spidev>=0))
258 {
294 {
259 ((SPI_TypeDef *)(spidev->_dev))->CR1 &= ~(1<<1);
295 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
260 return 1;
296 if(level==spiclkinhlow)
261 }
297 {
262 else
298 _dev_->CR1 &= ~(1<<1);
263 {
299 return 1;
264 if(level==spiclkinhhigh)
300 }
265 {
301 else
266 ((SPI_TypeDef *)(spidev->_dev))->CR1 |= (1<<1);
302 {
267 return 1;
303 if(level==spiclkinhhigh)
268 }
304 {
269 else return 0;
305 _dev_->CR1 |= (1<<1);
270 }
306 return 1;
271 }
307 }
272
308 else return -1;
273 int spisetclkphase(spi_t* spidev,spiclkphase_t phase)
309 }
274 {
310 }
275 if(phase==spiclkfirstedge)
311 return -1;
276 {
277 ((SPI_TypeDef *)(spidev->_dev))->CR1 &= ~1;
278 return 1;
279 }
280 else
281 {
282 if(phase==spiclksecondedge)
283 {
284 ((SPI_TypeDef *)(spidev->_dev))->CR1 |= 1;
285 return 1;
286 }
287 else return 0;
288 }
289 }
312 }
290
313
291 int spiputw(spi_t* spidev,uint16_t data)
314 int spisetclkphase(spi_t spidev,spiclkphase_t phase)
292 {
315 {
293 ((SPI_TypeDef *)(spidev->_dev))->DR = data;
316 if((spidev<3)&&(spidev>=0))
294 while((((SPI_TypeDef *)(spidev->_dev))->SR & (1<<7)) == (1<<7));
317 {
295 return 1;
318 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
296 }
319 if(phase==spiclkfirstedge)
297 uint16_t spigetw(spi_t* spidev)
320 {
298 {
321 _dev_->CR1 &= ~1;
299 while((((SPI_TypeDef *)(spidev->_dev))->SR & (1<<7)) == (1<<7));
322 return 1;
300 ((SPI_TypeDef *)(spidev->_dev))->DR = 0xFFFF;
323 }
301 while((((SPI_TypeDef *)(spidev->_dev))->SR & (1<<0)) == 0);
324 else
302 return ((SPI_TypeDef *)(spidev->_dev))->DR;
325 {
326 if(phase==spiclksecondedge)
327 {
328 _dev_->CR1 |= 1;
329 return 1;
330 }
331 else return -1;
332 }
333 }
334 return -1;
303 }
335 }
304
336
305 int spiputs(spi_t* spidev,char* s)
337 int spiputw(spi_t spidev,uint16_t data)
306 {
338 {
307 while (*s) spiputw(spidev,*s++);
339 if((spidev<3)&&(spidev>=0))
308 return 1;
340 {
341 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
342 _dev_->DR = data;
343 while((_dev_->SR & (1<<7)) == (1<<7));
344 return 1;
345 }
346 return -1;
347 }
348 uint16_t spigetw(spi_t spidev)
349 {
350 if((spidev<3)&&(spidev>=0))
351 {
352 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
353 while((_dev_->SR & (1<<7)) == (1<<7));
354 _dev_->DR = 0xFFFF;
355 while((_dev_->SR & (1<<0)) == 0);
356 return _dev_->DR;
357 }
358 return -1;
309 }
359 }
310
360
311 int spigets(spi_t* spidev,char* s)
361 int spiputs(spi_t spidev,char* s)
312 {
362 {
313 do
363 while (*s) spiputw(spidev,*s++);
314 {
364 return 1;
315 (*s) = spigetw(spidev);
316 }
317 while(*s++);
318 return 1;
319 }
365 }
320
366
321 int spiputnw(spi_t* spidev,uint16_t* w,int n)
367 int spigets(spi_t spidev,char* s)
322 {
368 {
323 while(n!=0)
369 do
324 {
370 {
325 spiputw(spidev,*w++);
371 (*s) = spigetw(spidev);
326 n--;
372 }
327 }
373 while(*s++);
328 return 1;
374 return 1;
329 }
375 }
330
376
331 int spigetnw(spi_t* spidev,uint16_t* w,int n)
377 int spiputnw(spi_t spidev,uint16_t* w,int n)
332 {
378 {
333 while(n!=0)
379 while(n!=0)
334 {
380 {
335 *w++=spigetw(spidev);
381 spiputw(spidev,*w++);
336 n--;
382 n--;
337 }
383 }
338 return 1;
384 return 1;
339 }
385 }
340
386
341 int spiputnc(spi_t* spidev,char* c,int n)
387 int spigetnw(spi_t spidev,uint16_t* w,int n)
342 {
388 {
343 while(n!=0)
389 while(n!=0)
344 {
390 {
345 spiputw(spidev,*c++);
391 *w++=spigetw(spidev);
346 n--;
392 n--;
347 }
393 }
348 return 1;
394 return 1;
349 }
395 }
350
396
351 int spigetnc(spi_t* spidev,char* c,int n)
397 int spiputnc(spi_t spidev,char* c,int n)
352 {
398 {
353 while(n!=0)
399 while(n!=0)
354 {
400 {
355 *c++=spigetw(spidev);
401 spiputw(spidev,*c++);
356 n--;
402 n--;
357 }
403 }
358 return 1;
404 return 1;
359 }
405 }
360
406
361 int spiavailiabledata(spi_t*spidev)
407 int spigetnc(spi_t spidev,char* c,int n)
362 {
408 {
363 return 0;
409 while(n!=0)
410 {
411 *c++=spigetw(spidev);
412 n--;
413 }
414 return 1;
415 }
416
417 int spiavailiabledata(spi_t spidev)
418 {
419 return 0;
364 }
420 }
365
421
366
422
Show file before | Show file after | Hide comments
@@ -28,323 +28,351
28 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
28 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
29 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
29 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
30
30
31 int uartopen(int count ,uart_t* uart)
31 USART_TypeDef* _uart_dev_table[6]={USART1,USART2,USART3,UART4,UART5,USART6};
32
33
34 uart_t uartopen(int count)
32 {
35 {
33
36
34 switch(count)
37 switch(count)
35 {
38 {
36 case 0:
39 case 0:
37 uart->_dev = (void*)USART1;
38 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
40 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
39 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
41 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
40 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
42 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
41 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
43 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
42 ((USART_TypeDef *)(uart->_dev))->CR3 &= ~((1<<8) + (1<<9));
44 USART1->CR3 &= ~((1<<8) + (1<<9));
43 //uartenable(uart);
45 return (uart_t)0;
44 break;
46 break;
45 case 1:
47 case 1:
46 uart->_dev = (void*)USART2;
47 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
48 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
48 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
49 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
49 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
50 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
50 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
51 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
51 ((USART_TypeDef *)(uart->_dev))->CR3 &= ~((1<<8) + (1<<9));
52 USART2->CR3 &= ~((1<<8) + (1<<9));
52 //uartenable(uart);
53 return (uart_t)1;
53 break;
54 break;
54 case 2:
55 case 2:
55 uart->_dev = (void*)USART3;
56 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
56 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
57 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
57 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
58 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
58 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
59 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
59 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
60 ((USART_TypeDef *)(uart->_dev))->CR3 &= ~((1<<8) + (1<<9));
60 USART3->CR3 &= ~((1<<8) + (1<<9));
61 //uartenable(uart);
61 return (uart_t)2;
62 break;
62 break;
63 case 3:
63 case 3:
64 uart->_dev = (void*)UART4;
65 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
64 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
66 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
65 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
67 RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
66 RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
68 ((USART_TypeDef *)(uart->_dev))->CR3 &= ~((1<<8) + (1<<9));
67 UART4->CR3 &= ~((1<<8) + (1<<9));
69 //uartenable(uart);
68 return (uart_t)3;
70 break;
69 break;
71 case 4:
70 case 4:
72 uart->_dev = (void*)UART5;
73 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
71 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
74 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
72 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
75 RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
73 RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
74 return (uart_t)4;
76 break;
75 break;
77 case 5:
76 case 5:
78 uart->_dev = (void*)USART6;
79 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
77 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
80 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
78 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
81 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
79 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
80 return (uart_t)5;
82 break;
81 break;
83 default:
82 default:
84 break;
83 break;
85 }
84 }
85 return -1;
86 }
87
88 uart_t uartopenandconfig(int count, uint32_t cfg, uint32_t speed, uint32_t TXpin, uint32_t RXpin, uint32_t RTSpin, uint32_t CTSpin)
89 {
90 uart_t dev= uartopen(count);
91 uartsetconfig(dev,cfg,speed);
92 uartsetpins(dev,TXpin,RXpin,RTSpin,CTSpin);
93 return 1;
94 }
95
96
97 int uartclose(uart_t uart)
98 {
99 switch(uart)
100 {
101 case 0:
102 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
103 break;
104 case 1:
105 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
106 break;
107 case 2:
108 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
109 break;
110 case 3:
111 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
112 break;
113 case 4:
114 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
115 break;
116 case 5:
117 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
118 break;
119 default:
120 return -1;
121 break;
122 }
86 return 1;
123 return 1;
87 }
124 }
88
125
89 int uartopenandconfig(int count ,uart_t* uart,uint32_t cfg,uint32_t speed,uint32_t TXpin,uint32_t RXpin,uint32_t RTSpin,uint32_t CTSpin)
126 int uartsetpins(uart_t uart,uint32_t TXpin,uint32_t RXpin,uint32_t RTSpin,uint32_t CTSpin)
90 {
127 {
91 uartopen(count ,uart);
128 if(uart >5)return -1;
92 uart->cfg = cfg;
129 if(uart <0)return -1;
93 uart->speed = speed;
130 gpio_t TX,RX,CTS,RTS;
94 uartsetconfig(uart);
131 TX = gpioopen(TXpin);
95 uartsetpins(uart,TXpin,RXpin,RTSpin,CTSpin);
132 RX = gpioopen(RXpin);
96 return 1;
133 TX |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
97 }
134 RX |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
98
135 gpiosetconfig(&TX);
99
136 gpiosetconfig(&RX);
100 int uartclose(uart_t* uart)
137 uint8_t gpioAFuartx = GPIO_AF_USART1;
101 {
138 switch(uart)
102 switch((int)uart->_dev)
103 {
139 {
104 case (int)(void*)USART1:
140 case 0:
105 uart->_dev = (void*)USART1;
106 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
107 break;
108 case (int)(void*)USART2:
109 uart->_dev = (void*)USART2;
110 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
111 break;
112 case (int)(void*)USART3:
113 uart->_dev = (void*)USART3;
114 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
115 break;
116 case (int)(void*)UART4:
117 uart->_dev = (void*)UART4;
118 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
119 break;
120 case (int)(void*)UART5:
121 uart->_dev = (void*)UART5;
122 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
123 break;
124 case (int)(void*)USART6:
125 uart->_dev = (void*)USART6;
126 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
127 break;
128 default:
129 break;
130 }
131 return 1;
132 }
133
134 int uartsetpins(uart_t* uart,uint32_t TXpin,uint32_t RXpin,uint32_t RTSpin,uint32_t CTSpin)
135 {
136 gpio_t TX,RX,CTS,RTS;
137 TX = gpioopen(TXpin);
138 RX = gpioopen(RXpin);
139 TX |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
140 RX |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
141 gpiosetconfig(&TX);
142 gpiosetconfig(&RX);
143 uint8_t gpioAFuartx = GPIO_AF_USART1;
144 switch((int)uart->_dev)
145 {
146 case (int)(void*)USART1:
147 gpioAFuartx = GPIO_AF_USART1;
141 gpioAFuartx = GPIO_AF_USART1;
148 break;
142 break;
149 case (int)(void*)USART2:
143 case 1:
150 gpioAFuartx = GPIO_AF_USART2;
144 gpioAFuartx = GPIO_AF_USART2;
151 break;
145 break;
152 case (int)(void*)USART3:
146 case 2:
153 gpioAFuartx = GPIO_AF_USART3;
147 gpioAFuartx = GPIO_AF_USART3;
154 break;
148 break;
155 case (int)(void*)UART4:
149 case 3:
156 gpioAFuartx = GPIO_AF_UART4;
150 gpioAFuartx = GPIO_AF_UART4;
157 break;
151 break;
158 case (int)(void*)UART5:
152 case 4:
159 gpioAFuartx = GPIO_AF_UART5;
153 gpioAFuartx = GPIO_AF_UART5;
160 break;
154 break;
161 case (int)(void*)USART6:
155 case 5:
162 gpioAFuartx = GPIO_AF_USART6;
156 gpioAFuartx = GPIO_AF_USART6;
163 break;
157 break;
164 default:
158 default:
159 return -1;
165 break;
160 break;
166 }
161 }
167 GPIO_PinAFConfig(GPIOGETPORT(TX), (uint8_t)(TX & 0xF), gpioAFuartx);
162 GPIO_PinAFConfig(GPIOGETPORT(TX), (uint8_t)(TX & 0xF), gpioAFuartx);
168 GPIO_PinAFConfig(GPIOGETPORT(RX), (uint8_t)(RX & 0xF), gpioAFuartx);
163 GPIO_PinAFConfig(GPIOGETPORT(RX), (uint8_t)(RX & 0xF), gpioAFuartx);
169 if((gpioAFuartx!=GPIO_AF_UART5) && (gpioAFuartx!=GPIO_AF_UART4))
164 if((gpioAFuartx!=GPIO_AF_UART5) && (gpioAFuartx!=GPIO_AF_UART4))
170 {
165 {
171 if(CTSpin!=-1)
166 if(CTSpin!=-1)
172 {
167 {
173 CTS = gpioopen(CTSpin);
168 CTS = gpioopen(CTSpin);
174 CTS |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
169 CTS |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
175 gpiosetconfig(&CTS);
170 gpiosetconfig(&CTS);
176 GPIO_PinAFConfig(GPIOGETPORT(CTS), (uint8_t)(CTS & 0xF), gpioAFuartx);
171 GPIO_PinAFConfig(GPIOGETPORT(CTS), (uint8_t)(CTS & 0xF), gpioAFuartx);
177 }
172 }
178
173
179 if(RTSpin!=-1)
174 if(RTSpin!=-1)
180 {
175 {
181 RTS = gpioopen(RTSpin);
176 RTS = gpioopen(RTSpin);
182 RTS |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
177 RTS |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
183 gpiosetconfig(&RTS);
178 gpiosetconfig(&RTS);
184 GPIO_PinAFConfig(GPIOGETPORT(RTS), (uint8_t)(RTS & 0xF), gpioAFuartx);
179 GPIO_PinAFConfig(GPIOGETPORT(RTS), (uint8_t)(RTS & 0xF), gpioAFuartx);
185 }
186 }
180 }
187 return 1;
181 }
182 return 1;
188 }
183 }
189
184
190 int uartsetconfig(uart_t* uart)
185 int uartsetconfig(uart_t uart, uint32_t cfg, uint32_t speed)
191 {
186 {
192 int res=1;
187 int res=1;
193 uartdisable(uart);
188 uartdisable(uart);
194 uartsetspeed(uart,uart->speed);
189 uartsetspeed(uart,speed);
195 uartsetparity(uart,uart->cfg & UARTPARITYMASK);
190 uartsetparity(uart,cfg & UARTPARITYMASK);
196 uartsetdatabits(uart,uart->cfg & UARTBITSMASK);
191 uartsetdatabits(uart,cfg & UARTBITSMASK);
197 uartsetstopbits(uart,uart->cfg & UARTSTOPBITSMASK);
192 uartsetstopbits(uart,cfg & UARTSTOPBITSMASK);
198 uartenable(uart);
193 uartenable(uart);
199 return res;
194 return res;
200 }
195 }
201
196
202 int uartenable(uart_t* uart)
197 int uartenable(uart_t uart)
203 {
198 {
204 ((USART_TypeDef *)(uart->_dev))->CR1 |= (1<<13);
199 if((uart<6)&&(uart>=0))
205 ((USART_TypeDef *)(uart->_dev))->CR1 |= (1<<2) + (1<<3);
200 {
206 ((USART_TypeDef *)(uart->_dev))->DR = ' ';
201 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
207 return 1;
202 _dev_->CR1 |= (1<<13);
203 _dev_->CR1 |= (1<<2) + (1<<3);
204 _dev_->DR = ' ';
205 return 1;
206 }
207 return -1;
208 }
208 }
209
209
210 int uartdisable(uart_t* uart)
210 int uartdisable(uart_t uart)
211 {
211 {
212 if((((USART_TypeDef *)(uart->_dev))->CR1 & ((1<<3) +(1<<13)))==((1<<3) +(1<<13)))
212 if((uart<6)&&(uart>=0))
213 {
213 {
214 while((((USART_TypeDef *)(uart->_dev))->SR & (uint16_t)(1<<7))!=(uint16_t)(1<<7));
214 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
215 if((_dev_->CR1 & ((1<<3) +(1<<13)))==((1<<3) +(1<<13)))
216 {
217 while((_dev_->SR & (uint16_t)(1<<7))!=(uint16_t)(1<<7));
218 }
219 _dev_->CR1 &= ~((1<<2) + (1<<3) +(1<<13));
220 return 1;
215 }
221 }
216 ((USART_TypeDef *)(uart->_dev))->CR1 &= ~((1<<2) + (1<<3) +(1<<13));
222 return -1;
217 return 1;
218 }
223 }
219
224
220 int uartsetspeed(uart_t* uart,int speed)
225 int uartsetspeed(uart_t uart,uint32_t speed)
221 {
226 {
222 uart->speed = speed;
227 if((uart<6)&&(uart>=0))
223 uint32_t tmpreg = 0x00, apbclock = 0x00;
224 uint32_t integerdivider = 0x00;
225 uint32_t fractionaldivider = 0x00;
226 RCC_ClocksTypeDef RCC_ClocksStatus;
227 RCC_GetClocksFreq(&RCC_ClocksStatus);
228
229 if (((USART_TypeDef *)(uart->_dev) == USART1) || (((USART_TypeDef *)(uart->_dev) == USART6)))
230 {
231 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
232 }
233 else
234 {
235 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
236 }
237 if (((((USART_TypeDef *)(uart->_dev))->CR1) & USART_CR1_OVER8) != (uint16_t)0)
238 {
228 {
239 integerdivider = ((25 * apbclock) / (2 * (speed)));
229 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
240 }
230 uint32_t tmpreg = 0x00, apbclock = 0x00;
241 else
231 uint32_t integerdivider = 0x00;
242 {
232 uint32_t fractionaldivider = 0x00;
243 integerdivider = ((25 * apbclock) / (4 * (speed)));
233 RCC_ClocksTypeDef RCC_ClocksStatus;
234 RCC_GetClocksFreq(&RCC_ClocksStatus);
235
236 if ((_dev_ == USART1) || ((_dev_ == USART6)))
237 {
238 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
239 }
240 else
241 {
242 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
243 }
244 if (((_dev_->CR1) & USART_CR1_OVER8) != (uint16_t)0)
245 {
246 integerdivider = ((25 * apbclock) / (2 * (speed)));
247 }
248 else
249 {
250 integerdivider = ((25 * apbclock) / (4 * (speed)));
251 }
252 tmpreg = (integerdivider / 100) << 4;
253 fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
254 if ((_dev_->CR1 & USART_CR1_OVER8) != (uint16_t)0)
255 {
256 tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
257 }
258 else
259 {
260 tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
261 }
262 _dev_->BRR = (uint16_t)tmpreg;
263 return 1;
244 }
264 }
245 tmpreg = (integerdivider / 100) << 4;
265 return -1;
246 fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
247 if ((((USART_TypeDef *)(uart->_dev))->CR1 & USART_CR1_OVER8) != (uint16_t)0)
248 {
249 tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
250 }
251 else
252 {
253 tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
254 }
255 ((USART_TypeDef *)(uart->_dev))->BRR = (uint16_t)tmpreg;
256 return 1;
257 }
266 }
258
267
259 int uartsetparity(uart_t* uart,uartparity_t parity)
268 int uartsetparity(uart_t uart,uartparity_t parity)
260 {
269 {
261 uart->cfg &= ~(UARTPARITYMASK);
270 if((uart<6)&&(uart>=0))
262 uart->cfg |= parity;
263 ((USART_TypeDef *)(uart->_dev))->CR1 &= ~(((1<<9)+(1<<10)));
264 switch(parity)
265 {
271 {
266 case uartparityeven:
272 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
267 ((USART_TypeDef *)(uart->_dev))->CR1 |= (1<<10);
273 _dev_->CR1 &= ~(((1<<9)+(1<<10)));
268 break;
274 switch(parity)
269 case uartparityodd:
275 {
270 ((USART_TypeDef *)(uart->_dev))->CR1 |= (1<<10) + (1<<9);
276 case uartparityeven:
271 break;
277 _dev_->CR1 |= (1<<10);
272 case uartparitynone:
278 break;
273 break;
279 case uartparityodd:
274 default :
280 _dev_->CR1 |= (1<<10) + (1<<9);
275 return 0;
281 break;
276 break;
282 case uartparitynone:
283 break;
284 default :
285 return 0;
286 break;
287 }
288 return 1;
277 }
289 }
278 return 1;
290 return -1;
291 }
292
293 int uartsetdatabits(uart_t uart,uartbits_t databits)
294 {
295 if((uart<6)&&(uart>=0))
296 {
297 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
298 _dev_->CR1 &= ~(((1<<12)));
299 switch(databits)
300 {
301 case uart7bits:
302 return 0;
303 break;
304 case uart8bits:
305 break;
306 case uart9bits:
307 _dev_->CR1 |= (1<<12);
308 break;
309 default :
310 return 0;
311 break;
312 }
313 return 1;
314 }
315 return -1;
279 }
316 }
280
317
281 int uartsetdatabits(uart_t* uart,uartbits_t databits)
318 int uartsetstopbits(uart_t uart,uartstopbits_t stopbits)
282 {
319 {
283 uart->cfg &= ~UARTBITSMASK;
320 if((uart<6)&&(uart>=0))
284 uart->cfg |= databits;
285 ((USART_TypeDef *)(uart->_dev))->CR1 &= ~(((1<<12)));
286 switch(databits)
287 {
321 {
288 case uart7bits:
322 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
289 return 0;
323 _dev_->CR2 &= ~(((1<<12)+(1<<13)));
290 break;
324 switch(stopbits)
291 case uart8bits:
325 {
292 break;
326 case uarthalfstop:
293 case uart9bits:
327 _dev_->CR2 |= (1<<12);
294 ((USART_TypeDef *)(uart->_dev))->CR1 |= (1<<12);
328 break;
295 break;
329 case uartonestop:
296 default :
330 break;
297 return 0;
331 case uartonehalfstop:
298 break;
332 _dev_->CR2 |= (1<<12) + (1<<13);
333 break;
334 case uarttwostop:
335 _dev_->CR2 |= (1<<13);
336 break;
337 default :
338 return 0;
339 break;
340 }
341 return 1;
299 }
342 }
300 return 1;
343 return -1;
301 }
344 }
302
345
303 int uartsetstopbits(uart_t* uart,uartstopbits_t stopbits)
346 int uartputc(uart_t uart,char c)
304 {
347 {
305 uart->cfg &= ~UARTSTOPBITSMASK;
348 if((uart<6)&&(uart>=0))
306 uart->cfg |= stopbits;
307 ((USART_TypeDef *)(uart->_dev))->CR2 &= ~(((1<<12)+(1<<13)));
308 switch(stopbits)
309 {
349 {
310 case uarthalfstop:
350 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
311 ((USART_TypeDef *)(uart->_dev))->CR2 |= (1<<12);
351 while((_dev_->SR & (uint16_t)(1<<7))!=(uint16_t)(1<<7));
312 break;
352 _dev_->DR = c;
313 case uartonestop:
353 return 1;
314 break;
315 case uartonehalfstop:
316 ((USART_TypeDef *)(uart->_dev))->CR2 |= (1<<12) + (1<<13);
317 break;
318 case uarttwostop:
319 ((USART_TypeDef *)(uart->_dev))->CR2 |= (1<<13);
320 break;
321 default :
322 return 0;
323 break;
324 }
354 }
325 return 1;
355 return -1;
326 }
356 }
327
357
328 int uartputc(uart_t* uart,char c)
358 char uartgetc(uart_t uart)
329 {
359 {
330 while((((USART_TypeDef *)(uart->_dev))->SR & (uint16_t)(1<<7))!=(uint16_t)(1<<7));
360 if((uart<6)&&(uart>=0))
331 ((USART_TypeDef *)(uart->_dev))->DR = c;
361 {
332 return 1;
362 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
363 while(!(_dev_->SR & (1<<5)));
364 return (char)_dev_->DR;
365 }
366 return -1;
333 }
367 }
334
368
335 char uartgetc(uart_t* uart)
369 int uartputs(uart_t uart,char* s)
336 {
337 while(!(((USART_TypeDef *)(uart->_dev))->SR & (1<<5)));
338 return (char)((USART_TypeDef *)(uart->_dev))->DR;
339 }
340
341 int uartputs(uart_t* uart,char* s)
342 {
370 {
343 while (*s) uartputc(uart,*s++);
371 while (*s) uartputc(uart,*s++);
344 return 1;
372 return 1;
345 }
373 }
346
374
347 int uartgets(uart_t* uart,char* s)
375 int uartgets(uart_t uart,char* s)
348 {
376 {
349 do
377 do
350 {
378 {
@@ -354,7 +382,7 int uartgets(uart_t* uart,char* s)
354 return 1;
382 return 1;
355 }
383 }
356
384
357 int uartputnc(uart_t* uart,char* c,int n)
385 int uartputnc(uart_t uart,char* c,int n)
358 {
386 {
359 int l=0;
387 int l=0;
360 while(l<n)
388 while(l<n)
@@ -365,7 +393,7 int uartputnc(uart_t* uart,char* c,int n
365 return n;
393 return n;
366 }
394 }
367
395
368 int uartgetnc(uart_t* uart,char* c,int n)
396 int uartgetnc(uart_t uart,char* c,int n)
369 {
397 {
370 int l=0;
398 int l=0;
371 while(l<n)
399 while(l<n)
@@ -376,23 +404,28 int uartgetnc(uart_t* uart,char* c,int n
376 return n;
404 return n;
377 }
405 }
378
406
379 int uartavailiabledata(uart_t* uart)
407 int uartavailiabledata(uart_t uart)
380 {
408 {
381 if(!(((USART_TypeDef *)(uart->_dev))->SR & (1<<5)))
409 if((uart<6)&&(uart>=0))
382 return 0;
410 {
383 else
411 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
384 return 1;
412 if(!(_dev_->SR & (1<<5)))
413 return 0;
414 else
415 return 1;
416 }
417 return -1;
385 }
418 }
386
419
387
420
388 int _uartstrwrite(streamdevice* device,void* data,int size, int n)
421 int _uartstrwrite(streamdevice* device,void* data,int size, int n)
389 {
422 {
390 return uartputnc((uart_t*) device->_stream,(char*) data,size*n);
423 return uartputnc((uart_t) device->_stream,(char*) data,size*n);
391 }
424 }
392
425
393 int _uartstrread(streamdevice* device,void* data,int size, int n)
426 int _uartstrread(streamdevice* device,void* data,int size, int n)
394 {
427 {
395 return uartgetnc((uart_t*) device->_stream,(char*) data,size*n);
428 return uartgetnc((uart_t) device->_stream,(char*) data,size*n);
396 }
429 }
397
430
398 int _uartstrsetpos(streamdevice* device,int pos)
431 int _uartstrsetpos(streamdevice* device,int pos)
@@ -400,7 +433,7 int _uartstrsetpos(streamdevice* device,
400 return 1;
433 return 1;
401 }
434 }
402
435
403 int uartmkstreamdev(uart_t* uart,streamdevice* strdev)
436 int uartmkstreamdev(uart_t uart,streamdevice* strdev)
404 {
437 {
405 strdev->_stream = (UHANDLE)uart;
438 strdev->_stream = (UHANDLE)uart;
406 strdev->write = (write_t)&_uartstrwrite;
439 strdev->write = (write_t)&_uartstrwrite;
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@@ -100,11 +100,12 int _open(const char *name, int flags, i
100 {
100 {
101 if(!strncmp("UART", name, 4) && ((name[4] & 0x30)==0x30))
101 if(!strncmp("UART", name, 4) && ((name[4] & 0x30)==0x30))
102 {
102 {
103 uart_t* uart1 = malloc(sizeof(uart_t));
103 //uart_t* uart1 = malloc(sizeof(uart_t));
104 streamdevice* fd1 = malloc(sizeof(streamdevice));
104 streamdevice* fd1 = malloc(sizeof(streamdevice));
105 if(uartopen((name[4] & 0xF)-1,uart1));
105 uart_t uart=uartopen((name[4] & 0xF)-1);
106 if(uart!=-1);
106 {
107 {
107 uartmkstreamdev(uart1,fd1);
108 uartmkstreamdev(uart,fd1);
108 int i=2;
109 int i=2;
109 while(i<__max_opened_files__ && __opnfiles__[i]!=NULL)i++;
110 while(i<__max_opened_files__ && __opnfiles__[i]!=NULL)i++;
110 if(i!=__max_opened_files__)
111 if(i!=__max_opened_files__)
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