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1 | ||
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2 | INCLUDEPATH += $$[QT_INSTALL_HEADERS]/STM32F4xx_StdPeriph_Driver | |
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3 | INCLUDEPATH += $$[QT_INSTALL_HEADERS]/STM32F4xx_CMSIS | |
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4 | ||
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5 | LIBS += -L$$[QT_INSTALL_LIBS]/$$UCMODEL | |
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6 | LIBS += -lcpu | |
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7 | ||
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8 | ||
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9 | ||
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10 | ||
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18 |
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1 | #include "stm32f4xx.h" | |
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2 | #include <stdint.h> | |
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3 | #include <stdlib.h> | |
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4 | #include <stdio.h> | |
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5 | #include <bsp.h> | |
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6 | #include <stm32f4xx_rcc.h> | |
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7 | #include <core.h> | |
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8 | extern int main(); | |
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9 | ||
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10 | ||
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11 | ||
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12 | void cpu_init() | |
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13 | { | |
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14 | extern uint32_t currentCpuFreq; | |
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15 | #ifndef CPUFREQ | |
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16 | #define CPUFREQ (16*1000*1000) | |
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17 | #endif | |
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18 | currentCpuFreq = CPUFREQ; | |
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19 | enable_FPU(); | |
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20 | RCC->CR |= (uint32_t)0x00000001; | |
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21 | FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; | |
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22 | reset_AHB1(); | |
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23 | reset_AHB2(); | |
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24 | reset_APB1(); | |
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25 | reset_APB2(); | |
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26 | RCC->CR |= (uint32_t)0x00000001; | |
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27 | FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; | |
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28 | RCC->CFGR = 0x00000000; | |
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29 | RCC->CIR = 0x00000000; | |
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30 | SCB->VTOR = FLASH_BASE; | |
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31 | RCC->APB1ENR |= RCC_APB1ENR_PWREN; | |
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32 | PWR->CR |= PWR_CR_PMODE; | |
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33 | currentCpuFreq=setCpuFreq(currentCpuFreq); | |
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34 | currentCpuFreq=getCpuFreq(); | |
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35 | configureSysTick(); | |
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36 | bsp_init(); | |
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37 | printf("SysTick Configured to reach 100us period\n\r"); | |
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38 | RCC_ClocksTypeDef RCC_ClocksStatus; | |
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39 | RCC_GetClocksFreq(&RCC_ClocksStatus); | |
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40 | printf("PLL Configured got:\n\r SYS=%uHz\n\r CPU=%uHz\n\r APB1=%uHz\n\r APB2=%uHz\n\r",(unsigned int)RCC_ClocksStatus.SYSCLK_Frequency,(unsigned int)RCC_ClocksStatus.HCLK_Frequency,(unsigned int)RCC_ClocksStatus.PCLK1_Frequency,(unsigned int)RCC_ClocksStatus.PCLK2_Frequency); | |
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41 | printf("Enter Main\n\r"); | |
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42 | int res=main(); | |
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43 | printf("\n\rprogram exited with code "); | |
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44 | printf("%u",res); | |
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45 | printf("\n\r"); | |
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46 | while(1) | |
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47 | { | |
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48 | delay_100us(10000); | |
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49 | gpioset(LED1); | |
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50 | delay_100us(10000); | |
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51 | gpioclr(LED1); | |
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52 | } | |
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53 | } | |
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54 | ||
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55 | ||
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56 | ||
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57 | ||
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58 | ||
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59 | ||
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60 | ||
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61 | ||
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62 | ||
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63 |
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1 | #include <stdint.h> | |
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2 | #include <streamdevices.h> | |
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3 | #include <stdio.h> | |
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4 | #include <bsp.h> | |
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5 | ||
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6 | const int32_t __max_opened_files__ = __MAX_OPENED_FILES__; | |
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7 | __IO streamdevice* __opnfiles__[__MAX_OPENED_FILES__]; | |
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8 | const int32_t __fs_root_size__ = __FS_ROOT_SIZE__; | |
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9 | int32_t __fs_root__[__FS_ROOT_SIZE__]; | |
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10 | ||
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11 | ||
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12 | /* | |
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13 | void __init_fs() | |
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14 | { | |
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15 | int i=0; | |
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16 | for(i=0;i<__fs_root_size__;i++) | |
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17 | { | |
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18 | __fs_root__[i]=(int32_t)NULL; | |
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19 | } | |
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20 | for(i=0;i<__max_opened_files__ ;i++) | |
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21 | { | |
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22 | __opnfiles__[i]._stream=NULL; | |
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23 | } | |
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24 | } | |
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25 | */ |
@@ -0,0 +1,454 | |||
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1 | ||
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2 | .syntax unified | |
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3 | .cpu cortex-m4 | |
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4 | /*.fpu softvfp*/ | |
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5 | .fpu fpv4-sp-d16 | |
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6 | .thumb | |
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7 | ||
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8 | .global g_pfnVectors | |
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9 | .global Default_Handler | |
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10 | ||
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11 | /* start address for the initialization values of the .data section. | |
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12 | defined in linker script */ | |
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13 | .word _sidata | |
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14 | /* start address for the .data section. defined in linker script */ | |
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15 | .word _sdata | |
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16 | /* end address for the .data section. defined in linker script */ | |
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17 | .word _edata | |
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18 | /* start address for the .bss section. defined in linker script */ | |
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19 | .word _sbss | |
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20 | /* end address for the .bss section. defined in linker script */ | |
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21 | .word _ebss | |
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22 | /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ | |
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23 | ||
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24 | ||
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25 | .section .text.Reset_Handler | |
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26 | .weak Reset_Handler | |
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27 | .type Reset_Handler, %function | |
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28 | Reset_Handler: | |
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29 | ||
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30 | /* Copy the data segment initializers from flash to SRAM */ | |
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31 | movs r1, #0 | |
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32 | b LoopCopyDataInit | |
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33 | ||
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34 | CopyDataInit: | |
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35 | ldr r3, =_sidata | |
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36 | ldr r3, [r3, r1] | |
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37 | str r3, [r0, r1] | |
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38 | adds r1, r1, #4 | |
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39 | ||
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40 | LoopCopyDataInit: | |
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41 | ldr r0, =_sdata | |
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42 | ldr r3, =_edata | |
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43 | adds r2, r0, r1 | |
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44 | cmp r2, r3 | |
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45 | bcc CopyDataInit | |
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46 | ldr r2, =_sbss | |
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47 | b LoopFillZerobss | |
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48 | /* Zero fill the bss segment. */ | |
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49 | FillZerobss: | |
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50 | movs r3, #0 | |
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51 | str r3, [r2], #4 | |
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52 | ||
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53 | LoopFillZerobss: | |
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54 | ldr r3, = _ebss | |
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55 | cmp r2, r3 | |
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56 | bcc FillZerobss | |
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57 | ||
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58 | bl cpu_init | |
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59 | bx lr | |
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60 | .size Reset_Handler, .-Reset_Handler | |
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61 | ||
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62 | .section .text.Default_Handler,"ax",%progbits | |
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63 | Default_Handler: | |
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64 | Infinite_Loop: | |
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65 | b Infinite_Loop | |
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66 | .size Default_Handler, .-Default_Handler | |
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67 | ||
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68 | ||
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69 | .section .isr_vector,"a",%progbits | |
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70 | .type g_pfnVectors, %object | |
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71 | .size g_pfnVectors, .-g_pfnVectors | |
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72 | ||
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73 | ||
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74 | g_pfnVectors: | |
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75 | .word _estack | |
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76 | .word Reset_Handler | |
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77 | .word NMI_Handler | |
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78 | .word HardFault_Handler | |
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79 | .word MemManage_Handler | |
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80 | .word BusFault_Handler | |
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81 | .word UsageFault_Handler | |
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82 | .word 0 | |
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83 | .word 0 | |
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84 | .word 0 | |
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85 | .word 0 | |
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86 | .word SVC_Handler | |
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87 | .word DebugMon_Handler | |
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88 | .word 0 | |
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89 | .word PendSV_Handler | |
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90 | .word SysTick_Handler | |
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91 | ||
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92 | /* External Interrupts */ | |
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93 | .word WWDG_IRQHandler /* Window WatchDog */ | |
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94 | .word PVD_IRQHandler /* PVD through EXTI Line detection */ | |
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95 | .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ | |
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96 | .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ | |
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97 | .word FLASH_IRQHandler /* FLASH */ | |
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98 | .word RCC_IRQHandler /* RCC */ | |
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99 | .word EXTI0_IRQHandler /* EXTI Line0 */ | |
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100 | .word EXTI1_IRQHandler /* EXTI Line1 */ | |
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101 | .word EXTI2_IRQHandler /* EXTI Line2 */ | |
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102 | .word EXTI3_IRQHandler /* EXTI Line3 */ | |
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103 | .word EXTI4_IRQHandler /* EXTI Line4 */ | |
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104 | .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ | |
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105 | .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ | |
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106 | .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ | |
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107 | .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ | |
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108 | .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ | |
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109 | .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ | |
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110 | .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ | |
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111 | .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ | |
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112 | .word CAN1_TX_IRQHandler /* CAN1 TX */ | |
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113 | .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ | |
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114 | .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ | |
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115 | .word CAN1_SCE_IRQHandler /* CAN1 SCE */ | |
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116 | .word EXTI9_5_IRQHandler /* External Line[9:5]s */ | |
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117 | .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ | |
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118 | .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ | |
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119 | .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ | |
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120 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ | |
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121 | .word TIM2_IRQHandler /* TIM2 */ | |
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122 | .word TIM3_IRQHandler /* TIM3 */ | |
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123 | .word TIM4_IRQHandler /* TIM4 */ | |
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124 | .word I2C1_EV_IRQHandler /* I2C1 Event */ | |
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125 | .word I2C1_ER_IRQHandler /* I2C1 Error */ | |
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126 | .word I2C2_EV_IRQHandler /* I2C2 Event */ | |
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127 | .word I2C2_ER_IRQHandler /* I2C2 Error */ | |
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128 | .word SPI1_IRQHandler /* SPI1 */ | |
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129 | .word SPI2_IRQHandler /* SPI2 */ | |
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130 | .word USART1_IRQHandler /* USART1 */ | |
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131 | .word USART2_IRQHandler /* USART2 */ | |
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132 | .word USART3_IRQHandler /* USART3 */ | |
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133 | .word EXTI15_10_IRQHandler /* External Line[15:10]s */ | |
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134 | .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ | |
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135 | .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ | |
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136 | .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ | |
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137 | .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ | |
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138 | .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ | |
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139 | .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ | |
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140 | .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ | |
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141 | .word FSMC_IRQHandler /* FSMC */ | |
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142 | .word SDIO_IRQHandler /* SDIO */ | |
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143 | .word TIM5_IRQHandler /* TIM5 */ | |
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144 | .word SPI3_IRQHandler /* SPI3 */ | |
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145 | .word UART4_IRQHandler /* UART4 */ | |
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146 | .word UART5_IRQHandler /* UART5 */ | |
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147 | .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ | |
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148 | .word TIM7_IRQHandler /* TIM7 */ | |
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149 | .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ | |
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150 | .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ | |
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151 | .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ | |
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152 | .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ | |
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153 | .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ | |
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154 | .word ETH_IRQHandler /* Ethernet */ | |
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155 | .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ | |
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156 | .word CAN2_TX_IRQHandler /* CAN2 TX */ | |
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157 | .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ | |
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158 | .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ | |
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159 | .word CAN2_SCE_IRQHandler /* CAN2 SCE */ | |
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160 | .word OTG_FS_IRQHandler /* USB OTG FS */ | |
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161 | .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ | |
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162 | .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ | |
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163 | .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ | |
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164 | .word USART6_IRQHandler /* USART6 */ | |
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165 | .word I2C3_EV_IRQHandler /* I2C3 event */ | |
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166 | .word I2C3_ER_IRQHandler /* I2C3 error */ | |
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167 | .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ | |
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168 | .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ | |
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169 | .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ | |
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170 | .word OTG_HS_IRQHandler /* USB OTG HS */ | |
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171 | .word DCMI_IRQHandler /* DCMI */ | |
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172 | .word CRYP_IRQHandler /* CRYP crypto */ | |
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173 | .word HASH_RNG_IRQHandler /* Hash and Rng */ | |
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174 | .word FPU_IRQHandler /* FPU */ | |
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175 | ||
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176 | /******************************************************************************* | |
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177 | * | |
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178 | * Provide weak aliases for each Exception handler to the Default_Handler. | |
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179 | * As they are weak aliases, any function with the same name will override | |
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180 | * this definition. | |
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181 | * | |
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182 | *******************************************************************************/ | |
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183 | .weak NMI_Handler | |
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184 | .thumb_set NMI_Handler,Default_Handler | |
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185 | ||
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186 | .weak HardFault_Handler | |
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187 | .thumb_set HardFault_Handler,Default_Handler | |
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188 | ||
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189 | .weak MemManage_Handler | |
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190 | .thumb_set MemManage_Handler,Default_Handler | |
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191 | ||
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192 | .weak BusFault_Handler | |
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193 | .thumb_set BusFault_Handler,Default_Handler | |
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194 | ||
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195 | .weak UsageFault_Handler | |
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196 | .thumb_set UsageFault_Handler,Default_Handler | |
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197 | ||
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198 | .weak SVC_Handler | |
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199 | .thumb_set SVC_Handler,Default_Handler | |
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200 | ||
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201 | .weak DebugMon_Handler | |
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202 | .thumb_set DebugMon_Handler,Default_Handler | |
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203 | ||
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204 | .weak PendSV_Handler | |
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205 | .thumb_set PendSV_Handler,Default_Handler | |
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206 | ||
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207 | .weak SysTick_Handler | |
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208 | .thumb_set SysTick_Handler,Default_Handler | |
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209 | ||
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210 | .weak WWDG_IRQHandler | |
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211 | .thumb_set WWDG_IRQHandler,Default_Handler | |
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212 | ||
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213 | .weak PVD_IRQHandler | |
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214 | .thumb_set PVD_IRQHandler,Default_Handler | |
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215 | ||
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216 | .weak TAMP_STAMP_IRQHandler | |
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217 | .thumb_set TAMP_STAMP_IRQHandler,Default_Handler | |
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218 | ||
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219 | .weak RTC_WKUP_IRQHandler | |
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220 | .thumb_set RTC_WKUP_IRQHandler,Default_Handler | |
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221 | ||
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222 | .weak FLASH_IRQHandler | |
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223 | .thumb_set FLASH_IRQHandler,Default_Handler | |
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224 | ||
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225 | .weak RCC_IRQHandler | |
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226 | .thumb_set RCC_IRQHandler,Default_Handler | |
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227 | ||
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228 | .weak EXTI0_IRQHandler | |
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229 | .thumb_set EXTI0_IRQHandler,Default_Handler | |
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230 | ||
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231 | .weak EXTI1_IRQHandler | |
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232 | .thumb_set EXTI1_IRQHandler,Default_Handler | |
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233 | ||
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234 | .weak EXTI2_IRQHandler | |
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235 | .thumb_set EXTI2_IRQHandler,Default_Handler | |
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236 | ||
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237 | .weak EXTI3_IRQHandler | |
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238 | .thumb_set EXTI3_IRQHandler,Default_Handler | |
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239 | ||
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240 | .weak EXTI4_IRQHandler | |
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241 | .thumb_set EXTI4_IRQHandler,Default_Handler | |
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242 | ||
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243 | .weak DMA1_Stream0_IRQHandler | |
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244 | .thumb_set DMA1_Stream0_IRQHandler,Default_Handler | |
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245 | ||
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246 | .weak DMA1_Stream1_IRQHandler | |
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247 | .thumb_set DMA1_Stream1_IRQHandler,Default_Handler | |
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248 | ||
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249 | .weak DMA1_Stream2_IRQHandler | |
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250 | .thumb_set DMA1_Stream2_IRQHandler,Default_Handler | |
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251 | ||
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252 | .weak DMA1_Stream3_IRQHandler | |
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253 | .thumb_set DMA1_Stream3_IRQHandler,Default_Handler | |
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254 | ||
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255 | .weak DMA1_Stream4_IRQHandler | |
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256 | .thumb_set DMA1_Stream4_IRQHandler,Default_Handler | |
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257 | ||
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258 | .weak DMA1_Stream5_IRQHandler | |
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259 | .thumb_set DMA1_Stream5_IRQHandler,Default_Handler | |
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260 | ||
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261 | .weak DMA1_Stream6_IRQHandler | |
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262 | .thumb_set DMA1_Stream6_IRQHandler,Default_Handler | |
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263 | ||
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264 | .weak ADC_IRQHandler | |
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265 | .thumb_set ADC_IRQHandler,Default_Handler | |
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266 | ||
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267 | .weak CAN1_TX_IRQHandler | |
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268 | .thumb_set CAN1_TX_IRQHandler,Default_Handler | |
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269 | ||
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270 | .weak CAN1_RX0_IRQHandler | |
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271 | .thumb_set CAN1_RX0_IRQHandler,Default_Handler | |
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272 | ||
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273 | .weak CAN1_RX1_IRQHandler | |
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274 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler | |
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275 | ||
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276 | .weak CAN1_SCE_IRQHandler | |
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277 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler | |
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278 | ||
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279 | .weak EXTI9_5_IRQHandler | |
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280 | .thumb_set EXTI9_5_IRQHandler,Default_Handler | |
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281 | ||
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282 | .weak TIM1_BRK_TIM9_IRQHandler | |
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283 | .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler | |
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284 | ||
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285 | .weak TIM1_UP_TIM10_IRQHandler | |
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286 | .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler | |
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287 | ||
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288 | .weak TIM1_TRG_COM_TIM11_IRQHandler | |
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289 | .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler | |
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290 | ||
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291 | .weak TIM1_CC_IRQHandler | |
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292 | .thumb_set TIM1_CC_IRQHandler,Default_Handler | |
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293 | ||
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294 | .weak TIM2_IRQHandler | |
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295 | .thumb_set TIM2_IRQHandler,Default_Handler | |
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296 | ||
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297 | .weak TIM3_IRQHandler | |
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298 | .thumb_set TIM3_IRQHandler,Default_Handler | |
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299 | ||
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300 | .weak TIM4_IRQHandler | |
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301 | .thumb_set TIM4_IRQHandler,Default_Handler | |
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302 | ||
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303 | .weak I2C1_EV_IRQHandler | |
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304 | .thumb_set I2C1_EV_IRQHandler,Default_Handler | |
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305 | ||
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306 | .weak I2C1_ER_IRQHandler | |
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307 | .thumb_set I2C1_ER_IRQHandler,Default_Handler | |
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308 | ||
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309 | .weak I2C2_EV_IRQHandler | |
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310 | .thumb_set I2C2_EV_IRQHandler,Default_Handler | |
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311 | ||
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312 | .weak I2C2_ER_IRQHandler | |
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313 | .thumb_set I2C2_ER_IRQHandler,Default_Handler | |
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314 | ||
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315 | .weak SPI1_IRQHandler | |
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316 | .thumb_set SPI1_IRQHandler,Default_Handler | |
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317 | ||
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318 | .weak SPI2_IRQHandler | |
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319 | .thumb_set SPI2_IRQHandler,Default_Handler | |
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320 | ||
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321 | .weak USART1_IRQHandler | |
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322 | .thumb_set USART1_IRQHandler,Default_Handler | |
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323 | ||
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324 | .weak USART2_IRQHandler | |
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325 | .thumb_set USART2_IRQHandler,Default_Handler | |
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326 | ||
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327 | .weak USART3_IRQHandler | |
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328 | .thumb_set USART3_IRQHandler,Default_Handler | |
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329 | ||
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330 | .weak EXTI15_10_IRQHandler | |
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331 | .thumb_set EXTI15_10_IRQHandler,Default_Handler | |
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332 | ||
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333 | .weak RTC_Alarm_IRQHandler | |
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334 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler | |
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335 | ||
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336 | .weak OTG_FS_WKUP_IRQHandler | |
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337 | .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler | |
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338 | ||
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339 | .weak TIM8_BRK_TIM12_IRQHandler | |
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340 | .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler | |
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341 | ||
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342 | .weak TIM8_UP_TIM13_IRQHandler | |
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343 | .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler | |
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344 | ||
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345 | .weak TIM8_TRG_COM_TIM14_IRQHandler | |
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346 | .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler | |
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347 | ||
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348 | .weak TIM8_CC_IRQHandler | |
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349 | .thumb_set TIM8_CC_IRQHandler,Default_Handler | |
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350 | ||
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351 | .weak DMA1_Stream7_IRQHandler | |
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352 | .thumb_set DMA1_Stream7_IRQHandler,Default_Handler | |
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353 | ||
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354 | .weak FSMC_IRQHandler | |
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355 | .thumb_set FSMC_IRQHandler,Default_Handler | |
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356 | ||
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357 | .weak SDIO_IRQHandler | |
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358 | .thumb_set SDIO_IRQHandler,Default_Handler | |
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359 | ||
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360 | .weak TIM5_IRQHandler | |
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361 | .thumb_set TIM5_IRQHandler,Default_Handler | |
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362 | ||
|
363 | .weak SPI3_IRQHandler | |
|
364 | .thumb_set SPI3_IRQHandler,Default_Handler | |
|
365 | ||
|
366 | .weak UART4_IRQHandler | |
|
367 | .thumb_set UART4_IRQHandler,Default_Handler | |
|
368 | ||
|
369 | .weak UART5_IRQHandler | |
|
370 | .thumb_set UART5_IRQHandler,Default_Handler | |
|
371 | ||
|
372 | .weak TIM6_DAC_IRQHandler | |
|
373 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler | |
|
374 | ||
|
375 | .weak TIM7_IRQHandler | |
|
376 | .thumb_set TIM7_IRQHandler,Default_Handler | |
|
377 | ||
|
378 | .weak DMA2_Stream0_IRQHandler | |
|
379 | .thumb_set DMA2_Stream0_IRQHandler,Default_Handler | |
|
380 | ||
|
381 | .weak DMA2_Stream1_IRQHandler | |
|
382 | .thumb_set DMA2_Stream1_IRQHandler,Default_Handler | |
|
383 | ||
|
384 | .weak DMA2_Stream2_IRQHandler | |
|
385 | .thumb_set DMA2_Stream2_IRQHandler,Default_Handler | |
|
386 | ||
|
387 | .weak DMA2_Stream3_IRQHandler | |
|
388 | .thumb_set DMA2_Stream3_IRQHandler,Default_Handler | |
|
389 | ||
|
390 | .weak DMA2_Stream4_IRQHandler | |
|
391 | .thumb_set DMA2_Stream4_IRQHandler,Default_Handler | |
|
392 | ||
|
393 | .weak ETH_IRQHandler | |
|
394 | .thumb_set ETH_IRQHandler,Default_Handler | |
|
395 | ||
|
396 | .weak ETH_WKUP_IRQHandler | |
|
397 | .thumb_set ETH_WKUP_IRQHandler,Default_Handler | |
|
398 | ||
|
399 | .weak CAN2_TX_IRQHandler | |
|
400 | .thumb_set CAN2_TX_IRQHandler,Default_Handler | |
|
401 | ||
|
402 | .weak CAN2_RX0_IRQHandler | |
|
403 | .thumb_set CAN2_RX0_IRQHandler,Default_Handler | |
|
404 | ||
|
405 | .weak CAN2_RX1_IRQHandler | |
|
406 | .thumb_set CAN2_RX1_IRQHandler,Default_Handler | |
|
407 | ||
|
408 | .weak CAN2_SCE_IRQHandler | |
|
409 | .thumb_set CAN2_SCE_IRQHandler,Default_Handler | |
|
410 | ||
|
411 | .weak OTG_FS_IRQHandler | |
|
412 | .thumb_set OTG_FS_IRQHandler,Default_Handler | |
|
413 | ||
|
414 | .weak DMA2_Stream5_IRQHandler | |
|
415 | .thumb_set DMA2_Stream5_IRQHandler,Default_Handler | |
|
416 | ||
|
417 | .weak DMA2_Stream6_IRQHandler | |
|
418 | .thumb_set DMA2_Stream6_IRQHandler,Default_Handler | |
|
419 | ||
|
420 | .weak DMA2_Stream7_IRQHandler | |
|
421 | .thumb_set DMA2_Stream7_IRQHandler,Default_Handler | |
|
422 | ||
|
423 | .weak USART6_IRQHandler | |
|
424 | .thumb_set USART6_IRQHandler,Default_Handler | |
|
425 | ||
|
426 | .weak I2C3_EV_IRQHandler | |
|
427 | .thumb_set I2C3_EV_IRQHandler,Default_Handler | |
|
428 | ||
|
429 | .weak I2C3_ER_IRQHandler | |
|
430 | .thumb_set I2C3_ER_IRQHandler,Default_Handler | |
|
431 | ||
|
432 | .weak OTG_HS_EP1_OUT_IRQHandler | |
|
433 | .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler | |
|
434 | ||
|
435 | .weak OTG_HS_EP1_IN_IRQHandler | |
|
436 | .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler | |
|
437 | ||
|
438 | .weak OTG_HS_WKUP_IRQHandler | |
|
439 | .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler | |
|
440 | ||
|
441 | .weak OTG_HS_IRQHandler | |
|
442 | .thumb_set OTG_HS_IRQHandler,Default_Handler | |
|
443 | ||
|
444 | .weak DCMI_IRQHandler | |
|
445 | .thumb_set DCMI_IRQHandler,Default_Handler | |
|
446 | ||
|
447 | .weak CRYP_IRQHandler | |
|
448 | .thumb_set CRYP_IRQHandler,Default_Handler | |
|
449 | ||
|
450 | .weak HASH_RNG_IRQHandler | |
|
451 | .thumb_set HASH_RNG_IRQHandler,Default_Handler | |
|
452 | ||
|
453 | .weak FPU_IRQHandler | |
|
454 | .thumb_set FPU_IRQHandler,Default_Handler |
@@ -0,0 +1,171 | |||
|
1 | /* | |
|
2 | ***************************************************************************** | |
|
3 | ** | |
|
4 | ** File : stm32_flash.ld | |
|
5 | ** | |
|
6 | ** Abstract : Linker script for STM32F407VG Device with | |
|
7 | ** 1024KByte FLASH, 192KByte RAM | |
|
8 | ** | |
|
9 | ** Set heap size, stack size and stack location according | |
|
10 | ** to application requirements. | |
|
11 | ** | |
|
12 | ** Set memory bank area and size if external memory is used. | |
|
13 | ** | |
|
14 | ** Target : STMicroelectronics STM32 | |
|
15 | ** | |
|
16 | ** Environment : Atollic TrueSTUDIO(R) | |
|
17 | ** | |
|
18 | ** Distribution: The file is distributed οΏ½as is,οΏ½ without any warranty | |
|
19 | ** of any kind. | |
|
20 | ** | |
|
21 | ** (c)Copyright Atollic AB. | |
|
22 | ** You may use this file as-is or modify it according to the needs of your | |
|
23 | ** project. Distribution of this file (unmodified or modified) is not | |
|
24 | ** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the | |
|
25 | ** rights to distribute the assembled, compiled & linked contents of this | |
|
26 | ** file as part of an application binary file, provided that it is built | |
|
27 | ** using the Atollic TrueSTUDIO(R) toolchain. | |
|
28 | ** | |
|
29 | ***************************************************************************** | |
|
30 | */ | |
|
31 | ||
|
32 | /* Entry Point */ | |
|
33 | ENTRY(Reset_Handler) | |
|
34 | ||
|
35 | /* Highest address of the user mode stack */ | |
|
36 | _estack = 0x20020000; /* end of 128K RAM on AHB bus*/ | |
|
37 | ||
|
38 | /* Generate a link error if heap and stack don't fit into RAM */ | |
|
39 | _Min_Heap_Size = 0; /* required amount of heap */ | |
|
40 | _Min_Stack_Size = 0x1000; /* required amount of stack */ | |
|
41 | ||
|
42 | /* Specify the memory areas */ | |
|
43 | MEMORY | |
|
44 | { | |
|
45 | FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024k | |
|
46 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 112k | |
|
47 | CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 64k | |
|
48 | MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K | |
|
49 | } | |
|
50 | ||
|
51 | /* Define output sections */ | |
|
52 | SECTIONS | |
|
53 | { | |
|
54 | /* The startup code goes first into FLASH */ | |
|
55 | .isr_vector : | |
|
56 | { | |
|
57 | . = ALIGN(4); | |
|
58 | KEEP(*(.isr_vector)) /* Startup code */ | |
|
59 | . = ALIGN(4); | |
|
60 | } >FLASH | |
|
61 | ||
|
62 | /* The program code and other data goes into FLASH */ | |
|
63 | .text : | |
|
64 | { | |
|
65 | . = ALIGN(4); | |
|
66 | *(.text) /* .text sections (code) */ | |
|
67 | *(.text*) /* .text* sections (code) */ | |
|
68 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ | |
|
69 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ | |
|
70 | *(.glue_7) /* glue arm to thumb code */ | |
|
71 | *(.glue_7t) /* glue thumb to arm code */ | |
|
72 | *(.eh_frame) | |
|
73 | ||
|
74 | KEEP (*(.init)) | |
|
75 | KEEP (*(.fini)) | |
|
76 | ||
|
77 | . = ALIGN(4); | |
|
78 | _etext = .; /* define a global symbols at end of code */ | |
|
79 | } >FLASH | |
|
80 | ||
|
81 | ||
|
82 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH | |
|
83 | .ARM : { | |
|
84 | __exidx_start = .; | |
|
85 | *(.ARM.exidx*) | |
|
86 | __exidx_end = .; | |
|
87 | } >FLASH | |
|
88 | ||
|
89 | .preinit_array : | |
|
90 | { | |
|
91 | PROVIDE_HIDDEN (__preinit_array_start = .); | |
|
92 | KEEP (*(.preinit_array*)) | |
|
93 | PROVIDE_HIDDEN (__preinit_array_end = .); | |
|
94 | } >FLASH | |
|
95 | .init_array : | |
|
96 | { | |
|
97 | PROVIDE_HIDDEN (__init_array_start = .); | |
|
98 | KEEP (*(SORT(.init_array.*))) | |
|
99 | KEEP (*(.init_array*)) | |
|
100 | PROVIDE_HIDDEN (__init_array_end = .); | |
|
101 | } >FLASH | |
|
102 | .fini_array : | |
|
103 | { | |
|
104 | PROVIDE_HIDDEN (__fini_array_start = .); | |
|
105 | KEEP (*(.fini_array*)) | |
|
106 | KEEP (*(SORT(.fini_array.*))) | |
|
107 | PROVIDE_HIDDEN (__fini_array_end = .); | |
|
108 | } >FLASH | |
|
109 | ||
|
110 | /* used by the startup to initialize data */ | |
|
111 | _sidata = .; | |
|
112 | ||
|
113 | /* Initialized data sections goes into RAM, load LMA copy after code */ | |
|
114 | .data : AT ( _sidata ) | |
|
115 | { | |
|
116 | . = ALIGN(4); | |
|
117 | _sdata = .; /* create a global symbol at data start */ | |
|
118 | *(.data) /* .data sections */ | |
|
119 | *(.data*) /* .data* sections */ | |
|
120 | ||
|
121 | . = ALIGN(4); | |
|
122 | _edata = .; /* define a global symbol at data end */ | |
|
123 | } >RAM | |
|
124 | ||
|
125 | /* Uninitialized data section */ | |
|
126 | . = ALIGN(4); | |
|
127 | .bss : | |
|
128 | { | |
|
129 | /* This is used by the startup in order to initialize the .bss secion */ | |
|
130 | _sbss = .; /* define a global symbol at bss start */ | |
|
131 | __bss_start__ = _sbss; | |
|
132 | *(.bss) | |
|
133 | *(.bss*) | |
|
134 | *(COMMON) | |
|
135 | ||
|
136 | . = ALIGN(4); | |
|
137 | _ebss = .; /* define a global symbol at bss end */ | |
|
138 | __bss_end__ = _ebss; | |
|
139 | } >RAM | |
|
140 | ||
|
141 | /* User_heap_stack section, used to check that there is enough RAM left */ | |
|
142 | ._user_heap_stack : | |
|
143 | { | |
|
144 | . = ALIGN(4); | |
|
145 | PROVIDE ( end = . ); | |
|
146 | PROVIDE ( _end = . ); | |
|
147 | . = . + _Min_Heap_Size; | |
|
148 | . = . + _Min_Stack_Size; | |
|
149 | . = ALIGN(4); | |
|
150 | } >RAM | |
|
151 | ||
|
152 | /* MEMORY_bank1 section, code must be located here explicitly */ | |
|
153 | /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ | |
|
154 | .memory_b1_text : | |
|
155 | { | |
|
156 | *(.mb1text) /* .mb1text sections (code) */ | |
|
157 | *(.mb1text*) /* .mb1text* sections (code) */ | |
|
158 | *(.mb1rodata) /* read-only data (constants) */ | |
|
159 | *(.mb1rodata*) | |
|
160 | } >MEMORY_B1 | |
|
161 | ||
|
162 | /* Remove information from the standard libraries */ | |
|
163 | /DISCARD/ : | |
|
164 | { | |
|
165 | libc.a ( * ) | |
|
166 | libm.a ( * ) | |
|
167 | libgcc.a ( * ) | |
|
168 | } | |
|
169 | ||
|
170 | .ARM.attributes 0 : { *(.ARM.attributes) } | |
|
171 | } |
@@ -0,0 +1,261 | |||
|
1 | #include <stdlib.h> | |
|
2 | #include <errno.h> | |
|
3 | #include <string.h> | |
|
4 | #include <sys/stat.h> | |
|
5 | #include <sys/types.h> | |
|
6 | #include <sys/times.h> | |
|
7 | #include <streamdevices.h> | |
|
8 | #include <string.h> | |
|
9 | #include <stdio.h> | |
|
10 | #include <gpio.h> | |
|
11 | #include <uart.h> | |
|
12 | #include <stdint.h> | |
|
13 | ||
|
14 | #undef errno | |
|
15 | ||
|
16 | ||
|
17 | ||
|
18 | #ifdef __cplusplus | |
|
19 | extern "C" { | |
|
20 | #endif | |
|
21 | extern int errno; | |
|
22 | extern int32_t __max_opened_files__; | |
|
23 | extern streamdevice* __opnfiles__[]; | |
|
24 | extern int32_t* __fs_root__; | |
|
25 | extern int32_t __fs_root_size__; | |
|
26 | ||
|
27 | char *__env[1] = { 0 }; | |
|
28 | char **environ = __env; | |
|
29 | ||
|
30 | int _exit() | |
|
31 | { | |
|
32 | while(1); | |
|
33 | } | |
|
34 | ||
|
35 | int _close(int file) | |
|
36 | { | |
|
37 | if(file<__max_opened_files__ && __opnfiles__[file]!=NULL) | |
|
38 | { | |
|
39 | return __opnfiles__[file]->ops->close( __opnfiles__[file]); | |
|
40 | } | |
|
41 | return 0; | |
|
42 | } | |
|
43 | ||
|
44 | ||
|
45 | int _write(int file, char *ptr, int len) | |
|
46 | { | |
|
47 | if(file<__max_opened_files__ && __opnfiles__[file]!=NULL) | |
|
48 | { | |
|
49 | if(__opnfiles__[file]->ops->write(__opnfiles__[file],ptr,1,len)) return len; | |
|
50 | } | |
|
51 | return 0; | |
|
52 | } | |
|
53 | ||
|
54 | int _execve(char *name, char **argv, char **env) { | |
|
55 | errno = ENOMEM; | |
|
56 | return -1; | |
|
57 | } | |
|
58 | ||
|
59 | ||
|
60 | int _fork(void) { | |
|
61 | errno = EAGAIN; | |
|
62 | return -1; | |
|
63 | } | |
|
64 | ||
|
65 | int _fstat(int file, struct stat *st) { | |
|
66 | st->st_mode = S_IFCHR; | |
|
67 | return 0; | |
|
68 | } | |
|
69 | ||
|
70 | ||
|
71 | int _getpid(void) { | |
|
72 | return 1; | |
|
73 | } | |
|
74 | ||
|
75 | ||
|
76 | int _isatty(int file) { | |
|
77 | return 1; | |
|
78 | } | |
|
79 | ||
|
80 | ||
|
81 | int _kill(int pid, int sig) { | |
|
82 | errno = EINVAL; | |
|
83 | return -1; | |
|
84 | } | |
|
85 | ||
|
86 | ||
|
87 | int _link(char *old, char *_new) { | |
|
88 | errno = EMLINK; | |
|
89 | return -1; | |
|
90 | } | |
|
91 | ||
|
92 | ||
|
93 | int _lseek(int file, int ptr, int dir) { | |
|
94 | return 0; | |
|
95 | } | |
|
96 | ||
|
97 | #include <gpio.h> | |
|
98 | ||
|
99 | int _open(const char *name, int flags, int mode) | |
|
100 | { | |
|
101 | if(!strncmp("UART", name, 4) && ((name[4] & 0x30)==0x30)) | |
|
102 | { | |
|
103 | //uart_t* uart1 = malloc(sizeof(uart_t)); | |
|
104 | streamdevice* fd1 = malloc(sizeof(streamdevice)); | |
|
105 | uart_t uart=uartopen((name[4] & 0xF)-1); | |
|
106 | if(uart!=-1); | |
|
107 | { | |
|
108 | uartmkstreamdev(uart,fd1); | |
|
109 | int i=2; | |
|
110 | while((i<__max_opened_files__) && (__opnfiles__[i]!=NULL))i++; | |
|
111 | if(i!=__max_opened_files__) | |
|
112 | { | |
|
113 | __opnfiles__[i] = fd1; | |
|
114 | return i; | |
|
115 | } | |
|
116 | else printf("Too much files opened\n\r"); | |
|
117 | } | |
|
118 | } | |
|
119 | return -1; | |
|
120 | } | |
|
121 | ||
|
122 | int _read(int file, char *ptr, int len) { | |
|
123 | if(file<__max_opened_files__ && __opnfiles__[file]!=NULL) | |
|
124 | { | |
|
125 | if(__opnfiles__[file]->ops->read(__opnfiles__[file],ptr,1,len)) return len; | |
|
126 | } | |
|
127 | return 0; | |
|
128 | } | |
|
129 | ||
|
130 | ||
|
131 | ||
|
132 | caddr_t _sbrk(int incr) { | |
|
133 | register char * stack_ptr __asm__ ("sp"); | |
|
134 | extern char _end; /* Defined by the linker */ | |
|
135 | static char *heap_end; | |
|
136 | char *prev_heap_end; | |
|
137 | if (heap_end == 0) { | |
|
138 | heap_end = &_end; | |
|
139 | } | |
|
140 | prev_heap_end = heap_end; | |
|
141 | if (heap_end + incr > stack_ptr) { | |
|
142 | _write (1, "Heap and stack collision\n", 25); | |
|
143 | abort (); | |
|
144 | } | |
|
145 | heap_end += incr; | |
|
146 | return (caddr_t) prev_heap_end; | |
|
147 | } | |
|
148 | ||
|
149 | ||
|
150 | ||
|
151 | int _stat(char *file, struct stat *st) { | |
|
152 | st->st_mode = S_IFCHR; | |
|
153 | return 0; | |
|
154 | } | |
|
155 | ||
|
156 | ||
|
157 | int _times(struct tms *buf) { | |
|
158 | return -1; | |
|
159 | } | |
|
160 | ||
|
161 | ||
|
162 | int _unlink(char *name) { | |
|
163 | errno = ENOENT; | |
|
164 | return -1; | |
|
165 | } | |
|
166 | ||
|
167 | int _wait(int *status) { | |
|
168 | errno = ECHILD; | |
|
169 | return -1; | |
|
170 | } | |
|
171 | ||
|
172 | ||
|
173 | int _read_r (struct _reent *r, int file, char * ptr, int len) | |
|
174 | { | |
|
175 | r = r; | |
|
176 | file = file; | |
|
177 | ptr = ptr; | |
|
178 | len = len; | |
|
179 | _read(file,ptr,len); | |
|
180 | errno = EINVAL; | |
|
181 | return -1; | |
|
182 | } | |
|
183 | ||
|
184 | /***************************************************************************/ | |
|
185 | ||
|
186 | int _lseek_r (struct _reent *r, int file, int ptr, int dir) | |
|
187 | { | |
|
188 | r = r; | |
|
189 | file = file; | |
|
190 | ptr = ptr; | |
|
191 | dir = dir; | |
|
192 | ||
|
193 | return 0; | |
|
194 | } | |
|
195 | ||
|
196 | /***************************************************************************/ | |
|
197 | ||
|
198 | int _write_r (struct _reent *r, int file, char * ptr, int len) | |
|
199 | { | |
|
200 | return _write(file, ptr, len); | |
|
201 | } | |
|
202 | ||
|
203 | /***************************************************************************/ | |
|
204 | ||
|
205 | int _close_r (struct _reent *r, int file) | |
|
206 | { | |
|
207 | return 0; | |
|
208 | } | |
|
209 | ||
|
210 | /***************************************************************************/ | |
|
211 | ||
|
212 | caddr_t _sbrk_r (struct _reent *r, int incr) | |
|
213 | { | |
|
214 | register char * stack_ptr __asm__ ("sp"); | |
|
215 | extern char _end; /* Defined by the linker */ | |
|
216 | static char *heap_end; | |
|
217 | char *prev_heap_end; | |
|
218 | if (heap_end == 0) { | |
|
219 | heap_end = &_end; | |
|
220 | } | |
|
221 | prev_heap_end = heap_end; | |
|
222 | if (heap_end + incr > stack_ptr) { | |
|
223 | _write (1, "Heap and stack collision\n", 25); | |
|
224 | abort (); | |
|
225 | } | |
|
226 | heap_end += incr; | |
|
227 | return (caddr_t) prev_heap_end; | |
|
228 | } | |
|
229 | ||
|
230 | /***************************************************************************/ | |
|
231 | ||
|
232 | int _fstat_r (struct _reent *r, int file, struct stat * st) | |
|
233 | { | |
|
234 | r = r; | |
|
235 | file = file; | |
|
236 | ||
|
237 | memset (st, 0, sizeof (* st)); | |
|
238 | st->st_mode = S_IFCHR; | |
|
239 | return 0; | |
|
240 | } | |
|
241 | ||
|
242 | /***************************************************************************/ | |
|
243 | int _open_r(struct _reent *r,const char *name, int flags, int mode) | |
|
244 | { | |
|
245 | return _open(name, flags, mode); | |
|
246 | } | |
|
247 | ||
|
248 | int _isatty_r(struct _reent *r, int fd) | |
|
249 | { | |
|
250 | r = r; | |
|
251 | fd = fd; | |
|
252 | ||
|
253 | return 1; | |
|
254 | } | |
|
255 | ||
|
256 | ||
|
257 | #ifdef __cplusplus | |
|
258 | } | |
|
259 | #endif | |
|
260 | ||
|
261 |
@@ -1,13 +1,13 | |||
|
1 | 1 | |
|
2 | 2 | INCLUDEPATH += $$[QT_INSTALL_HEADERS] \ |
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3 | 3 | $$[QT_INSTALL_HEADERS]/GRAPHIC/CONTROLERS \ |
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4 | 4 | $$[QT_INSTALL_HEADERS]/GRAPHIC/GUI/FONTS \ |
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5 | 5 | $$[QT_INSTALL_HEADERS]/GRAPHIC/GUI/Widgets \ |
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6 | 6 | $$[QT_INSTALL_HEADERS]/$$ARCH |
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7 | 7 | |
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8 | 8 | |
|
9 | LIBS += -L$$[QT_INSTALL_LIBS]/$$ARCH -lCS43L22 -lina226 -lili9328 -lfonts -lsdcard -lfat32 -lmbr -luart -li2c -lgpio -lspi -lcpu -lcore -lm | |
|
9 | LIBS += -L$$[QT_INSTALL_LIBS]/$$ARCH -lterminal -lCS43L22 -lina226 -lili9328 -lfonts -lsdcard -lfat32 -lmbr -luart -li2c -lgpio -lspi -lcpu -lcore -lm | |
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10 | 10 | |
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11 | 11 | |
|
12 | 12 | |
|
13 | 13 |
@@ -1,7 +1,6 | |||
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1 | 1 | CPU=stm32f4xxxG |
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2 | 2 | DEFINES+=BSP=\\\"BEAGLESYNTH\\\" |
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3 | 3 | beagleCp.target = beagleCp |
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4 | 4 | beagleCp.commands = scp $$DESTDIR/$(QMAKE_TARGET).bin root@192.168.7.2://opt/stm32flashAje/hello.bin |
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5 | 5 | QMAKE_EXTRA_TARGETS += beagleCp |
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6 | ||
|
7 | include(../../../stm32f4/qmake.conf) | |
|
6 | UCMODEL=stm32f4 |
@@ -1,4 +1,3 | |||
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1 | 1 | CPU=stm32f4xxxG |
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2 | 2 | DEFINES+=BSP=\\\"M4Stick\\\" |
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3 | ||
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4 | include(../../../stm32f4/qmake.conf) | |
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3 | UCMODEL=stm32f4 |
@@ -1,4 +1,7 | |||
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1 | 1 | CPU=stm32f4xxxG |
|
2 | DEFINES+=BSP=\\\"M4Stick\\\" | |
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3 | ||
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4 | include(../../../stm32f4/qmake.conf) | |
|
2 | DEFINES+=BSP=\\\"M4StickV2\\\" | |
|
3 | #CONFIG += USB | |
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4 | USB += cdc | |
|
5 | DEFINES+= USE_USB_OTG_FS | |
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6 | DEFINES+=stm32f4 | |
|
7 | UCMODEL=stm32f4 |
@@ -1,4 +1,3 | |||
|
1 | 1 | CPU=stm32f4xxxG |
|
2 | 2 | DEFINES+=BSP=\\\"SOLAR_LFR_PSU\\\" |
|
3 | ||
|
4 | include(../../../stm32f4/qmake.conf) | |
|
3 | UCMODEL=stm32f4 |
@@ -1,4 +1,3 | |||
|
1 | 1 | CPU=stm32f4xxxG |
|
2 | 2 | DEFINES+=BSP=\\\"SOLAR_LFR_PSU\\\" |
|
3 | ||
|
4 | include(../../../stm32f4/qmake.conf) | |
|
3 | UCMODEL=stm32f4 |
@@ -1,6 +1,3 | |||
|
1 | 1 | CPU=stm32f4xxxG |
|
2 | 2 | DEFINES+=BSP=\\\"STM32F4Eval\\\" |
|
3 | ||
|
4 | include(../../../stm32f4/qmake.conf) | |
|
5 | ||
|
6 | ||
|
3 | UCMODEL=stm32f4 |
@@ -1,75 +1,73 | |||
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1 | 1 | # |
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2 | 2 | # qmake configuration for stm32f4 |
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3 | 3 | # |
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4 | 4 | # |
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5 | 5 | |
|
6 | 6 | |
|
7 | 7 | isEmpty(_stm32f4_conf){ |
|
8 | 8 | _stm32f4_conf="oneshot" |
|
9 | 9 | |
|
10 | 10 | QMAKE_CFLAGS=-mlittle-endian -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -std=c99 |
|
11 | 11 | |
|
12 | 12 | include(../common/arm-none-eabi.conf) |
|
13 | 13 | |
|
14 | 14 | DEFINES += __OPTIMIZED_MATH |
|
15 | 15 | DEFINES += \"assert_param(expr)=((void)0)\" |
|
16 | 16 | INCLUDEPATH += $$PWD |
|
17 | 17 | |
|
18 | 18 | DEFINES += __FPU_PRESENT=1 |
|
19 | 19 | DEFINES += ARM_MATH_CM4 |
|
20 | 20 | |
|
21 | 21 | DEFINES += BSP="\"\\\"$$BSP"\\\"\" |
|
22 | 22 | |
|
23 | 23 | CONFIG += cpu |
|
24 | 24 | |
|
25 | 25 | contains( TEMPLATE, app ) { |
|
26 | 26 | OBJECTS_DIR=obj |
|
27 | 27 | DESTDIR=bin |
|
28 | 28 | unix:QMAKE_POST_LINK += arm-none-eabi-objcopy -O ihex "$(TARGET)" $$DESTDIR/"$(QMAKE_TARGET).hex" && arm-none-eabi-objcopy -O binary "$(TARGET)" $$DESTDIR/"$(QMAKE_TARGET).bin && python $$[QT_INSTALL_BINS]/dfu.py -b 0x08000000:"$$DESTDIR/"$(QMAKE_TARGET).bin " $$DESTDIR/"$(QMAKE_TARGET).dfu" |
|
29 | 29 | win32:QMAKE_POST_LINK += arm-none-eabi-objcopy -O ihex "$(DESTDIR_TARGET)" $$DESTDIR/"$(QMAKE_TARGET).hex" && arm-none-eabi-objcopy -O binary "$(DESTDIR_TARGET)" $$DESTDIR/"$(QMAKE_TARGET).bin" |
|
30 | 30 | |
|
31 | 31 | LIBS += -L$$[QT_INSTALL_PREFIX]/bsp/lib/$$BSP |
|
32 | 32 | LIBS += -lbsp |
|
33 | 33 | |
|
34 | 34 | |
|
35 | 35 | QMAKE_LFLAGS= -mlittle-endian -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -std=c99 -T $$[QT_INSTALL_PREFIX]/mkspecs/features/stm32f4/stm32_flash.ld |
|
36 | 36 | |
|
37 | 37 | INCLUDEPATH+= $$[QT_INSTALL_PREFIX]/bsp/includes/$$BSP |
|
38 | 38 | |
|
39 | 39 | SOURCES +=$$[QT_INSTALL_PREFIX]/mkspecs/features/stm32f4/syscalls.c |
|
40 | 40 | SOURCES +=$$[QT_INSTALL_PREFIX]/mkspecs/features/stm32f4/fs.c |
|
41 | 41 | SOURCES +=$$[QT_INSTALL_PREFIX]/mkspecs/features/stm32f4/startup.s |
|
42 | 42 | SOURCES +=$$[QT_INSTALL_PREFIX]/mkspecs/features/stm32f4/cpuinit.c |
|
43 | 43 | |
|
44 | 44 | # OTHER_FILES += $$[QT_INSTALL_PREFIX]/ucfiles/stm32f4/$$CPU/stm32_flash.ld |
|
45 | 45 | |
|
46 | 46 | stflash.target = stflash |
|
47 | 47 | stflash.commands = cd $$DESTDIR && sudo st-flash write $(QMAKE_TARGET).bin 0x08000000 |
|
48 | dfu-util.target = dfu-util | |
|
49 | dfu-util.commands = cd $$DESTDIR && sudo dfu-util -i 0 -a 0 -d 0483:df11 -D $(QMAKE_TARGET).dfu | |
|
50 | QMAKE_EXTRA_TARGETS += stflash dfu-util | |
|
48 | QMAKE_EXTRA_TARGETS += stflash | |
|
51 | 49 | } |
|
52 | 50 | |
|
53 | 51 | contains( TEMPLATE, lib ) { |
|
54 | 52 | CONFIG+=staticlib |
|
55 | 53 | message( "You can only build static library for stm32f4" ) |
|
56 | 54 | } |
|
57 | 55 | |
|
58 | 56 | include(../common/libuc2libs.conf) |
|
59 | 57 | |
|
60 | 58 | } |
|
61 | 59 | |
|
62 | 60 | |
|
63 | 61 | |
|
64 | 62 | |
|
65 | 63 | |
|
66 | 64 | |
|
67 | 65 | |
|
68 | 66 | |
|
69 | 67 | |
|
70 | 68 | |
|
71 | 69 | |
|
72 | 70 | |
|
73 | 71 | |
|
74 | 72 | |
|
75 | 73 |
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