# HG changeset patch # User jeandet # Date 2013-05-29 08:54:57 # Node ID c31e6b955f5b0ace5c9c6b1ac64b6c08eb0b9a5d # Parent e6f450090662990ac9277f802b838431040a7551 mkspec updates diff --git a/mkspecs/common/libuc2libs.conf b/mkspecs/common/libuc2libs.conf --- a/mkspecs/common/libuc2libs.conf +++ b/mkspecs/common/libuc2libs.conf @@ -6,7 +6,7 @@ INCLUDEPATH += $$[QT_INSTALL_HEADERS] \ $$[QT_INSTALL_HEADERS]/$$ARCH -LIBS += -L$$[QT_INSTALL_LIBS]/$$ARCH -lCS43L22 -lina226 -lili9328 -lfonts -lsdcard -lfat32 -lmbr -luart -li2c -lgpio -lspi -lcpu -lcore -lm +LIBS += -L$$[QT_INSTALL_LIBS]/$$ARCH -lterminal -lCS43L22 -lina226 -lili9328 -lfonts -lsdcard -lfat32 -lmbr -luart -li2c -lgpio -lspi -lcpu -lcore -lm diff --git a/mkspecs/features/boards/BEAGLESYNTH/bsp.pri b/mkspecs/features/boards/BEAGLESYNTH/bsp.pri --- a/mkspecs/features/boards/BEAGLESYNTH/bsp.pri +++ b/mkspecs/features/boards/BEAGLESYNTH/bsp.pri @@ -3,5 +3,4 @@ DEFINES+=BSP=\\\"BEAGLESYNTH\\\" beagleCp.target = beagleCp beagleCp.commands = scp $$DESTDIR/$(QMAKE_TARGET).bin root@192.168.7.2://opt/stm32flashAje/hello.bin QMAKE_EXTRA_TARGETS += beagleCp - -include(../../../stm32f4/qmake.conf) +UCMODEL=stm32f4 diff --git a/mkspecs/features/boards/M4Stick/bsp.pri b/mkspecs/features/boards/M4Stick/bsp.pri --- a/mkspecs/features/boards/M4Stick/bsp.pri +++ b/mkspecs/features/boards/M4Stick/bsp.pri @@ -1,4 +1,3 @@ CPU=stm32f4xxxG DEFINES+=BSP=\\\"M4Stick\\\" - -include(../../../stm32f4/qmake.conf) +UCMODEL=stm32f4 diff --git a/mkspecs/features/boards/M4StickV2/bsp.pri b/mkspecs/features/boards/M4StickV2/bsp.pri --- a/mkspecs/features/boards/M4StickV2/bsp.pri +++ b/mkspecs/features/boards/M4StickV2/bsp.pri @@ -1,4 +1,7 @@ CPU=stm32f4xxxG -DEFINES+=BSP=\\\"M4Stick\\\" - -include(../../../stm32f4/qmake.conf) +DEFINES+=BSP=\\\"M4StickV2\\\" +#CONFIG += USB +USB += cdc +DEFINES+= USE_USB_OTG_FS +DEFINES+=stm32f4 +UCMODEL=stm32f4 diff --git a/mkspecs/features/boards/SOLAR_LFR_PSU/bsp.pri b/mkspecs/features/boards/SOLAR_LFR_PSU/bsp.pri --- a/mkspecs/features/boards/SOLAR_LFR_PSU/bsp.pri +++ b/mkspecs/features/boards/SOLAR_LFR_PSU/bsp.pri @@ -1,4 +1,3 @@ CPU=stm32f4xxxG DEFINES+=BSP=\\\"SOLAR_LFR_PSU\\\" - -include(../../../stm32f4/qmake.conf) +UCMODEL=stm32f4 diff --git a/mkspecs/features/boards/STM32F4Discovery/bsp.pri b/mkspecs/features/boards/STM32F4Discovery/bsp.pri --- a/mkspecs/features/boards/STM32F4Discovery/bsp.pri +++ b/mkspecs/features/boards/STM32F4Discovery/bsp.pri @@ -1,4 +1,3 @@ CPU=stm32f4xxxG DEFINES+=BSP=\\\"SOLAR_LFR_PSU\\\" - -include(../../../stm32f4/qmake.conf) +UCMODEL=stm32f4 diff --git a/mkspecs/features/boards/STM32F4Eval/bsp.pri b/mkspecs/features/boards/STM32F4Eval/bsp.pri --- a/mkspecs/features/boards/STM32F4Eval/bsp.pri +++ b/mkspecs/features/boards/STM32F4Eval/bsp.pri @@ -1,6 +1,3 @@ CPU=stm32f4xxxG DEFINES+=BSP=\\\"STM32F4Eval\\\" - -include(../../../stm32f4/qmake.conf) - - +UCMODEL=stm32f4 diff --git a/mkspecs/features/stm32f4/cpu.pri b/mkspecs/features/stm32f4/cpu.pri new file mode 100644 --- /dev/null +++ b/mkspecs/features/stm32f4/cpu.pri @@ -0,0 +1,18 @@ + +INCLUDEPATH += $$[QT_INSTALL_HEADERS]/STM32F4xx_StdPeriph_Driver +INCLUDEPATH += $$[QT_INSTALL_HEADERS]/STM32F4xx_CMSIS + +LIBS += -L$$[QT_INSTALL_LIBS]/$$UCMODEL +LIBS += -lcpu + + + + + + + + + + + + diff --git a/mkspecs/features/stm32f4/cpuinit.c b/mkspecs/features/stm32f4/cpuinit.c new file mode 100644 --- /dev/null +++ b/mkspecs/features/stm32f4/cpuinit.c @@ -0,0 +1,63 @@ +#include "stm32f4xx.h" +#include +#include +#include +#include +#include +#include +extern int main(); + + + +void cpu_init() +{ + extern uint32_t currentCpuFreq; +#ifndef CPUFREQ + #define CPUFREQ (16*1000*1000) +#endif + currentCpuFreq = CPUFREQ; + enable_FPU(); + RCC->CR |= (uint32_t)0x00000001; + FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; + reset_AHB1(); + reset_AHB2(); + reset_APB1(); + reset_APB2(); + RCC->CR |= (uint32_t)0x00000001; + FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; + RCC->CFGR = 0x00000000; + RCC->CIR = 0x00000000; + SCB->VTOR = FLASH_BASE; + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + PWR->CR |= PWR_CR_PMODE; + currentCpuFreq=setCpuFreq(currentCpuFreq); + currentCpuFreq=getCpuFreq(); + configureSysTick(); + bsp_init(); + printf("SysTick Configured to reach 100us period\n\r"); + RCC_ClocksTypeDef RCC_ClocksStatus; + RCC_GetClocksFreq(&RCC_ClocksStatus); + printf("PLL Configured got:\n\r SYS=%uHz\n\r CPU=%uHz\n\r APB1=%uHz\n\r APB2=%uHz\n\r",(unsigned int)RCC_ClocksStatus.SYSCLK_Frequency,(unsigned int)RCC_ClocksStatus.HCLK_Frequency,(unsigned int)RCC_ClocksStatus.PCLK1_Frequency,(unsigned int)RCC_ClocksStatus.PCLK2_Frequency); + printf("Enter Main\n\r"); + int res=main(); + printf("\n\rprogram exited with code "); + printf("%u",res); + printf("\n\r"); + while(1) + { + delay_100us(10000); + gpioset(LED1); + delay_100us(10000); + gpioclr(LED1); + } +} + + + + + + + + + + diff --git a/mkspecs/features/stm32f4/fs.c b/mkspecs/features/stm32f4/fs.c new file mode 100644 --- /dev/null +++ b/mkspecs/features/stm32f4/fs.c @@ -0,0 +1,25 @@ +#include +#include +#include +#include + +const int32_t __max_opened_files__ = __MAX_OPENED_FILES__; +__IO streamdevice* __opnfiles__[__MAX_OPENED_FILES__]; +const int32_t __fs_root_size__ = __FS_ROOT_SIZE__; +int32_t __fs_root__[__FS_ROOT_SIZE__]; + + +/* +void __init_fs() +{ + int i=0; + for(i=0;i<__fs_root_size__;i++) + { + __fs_root__[i]=(int32_t)NULL; + } + for(i=0;i<__max_opened_files__ ;i++) + { + __opnfiles__[i]._stream=NULL; + } +} +*/ diff --git a/mkspecs/features/stm32f4/startup.s b/mkspecs/features/stm32f4/startup.s new file mode 100644 --- /dev/null +++ b/mkspecs/features/stm32f4/startup.s @@ -0,0 +1,454 @@ + + .syntax unified + .cpu cortex-m4 + /*.fpu softvfp*/ + .fpu fpv4-sp-d16 + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + + bl cpu_init + bx lr +.size Reset_Handler, .-Reset_Handler + + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + + + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler diff --git a/mkspecs/features/stm32f4/stm32_flash.ld b/mkspecs/features/stm32f4/stm32_flash.ld new file mode 100644 --- /dev/null +++ b/mkspecs/features/stm32f4/stm32_flash.ld @@ -0,0 +1,171 @@ +/* +***************************************************************************** +** +** File : stm32_flash.ld +** +** Abstract : Linker script for STM32F407VG Device with +** 1024KByte FLASH, 192KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed �as is,� without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the Atollic TrueSTUDIO(R) toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of 128K RAM on AHB bus*/ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024k + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 112k + CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 64k + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/mkspecs/features/stm32f4/syscalls.c b/mkspecs/features/stm32f4/syscalls.c new file mode 100644 --- /dev/null +++ b/mkspecs/features/stm32f4/syscalls.c @@ -0,0 +1,261 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#undef errno + + + +#ifdef __cplusplus +extern "C" { +#endif +extern int errno; +extern int32_t __max_opened_files__; +extern streamdevice* __opnfiles__[]; +extern int32_t* __fs_root__; +extern int32_t __fs_root_size__; + +char *__env[1] = { 0 }; +char **environ = __env; + +int _exit() +{ + while(1); +} + +int _close(int file) +{ + if(file<__max_opened_files__ && __opnfiles__[file]!=NULL) + { + return __opnfiles__[file]->ops->close( __opnfiles__[file]); + } + return 0; +} + + +int _write(int file, char *ptr, int len) +{ + if(file<__max_opened_files__ && __opnfiles__[file]!=NULL) + { + if(__opnfiles__[file]->ops->write(__opnfiles__[file],ptr,1,len)) return len; + } + return 0; +} + +int _execve(char *name, char **argv, char **env) { + errno = ENOMEM; + return -1; +} + + +int _fork(void) { + errno = EAGAIN; + return -1; +} + +int _fstat(int file, struct stat *st) { + st->st_mode = S_IFCHR; + return 0; +} + + +int _getpid(void) { + return 1; +} + + +int _isatty(int file) { + return 1; +} + + +int _kill(int pid, int sig) { + errno = EINVAL; + return -1; +} + + +int _link(char *old, char *_new) { + errno = EMLINK; + return -1; +} + + +int _lseek(int file, int ptr, int dir) { + return 0; +} + +#include + +int _open(const char *name, int flags, int mode) +{ + if(!strncmp("UART", name, 4) && ((name[4] & 0x30)==0x30)) + { + //uart_t* uart1 = malloc(sizeof(uart_t)); + streamdevice* fd1 = malloc(sizeof(streamdevice)); + uart_t uart=uartopen((name[4] & 0xF)-1); + if(uart!=-1); + { + uartmkstreamdev(uart,fd1); + int i=2; + while((i<__max_opened_files__) && (__opnfiles__[i]!=NULL))i++; + if(i!=__max_opened_files__) + { + __opnfiles__[i] = fd1; + return i; + } + else printf("Too much files opened\n\r"); + } + } + return -1; +} + +int _read(int file, char *ptr, int len) { + if(file<__max_opened_files__ && __opnfiles__[file]!=NULL) + { + if(__opnfiles__[file]->ops->read(__opnfiles__[file],ptr,1,len)) return len; + } + return 0; +} + + + +caddr_t _sbrk(int incr) { + register char * stack_ptr __asm__ ("sp"); + extern char _end; /* Defined by the linker */ + static char *heap_end; + char *prev_heap_end; + if (heap_end == 0) { + heap_end = &_end; + } + prev_heap_end = heap_end; + if (heap_end + incr > stack_ptr) { + _write (1, "Heap and stack collision\n", 25); + abort (); + } + heap_end += incr; + return (caddr_t) prev_heap_end; +} + + + +int _stat(char *file, struct stat *st) { + st->st_mode = S_IFCHR; + return 0; +} + + +int _times(struct tms *buf) { + return -1; +} + + +int _unlink(char *name) { + errno = ENOENT; + return -1; +} + +int _wait(int *status) { + errno = ECHILD; + return -1; +} + + +int _read_r (struct _reent *r, int file, char * ptr, int len) +{ + r = r; + file = file; + ptr = ptr; + len = len; + _read(file,ptr,len); + errno = EINVAL; + return -1; +} + +/***************************************************************************/ + +int _lseek_r (struct _reent *r, int file, int ptr, int dir) +{ + r = r; + file = file; + ptr = ptr; + dir = dir; + + return 0; +} + +/***************************************************************************/ + +int _write_r (struct _reent *r, int file, char * ptr, int len) +{ + return _write(file, ptr, len); +} + +/***************************************************************************/ + +int _close_r (struct _reent *r, int file) +{ + return 0; +} + +/***************************************************************************/ + +caddr_t _sbrk_r (struct _reent *r, int incr) +{ + register char * stack_ptr __asm__ ("sp"); + extern char _end; /* Defined by the linker */ + static char *heap_end; + char *prev_heap_end; + if (heap_end == 0) { + heap_end = &_end; + } + prev_heap_end = heap_end; + if (heap_end + incr > stack_ptr) { + _write (1, "Heap and stack collision\n", 25); + abort (); + } + heap_end += incr; + return (caddr_t) prev_heap_end; +} + +/***************************************************************************/ + +int _fstat_r (struct _reent *r, int file, struct stat * st) +{ + r = r; + file = file; + + memset (st, 0, sizeof (* st)); + st->st_mode = S_IFCHR; + return 0; +} + +/***************************************************************************/ +int _open_r(struct _reent *r,const char *name, int flags, int mode) +{ + return _open(name, flags, mode); +} + +int _isatty_r(struct _reent *r, int fd) +{ + r = r; + fd = fd; + + return 1; +} + + +#ifdef __cplusplus +} +#endif + + diff --git a/mkspecs/stm32f4/qmake.conf b/mkspecs/stm32f4/qmake.conf --- a/mkspecs/stm32f4/qmake.conf +++ b/mkspecs/stm32f4/qmake.conf @@ -45,9 +45,7 @@ contains( TEMPLATE, app ) { stflash.target = stflash stflash.commands = cd $$DESTDIR && sudo st-flash write $(QMAKE_TARGET).bin 0x08000000 - dfu-util.target = dfu-util - dfu-util.commands = cd $$DESTDIR && sudo dfu-util -i 0 -a 0 -d 0483:df11 -D $(QMAKE_TARGET).dfu - QMAKE_EXTRA_TARGETS += stflash dfu-util + QMAKE_EXTRA_TARGETS += stflash } contains( TEMPLATE, lib ) {