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lpc17XX Rules OK, Makefile generator OK
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1 # use glob syntax.
2 syntax: glob
3
4 *.*~
5 *~
6 *.o
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1 #!/bin/bash
2 #/*------------------------------------------------------------------------------
3 #-- This file is a part of the libuc, microcontroler library
4 #-- Copyright (C) 2011, Alexis Jeandet
5 #--
6 #-- This program is free software; you can redistribute it and/or modify
7 #-- it under the terms of the GNU General Public License as published by
8 #-- the Free Software Foundation; either version 3 of the License, or
9 #-- (at your option) any later version.
10 #--
11 #-- This program is distributed in the hope that it will be useful,
12 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 #-- GNU General Public License for more details.
15 #--
16 #-- You should have received a copy of the GNU General Public License
17 #-- along with this program; if not, write to the Free Software
18 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #-------------------------------------------------------------------------------
20 #-- Author : Alexis Jeandet
21 #-- Mail : alexis.jeandet@gmail.com
22 #-------------------------------------------------------------------------------*/
23 TEMPLATE=""
24 ARCH=""
25 TARGET=""
26 SRCFILES=""
27 INCLUDES=""
28 LIBRARIES=""
29 HEADERSINSTALLPATH=""
30 TARGETINSTALLPATH=""
31
32 function getFilesList {
33 sed ':a;N;$!ba;s/\\\n/ /g' $1 | sed ':a;N;$!ba;s/\\ \n/ /g' | grep -i $2 | sed 's/\t//g'
34 }
35
36 function Template {
37 TEMPLATE=`more $1 | grep -i "TEMPLATE " | sed s/TEMPLATE// | sed s/=// | sed 's/^[ \t]*//;s/[ \t]*$//'`
38 }
39
40 function Arch {
41 ARCH=`more $1 | grep -i "ARCH " | sed s/ARCH// | sed s/=// | sed 's/^[ \t]*//;s/[ \t]*$//'`
42 }
43
44 function Target {
45 TARGET=`more $1 | grep -i "TARGET " | sed s/TARGET// | sed s/=// | sed 's/^[ \t]*//;s/[ \t]*$//'`
46 }
47
48 function Libs_Inc {
49 INCLUDEStmp=`more $1 | grep -i "LIBS " | sed s/LIBS// |sed s/+//|sed s/=//| sed 's/^[ \t]*//;s/[ \t]*$//'`
50 for FILES in $INCLUDEStmp
51 do
52 INCLUDES+='$('"LIBUC_INC_DIR_$FILES) "
53 done
54 }
55 function Libs_Link {
56 LIBRARIEStmp=`more $1 | grep -i "LIBS " | sed s/LIBS// |sed s/+//|sed s/=//| sed 's/^[ \t]*//;s/[ \t]*$//'`
57 for FILES in $LIBRARIEStmp
58 do
59 LIBRARIES+='$('"LIBUC_LIBS_DIR_$FILES) "'$('"LIBUC_LIBS_$FILES) "
60 done
61 }
62
63 function HeadersInstallPath {
64 HEADERSINSTALLPATH=`more $1 | grep -i "HEADERSINSTALLPATH" | sed s/HEADERSINSTALLPATH// | sed s/=// | sed 's/^[ \t]*//;s/[ \t]*$//'`
65 }
66
67 function TargetInstallPath {
68 TARGETINSTALLPATH=`more $1 | grep -i "TARGETINSTALLPATH" | sed s/TARGETINSTALLPATH// | sed s/=// | sed 's/^[ \t]*//;s/[ \t]*$//'`
69 }
70
71
72
73 Template $1
74 Target $1
75 Arch $1
76 Libs_Inc $1
77 Libs_Link $1
78 HeadersInstallPath $1
79 TargetInstallPath $1
80 echo $SRCFILES > Makefile
81 getFilesList $1 HEADERS >> Makefile
82 getFilesList $1 SOURCES >> Makefile
83 echo 'PROJECTDIR = `pwd`'>> Makefile
84 echo 'OBJECTFILES = $(SOURCES:.c=.o)'>> Makefile
85 echo "LIBUC = $libuc2" >> Makefile
86 echo "ARCH = "'$(LIBUC)'"/rules/$ARCH" >> Makefile
87 echo "TARGET=$TARGET">> Makefile
88 echo "LIBUC_INCLUDES=$INCLUDES">> Makefile
89 echo "LIBUC_LIBRARIES=$LIBRARIES">> Makefile
90 echo "TARGETINSTALLPATH=$TARGETINSTALLPATH">> Makefile
91 echo "HEADERSINSTALLPATH=$HEADERSINSTALLPATH">> Makefile
92 echo 'include $(ARCH)/rules.mk' >> Makefile
93
94
95
96 if(echo $TEMPLATE|grep -i app); then
97 echo '' >> Makefile
98 echo 'all:bin' >> Makefile
99 echo " @echo Code compiled" >> Makefile
100 else
101 if(echo $TEMPLATE|grep -i lib); then
102 echo '' >> Makefile
103 echo 'all:lib' >> Makefile
104 echo " @echo Code compiled" >> Makefile
105 else
106 if(echo $TEMPLATE|grep -i dir); then
107 echo '' >> Makefile
108 echo 'all:subdir' >> Makefile
109 echo " @echo Code compiled" >> Makefile
110 fi
111 fi
112 fi
113 echo $TEMPLATE
114 echo $TARGET
115 echo $ARCH
116
117
118
119
120
121
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1 NO CONTENT: new file 100644, binary diff hidden
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the libuc, microcontroler library
3 -- Copyright (C) 2011, Alexis Jeandet
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@gmail.com
21 -------------------------------------------------------------------------------*/
22 #include "LPC17xx.h"
23
24 struct ARM7uartRegs
25 {
26 unsigned long RWreg;
27 unsigned long IntEN;
28 unsigned long IntIdFIFOctrlr;
29 unsigned long LineCtrl;
30 unsigned long dummy;
31 unsigned long LineStat;
32 unsigned long ScratchPad;
33 };
34
35 typedef struct ARM7uartRegs uartDev;
36
37 uartDev* uartopen(int count);
38 void uartputc(uartDev* dev,char c);
39 void uartputs(uartDev* dev,char *s);
40 void uartgets(uartDev* dev,char *s);
41 char uartgetc(uartDev* dev);
42 void uartsetup(uartDev* dev,int baudRate,int cpuClk);
43
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1
2 HEADERSINSTALLPATH = $(LIBUC_INC_DIR)/UART
3 HEADERS += uart.h
4 SOURCES += uart.c
5 PROJECTDIR = `pwd`
6 OBJECTFILES = $(SOURCES:.c=.o)
7 LIBUC = /opt/libuc2
8 ARCH = $(LIBUC)/rules/lpc17XX-arm-noabi-gcc
9 TARGET=libuart
10 LIBUC_INCLUDES=
11 LIBUC_LIBRARIES=
12 TARGETINSTALLPATH=$(LIBUC_LIBS_DIR)/UART
13 HEADERSINSTALLPATH=$(LIBUC_INC_DIR)/UART
14 include $(ARCH)/rules.mk
15
16 all:lib
17 @echo Code compiled
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the libuc, microcontroler library
3 -- Copyright (C) 2011, Alexis Jeandet
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@gmail.com
21 -------------------------------------------------------------------------------*/
22 #include "uart.h"
23
24
25 void uartputc(uartDev* dev,char c) {
26 while (!((dev->LineStat & (1<<5))));
27 dev->RWreg = c;
28 }
29
30 char uartgetc(uartDev* dev) {
31 while (!((dev->LineStat & 1)));
32 return (char)dev->RWreg;
33 }
34
35
36 void uartputs(uartDev* dev,char *s) {
37 while (*s) uartputc(dev,*s++);
38 }
39
40
41 void uartgets(uartDev* dev,char *s) {
42 while (*s && (*s!=0xd)) *s++ = uartgetc(dev);
43 }
44
45 void uartsetup(uartDev* dev,int baudRate,int cpuClk)
46 {}
47
48 uartDev* uartopen(int count){
49 uartDev* dev;
50 switch(count)
51 {
52 case 0:
53 dev = (uartDev*)((unsigned long)LPC_UART0_BASE);
54 break;
55 case 1:
56 dev = (uartDev*)((unsigned long)LPC_UART1_BASE);
57 break;
58 case 2:
59 dev = (uartDev*)((unsigned long)LPC_UART2_BASE);
60 break;
61 case 3:
62 dev = (uartDev*)((unsigned long)LPC_UART3_BASE);
63 break;
64 default:
65 dev = (uartDev*)0;
66 break;
67 }
68 return dev;
69 }
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1 uart.o: uart.c uart.h /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/LPC17xx.h \
2 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/core_cm3.h \
3 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/system_LPC17xx.h
4
5 uart.h:
6
7 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/LPC17xx.h:
8
9 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/core_cm3.h:
10
11 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/system_LPC17xx.h:
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the libuc, microcontroler library
3 -- Copyright (C) 2011, Alexis Jeandet
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@gmail.com
21 -------------------------------------------------------------------------------*/
22 #include "LPC17xx.h"
23
24 struct ARM7uartRegs
25 {
26 unsigned long RWreg;
27 unsigned long IntEN;
28 unsigned long IntIdFIFOctrlr;
29 unsigned long LineCtrl;
30 unsigned long dummy;
31 unsigned long LineStat;
32 unsigned long ScratchPad;
33 };
34
35 typedef struct ARM7uartRegs uartDev;
36
37 uartDev* uartopen(int count);
38 void uartputc(uartDev* dev,char c);
39 void uartputs(uartDev* dev,char *s);
40 void uartgets(uartDev* dev,char *s);
41 char uartgetc(uartDev* dev);
42 void uartsetup(uartDev* dev,int baudRate,int cpuClk);
43
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1 TEMPLATE = lib
2 ARCH = lpc17XX-arm-noabi-gcc
3 TARGET = libuart
4 TARGETINSTALLPATH = $(LIBUC_LIBS_DIR)/UART
5 HEADERSINSTALLPATH = $(LIBUC_INC_DIR)/UART
6
7 LIBS +=
8
9 SOURCES += uart.c
10
11
12 HEADERS += uart.h
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1 /**************************************************************************//**
2 * @file LPC17xx.h
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
4 * NXP LPC17xx Device Series
5 * @version V1.07
6 * @date 19. October 2009
7 *
8 * @note
9 * Copyright (C) 2009 ARM Limited. All rights reserved.
10 *
11 * @par
12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
13 * processor based microcontrollers. This file can be freely distributed
14 * within development tools that are supporting such ARM based processors.
15 *
16 * @par
17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22 *
23 ******************************************************************************/
24
25
26 #ifndef __LPC17xx_H__
27 #define __LPC17xx_H__
28
29 /*
30 * ==========================================================================
31 * ---------- Interrupt Number Definition -----------------------------------
32 * ==========================================================================
33 */
34
35 typedef enum IRQn
36 {
37 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
38 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
39 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
40 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
41 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
42 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
43 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
44 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
45 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
46
47 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
48 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
49 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
50 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
51 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
52 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
53 UART0_IRQn = 5, /*!< UART0 Interrupt */
54 UART1_IRQn = 6, /*!< UART1 Interrupt */
55 UART2_IRQn = 7, /*!< UART2 Interrupt */
56 UART3_IRQn = 8, /*!< UART3 Interrupt */
57 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
58 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
59 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
60 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
61 SPI_IRQn = 13, /*!< SPI Interrupt */
62 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
63 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
64 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
65 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
66 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
67 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
68 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
69 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
70 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
71 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
72 USB_IRQn = 24, /*!< USB Interrupt */
73 CAN_IRQn = 25, /*!< CAN Interrupt */
74 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
75 I2S_IRQn = 27, /*!< I2S Interrupt */
76 ENET_IRQn = 28, /*!< Ethernet Interrupt */
77 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
78 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
79 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
80 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
81 } IRQn_Type;
82
83
84 /*
85 * ==========================================================================
86 * ----------- Processor and Core Peripheral Section ------------------------
87 * ==========================================================================
88 */
89
90 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
91 #define __MPU_PRESENT 1 /*!< MPU present or not */
92 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
93 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
94
95
96 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
97 #include "system_LPC17xx.h" /* System Header */
98
99
100 /******************************************************************************/
101 /* Device Specific Peripheral registers structures */
102 /******************************************************************************/
103
104 #if defined ( __CC_ARM )
105 #pragma anon_unions
106 #endif
107
108 /*------------- System Control (SC) ------------------------------------------*/
109 typedef struct
110 {
111 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
112 uint32_t RESERVED0[31];
113 __IO uint32_t PLL0CON; /* Clocking and Power Control */
114 __IO uint32_t PLL0CFG;
115 __I uint32_t PLL0STAT;
116 __O uint32_t PLL0FEED;
117 uint32_t RESERVED1[4];
118 __IO uint32_t PLL1CON;
119 __IO uint32_t PLL1CFG;
120 __I uint32_t PLL1STAT;
121 __O uint32_t PLL1FEED;
122 uint32_t RESERVED2[4];
123 __IO uint32_t PCON;
124 __IO uint32_t PCONP;
125 uint32_t RESERVED3[15];
126 __IO uint32_t CCLKCFG;
127 __IO uint32_t USBCLKCFG;
128 __IO uint32_t CLKSRCSEL;
129 uint32_t RESERVED4[12];
130 __IO uint32_t EXTINT; /* External Interrupts */
131 uint32_t RESERVED5;
132 __IO uint32_t EXTMODE;
133 __IO uint32_t EXTPOLAR;
134 uint32_t RESERVED6[12];
135 __IO uint32_t RSID; /* Reset */
136 uint32_t RESERVED7[7];
137 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
138 __IO uint32_t IRCTRIM; /* Clock Dividers */
139 __IO uint32_t PCLKSEL0;
140 __IO uint32_t PCLKSEL1;
141 uint32_t RESERVED8[4];
142 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
143 __IO uint32_t DMAREQSEL;
144 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
145 } LPC_SC_TypeDef;
146
147 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
148 typedef struct
149 {
150 __IO uint32_t PINSEL0;
151 __IO uint32_t PINSEL1;
152 __IO uint32_t PINSEL2;
153 __IO uint32_t PINSEL3;
154 __IO uint32_t PINSEL4;
155 __IO uint32_t PINSEL5;
156 __IO uint32_t PINSEL6;
157 __IO uint32_t PINSEL7;
158 __IO uint32_t PINSEL8;
159 __IO uint32_t PINSEL9;
160 __IO uint32_t PINSEL10;
161 uint32_t RESERVED0[5];
162 __IO uint32_t PINMODE0;
163 __IO uint32_t PINMODE1;
164 __IO uint32_t PINMODE2;
165 __IO uint32_t PINMODE3;
166 __IO uint32_t PINMODE4;
167 __IO uint32_t PINMODE5;
168 __IO uint32_t PINMODE6;
169 __IO uint32_t PINMODE7;
170 __IO uint32_t PINMODE8;
171 __IO uint32_t PINMODE9;
172 __IO uint32_t PINMODE_OD0;
173 __IO uint32_t PINMODE_OD1;
174 __IO uint32_t PINMODE_OD2;
175 __IO uint32_t PINMODE_OD3;
176 __IO uint32_t PINMODE_OD4;
177 __IO uint32_t I2CPADCFG;
178 } LPC_PINCON_TypeDef;
179
180 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
181 typedef struct
182 {
183 union {
184 __IO uint32_t FIODIR;
185 struct {
186 __IO uint16_t FIODIRL;
187 __IO uint16_t FIODIRH;
188 };
189 struct {
190 __IO uint8_t FIODIR0;
191 __IO uint8_t FIODIR1;
192 __IO uint8_t FIODIR2;
193 __IO uint8_t FIODIR3;
194 };
195 };
196 uint32_t RESERVED0[3];
197 union {
198 __IO uint32_t FIOMASK;
199 struct {
200 __IO uint16_t FIOMASKL;
201 __IO uint16_t FIOMASKH;
202 };
203 struct {
204 __IO uint8_t FIOMASK0;
205 __IO uint8_t FIOMASK1;
206 __IO uint8_t FIOMASK2;
207 __IO uint8_t FIOMASK3;
208 };
209 };
210 union {
211 __IO uint32_t FIOPIN;
212 struct {
213 __IO uint16_t FIOPINL;
214 __IO uint16_t FIOPINH;
215 };
216 struct {
217 __IO uint8_t FIOPIN0;
218 __IO uint8_t FIOPIN1;
219 __IO uint8_t FIOPIN2;
220 __IO uint8_t FIOPIN3;
221 };
222 };
223 union {
224 __IO uint32_t FIOSET;
225 struct {
226 __IO uint16_t FIOSETL;
227 __IO uint16_t FIOSETH;
228 };
229 struct {
230 __IO uint8_t FIOSET0;
231 __IO uint8_t FIOSET1;
232 __IO uint8_t FIOSET2;
233 __IO uint8_t FIOSET3;
234 };
235 };
236 union {
237 __O uint32_t FIOCLR;
238 struct {
239 __O uint16_t FIOCLRL;
240 __O uint16_t FIOCLRH;
241 };
242 struct {
243 __O uint8_t FIOCLR0;
244 __O uint8_t FIOCLR1;
245 __O uint8_t FIOCLR2;
246 __O uint8_t FIOCLR3;
247 };
248 };
249 } LPC_GPIO_TypeDef;
250
251 typedef struct
252 {
253 __I uint32_t IntStatus;
254 __I uint32_t IO0IntStatR;
255 __I uint32_t IO0IntStatF;
256 __O uint32_t IO0IntClr;
257 __IO uint32_t IO0IntEnR;
258 __IO uint32_t IO0IntEnF;
259 uint32_t RESERVED0[3];
260 __I uint32_t IO2IntStatR;
261 __I uint32_t IO2IntStatF;
262 __O uint32_t IO2IntClr;
263 __IO uint32_t IO2IntEnR;
264 __IO uint32_t IO2IntEnF;
265 } LPC_GPIOINT_TypeDef;
266
267 /*------------- Timer (TIM) --------------------------------------------------*/
268 typedef struct
269 {
270 __IO uint32_t IR;
271 __IO uint32_t TCR;
272 __IO uint32_t TC;
273 __IO uint32_t PR;
274 __IO uint32_t PC;
275 __IO uint32_t MCR;
276 __IO uint32_t MR0;
277 __IO uint32_t MR1;
278 __IO uint32_t MR2;
279 __IO uint32_t MR3;
280 __IO uint32_t CCR;
281 __I uint32_t CR0;
282 __I uint32_t CR1;
283 uint32_t RESERVED0[2];
284 __IO uint32_t EMR;
285 uint32_t RESERVED1[12];
286 __IO uint32_t CTCR;
287 } LPC_TIM_TypeDef;
288
289 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
290 typedef struct
291 {
292 __IO uint32_t IR;
293 __IO uint32_t TCR;
294 __IO uint32_t TC;
295 __IO uint32_t PR;
296 __IO uint32_t PC;
297 __IO uint32_t MCR;
298 __IO uint32_t MR0;
299 __IO uint32_t MR1;
300 __IO uint32_t MR2;
301 __IO uint32_t MR3;
302 __IO uint32_t CCR;
303 __I uint32_t CR0;
304 __I uint32_t CR1;
305 __I uint32_t CR2;
306 __I uint32_t CR3;
307 uint32_t RESERVED0;
308 __IO uint32_t MR4;
309 __IO uint32_t MR5;
310 __IO uint32_t MR6;
311 __IO uint32_t PCR;
312 __IO uint32_t LER;
313 uint32_t RESERVED1[7];
314 __IO uint32_t CTCR;
315 } LPC_PWM_TypeDef;
316
317 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
318 typedef struct
319 {
320 union {
321 __I uint8_t RBR;
322 __O uint8_t THR;
323 __IO uint8_t DLL;
324 uint32_t RESERVED0;
325 };
326 union {
327 __IO uint8_t DLM;
328 __IO uint32_t IER;
329 };
330 union {
331 __I uint32_t IIR;
332 __O uint8_t FCR;
333 };
334 __IO uint8_t LCR;
335 uint8_t RESERVED1[7];
336 __I uint8_t LSR;
337 uint8_t RESERVED2[7];
338 __IO uint8_t SCR;
339 uint8_t RESERVED3[3];
340 __IO uint32_t ACR;
341 __IO uint8_t ICR;
342 uint8_t RESERVED4[3];
343 __IO uint8_t FDR;
344 uint8_t RESERVED5[7];
345 __IO uint8_t TER;
346 uint8_t RESERVED6[39];
347 __I uint8_t FIFOLVL;
348 } LPC_UART_TypeDef;
349
350 typedef struct
351 {
352 union {
353 __I uint8_t RBR;
354 __O uint8_t THR;
355 __IO uint8_t DLL;
356 uint32_t RESERVED0;
357 };
358 union {
359 __IO uint8_t DLM;
360 __IO uint32_t IER;
361 };
362 union {
363 __I uint32_t IIR;
364 __O uint8_t FCR;
365 };
366 __IO uint8_t LCR;
367 uint8_t RESERVED1[7];
368 __I uint8_t LSR;
369 uint8_t RESERVED2[7];
370 __IO uint8_t SCR;
371 uint8_t RESERVED3[3];
372 __IO uint32_t ACR;
373 __IO uint8_t ICR;
374 uint8_t RESERVED4[3];
375 __IO uint8_t FDR;
376 uint8_t RESERVED5[7];
377 __IO uint8_t TER;
378 uint8_t RESERVED6[39];
379 __I uint8_t FIFOLVL;
380 } LPC_UART0_TypeDef;
381
382 typedef struct
383 {
384 union {
385 __I uint8_t RBR;
386 __O uint8_t THR;
387 __IO uint8_t DLL;
388 uint32_t RESERVED0;
389 };
390 union {
391 __IO uint8_t DLM;
392 __IO uint32_t IER;
393 };
394 union {
395 __I uint32_t IIR;
396 __O uint8_t FCR;
397 };
398 __IO uint8_t LCR;
399 uint8_t RESERVED1[3];
400 __IO uint8_t MCR;
401 uint8_t RESERVED2[3];
402 __I uint8_t LSR;
403 uint8_t RESERVED3[3];
404 __I uint8_t MSR;
405 uint8_t RESERVED4[3];
406 __IO uint8_t SCR;
407 uint8_t RESERVED5[3];
408 __IO uint32_t ACR;
409 uint32_t RESERVED6;
410 __IO uint32_t FDR;
411 uint32_t RESERVED7;
412 __IO uint8_t TER;
413 uint8_t RESERVED8[27];
414 __IO uint8_t RS485CTRL;
415 uint8_t RESERVED9[3];
416 __IO uint8_t ADRMATCH;
417 uint8_t RESERVED10[3];
418 __IO uint8_t RS485DLY;
419 uint8_t RESERVED11[3];
420 __I uint8_t FIFOLVL;
421 } LPC_UART1_TypeDef;
422
423 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
424 typedef struct
425 {
426 __IO uint32_t SPCR;
427 __I uint32_t SPSR;
428 __IO uint32_t SPDR;
429 __IO uint32_t SPCCR;
430 uint32_t RESERVED0[3];
431 __IO uint32_t SPINT;
432 } LPC_SPI_TypeDef;
433
434 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
435 typedef struct
436 {
437 __IO uint32_t CR0;
438 __IO uint32_t CR1;
439 __IO uint32_t DR;
440 __I uint32_t SR;
441 __IO uint32_t CPSR;
442 __IO uint32_t IMSC;
443 __IO uint32_t RIS;
444 __IO uint32_t MIS;
445 __IO uint32_t ICR;
446 __IO uint32_t DMACR;
447 } LPC_SSP_TypeDef;
448
449 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
450 typedef struct
451 {
452 __IO uint32_t I2CONSET;
453 __I uint32_t I2STAT;
454 __IO uint32_t I2DAT;
455 __IO uint32_t I2ADR0;
456 __IO uint32_t I2SCLH;
457 __IO uint32_t I2SCLL;
458 __O uint32_t I2CONCLR;
459 __IO uint32_t MMCTRL;
460 __IO uint32_t I2ADR1;
461 __IO uint32_t I2ADR2;
462 __IO uint32_t I2ADR3;
463 __I uint32_t I2DATA_BUFFER;
464 __IO uint32_t I2MASK0;
465 __IO uint32_t I2MASK1;
466 __IO uint32_t I2MASK2;
467 __IO uint32_t I2MASK3;
468 } LPC_I2C_TypeDef;
469
470 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
471 typedef struct
472 {
473 __IO uint32_t I2SDAO;
474 __IO uint32_t I2SDAI;
475 __O uint32_t I2STXFIFO;
476 __I uint32_t I2SRXFIFO;
477 __I uint32_t I2SSTATE;
478 __IO uint32_t I2SDMA1;
479 __IO uint32_t I2SDMA2;
480 __IO uint32_t I2SIRQ;
481 __IO uint32_t I2STXRATE;
482 __IO uint32_t I2SRXRATE;
483 __IO uint32_t I2STXBITRATE;
484 __IO uint32_t I2SRXBITRATE;
485 __IO uint32_t I2STXMODE;
486 __IO uint32_t I2SRXMODE;
487 } LPC_I2S_TypeDef;
488
489 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
490 typedef struct
491 {
492 __IO uint32_t RICOMPVAL;
493 __IO uint32_t RIMASK;
494 __IO uint8_t RICTRL;
495 uint8_t RESERVED0[3];
496 __IO uint32_t RICOUNTER;
497 } LPC_RIT_TypeDef;
498
499 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
500 typedef struct
501 {
502 __IO uint8_t ILR;
503 uint8_t RESERVED0[7];
504 __IO uint8_t CCR;
505 uint8_t RESERVED1[3];
506 __IO uint8_t CIIR;
507 uint8_t RESERVED2[3];
508 __IO uint8_t AMR;
509 uint8_t RESERVED3[3];
510 __I uint32_t CTIME0;
511 __I uint32_t CTIME1;
512 __I uint32_t CTIME2;
513 __IO uint8_t SEC;
514 uint8_t RESERVED4[3];
515 __IO uint8_t MIN;
516 uint8_t RESERVED5[3];
517 __IO uint8_t HOUR;
518 uint8_t RESERVED6[3];
519 __IO uint8_t DOM;
520 uint8_t RESERVED7[3];
521 __IO uint8_t DOW;
522 uint8_t RESERVED8[3];
523 __IO uint16_t DOY;
524 uint16_t RESERVED9;
525 __IO uint8_t MONTH;
526 uint8_t RESERVED10[3];
527 __IO uint16_t YEAR;
528 uint16_t RESERVED11;
529 __IO uint32_t CALIBRATION;
530 __IO uint32_t GPREG0;
531 __IO uint32_t GPREG1;
532 __IO uint32_t GPREG2;
533 __IO uint32_t GPREG3;
534 __IO uint32_t GPREG4;
535 __IO uint8_t RTC_AUXEN;
536 uint8_t RESERVED12[3];
537 __IO uint8_t RTC_AUX;
538 uint8_t RESERVED13[3];
539 __IO uint8_t ALSEC;
540 uint8_t RESERVED14[3];
541 __IO uint8_t ALMIN;
542 uint8_t RESERVED15[3];
543 __IO uint8_t ALHOUR;
544 uint8_t RESERVED16[3];
545 __IO uint8_t ALDOM;
546 uint8_t RESERVED17[3];
547 __IO uint8_t ALDOW;
548 uint8_t RESERVED18[3];
549 __IO uint16_t ALDOY;
550 uint16_t RESERVED19;
551 __IO uint8_t ALMON;
552 uint8_t RESERVED20[3];
553 __IO uint16_t ALYEAR;
554 uint16_t RESERVED21;
555 } LPC_RTC_TypeDef;
556
557 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
558 typedef struct
559 {
560 __IO uint8_t WDMOD;
561 uint8_t RESERVED0[3];
562 __IO uint32_t WDTC;
563 __O uint8_t WDFEED;
564 uint8_t RESERVED1[3];
565 __I uint32_t WDTV;
566 __IO uint32_t WDCLKSEL;
567 } LPC_WDT_TypeDef;
568
569 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
570 typedef struct
571 {
572 __IO uint32_t ADCR;
573 __IO uint32_t ADGDR;
574 uint32_t RESERVED0;
575 __IO uint32_t ADINTEN;
576 __I uint32_t ADDR0;
577 __I uint32_t ADDR1;
578 __I uint32_t ADDR2;
579 __I uint32_t ADDR3;
580 __I uint32_t ADDR4;
581 __I uint32_t ADDR5;
582 __I uint32_t ADDR6;
583 __I uint32_t ADDR7;
584 __I uint32_t ADSTAT;
585 __IO uint32_t ADTRM;
586 } LPC_ADC_TypeDef;
587
588 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
589 typedef struct
590 {
591 __IO uint32_t DACR;
592 __IO uint32_t DACCTRL;
593 __IO uint16_t DACCNTVAL;
594 } LPC_DAC_TypeDef;
595
596 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
597 typedef struct
598 {
599 __I uint32_t MCCON;
600 __O uint32_t MCCON_SET;
601 __O uint32_t MCCON_CLR;
602 __I uint32_t MCCAPCON;
603 __O uint32_t MCCAPCON_SET;
604 __O uint32_t MCCAPCON_CLR;
605 __IO uint32_t MCTIM0;
606 __IO uint32_t MCTIM1;
607 __IO uint32_t MCTIM2;
608 __IO uint32_t MCPER0;
609 __IO uint32_t MCPER1;
610 __IO uint32_t MCPER2;
611 __IO uint32_t MCPW0;
612 __IO uint32_t MCPW1;
613 __IO uint32_t MCPW2;
614 __IO uint32_t MCDEADTIME;
615 __IO uint32_t MCCCP;
616 __IO uint32_t MCCR0;
617 __IO uint32_t MCCR1;
618 __IO uint32_t MCCR2;
619 __I uint32_t MCINTEN;
620 __O uint32_t MCINTEN_SET;
621 __O uint32_t MCINTEN_CLR;
622 __I uint32_t MCCNTCON;
623 __O uint32_t MCCNTCON_SET;
624 __O uint32_t MCCNTCON_CLR;
625 __I uint32_t MCINTFLAG;
626 __O uint32_t MCINTFLAG_SET;
627 __O uint32_t MCINTFLAG_CLR;
628 __O uint32_t MCCAP_CLR;
629 } LPC_MCPWM_TypeDef;
630
631 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
632 typedef struct
633 {
634 __O uint32_t QEICON;
635 __I uint32_t QEISTAT;
636 __IO uint32_t QEICONF;
637 __I uint32_t QEIPOS;
638 __IO uint32_t QEIMAXPOS;
639 __IO uint32_t CMPOS0;
640 __IO uint32_t CMPOS1;
641 __IO uint32_t CMPOS2;
642 __I uint32_t INXCNT;
643 __IO uint32_t INXCMP;
644 __IO uint32_t QEILOAD;
645 __I uint32_t QEITIME;
646 __I uint32_t QEIVEL;
647 __I uint32_t QEICAP;
648 __IO uint32_t VELCOMP;
649 __IO uint32_t FILTER;
650 uint32_t RESERVED0[998];
651 __O uint32_t QEIIEC;
652 __O uint32_t QEIIES;
653 __I uint32_t QEIINTSTAT;
654 __I uint32_t QEIIE;
655 __O uint32_t QEICLR;
656 __O uint32_t QEISET;
657 } LPC_QEI_TypeDef;
658
659 /*------------- Controller Area Network (CAN) --------------------------------*/
660 typedef struct
661 {
662 __IO uint32_t mask[512]; /* ID Masks */
663 } LPC_CANAF_RAM_TypeDef;
664
665 typedef struct /* Acceptance Filter Registers */
666 {
667 __IO uint32_t AFMR;
668 __IO uint32_t SFF_sa;
669 __IO uint32_t SFF_GRP_sa;
670 __IO uint32_t EFF_sa;
671 __IO uint32_t EFF_GRP_sa;
672 __IO uint32_t ENDofTable;
673 __I uint32_t LUTerrAd;
674 __I uint32_t LUTerr;
675 __IO uint32_t FCANIE;
676 __IO uint32_t FCANIC0;
677 __IO uint32_t FCANIC1;
678 } LPC_CANAF_TypeDef;
679
680 typedef struct /* Central Registers */
681 {
682 __I uint32_t CANTxSR;
683 __I uint32_t CANRxSR;
684 __I uint32_t CANMSR;
685 } LPC_CANCR_TypeDef;
686
687 typedef struct /* Controller Registers */
688 {
689 __IO uint32_t MOD;
690 __O uint32_t CMR;
691 __IO uint32_t GSR;
692 __I uint32_t ICR;
693 __IO uint32_t IER;
694 __IO uint32_t BTR;
695 __IO uint32_t EWL;
696 __I uint32_t SR;
697 __IO uint32_t RFS;
698 __IO uint32_t RID;
699 __IO uint32_t RDA;
700 __IO uint32_t RDB;
701 __IO uint32_t TFI1;
702 __IO uint32_t TID1;
703 __IO uint32_t TDA1;
704 __IO uint32_t TDB1;
705 __IO uint32_t TFI2;
706 __IO uint32_t TID2;
707 __IO uint32_t TDA2;
708 __IO uint32_t TDB2;
709 __IO uint32_t TFI3;
710 __IO uint32_t TID3;
711 __IO uint32_t TDA3;
712 __IO uint32_t TDB3;
713 } LPC_CAN_TypeDef;
714
715 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
716 typedef struct /* Common Registers */
717 {
718 __I uint32_t DMACIntStat;
719 __I uint32_t DMACIntTCStat;
720 __O uint32_t DMACIntTCClear;
721 __I uint32_t DMACIntErrStat;
722 __O uint32_t DMACIntErrClr;
723 __I uint32_t DMACRawIntTCStat;
724 __I uint32_t DMACRawIntErrStat;
725 __I uint32_t DMACEnbldChns;
726 __IO uint32_t DMACSoftBReq;
727 __IO uint32_t DMACSoftSReq;
728 __IO uint32_t DMACSoftLBReq;
729 __IO uint32_t DMACSoftLSReq;
730 __IO uint32_t DMACConfig;
731 __IO uint32_t DMACSync;
732 } LPC_GPDMA_TypeDef;
733
734 typedef struct /* Channel Registers */
735 {
736 __IO uint32_t DMACCSrcAddr;
737 __IO uint32_t DMACCDestAddr;
738 __IO uint32_t DMACCLLI;
739 __IO uint32_t DMACCControl;
740 __IO uint32_t DMACCConfig;
741 } LPC_GPDMACH_TypeDef;
742
743 /*------------- Universal Serial Bus (USB) -----------------------------------*/
744 typedef struct
745 {
746 __I uint32_t HcRevision; /* USB Host Registers */
747 __IO uint32_t HcControl;
748 __IO uint32_t HcCommandStatus;
749 __IO uint32_t HcInterruptStatus;
750 __IO uint32_t HcInterruptEnable;
751 __IO uint32_t HcInterruptDisable;
752 __IO uint32_t HcHCCA;
753 __I uint32_t HcPeriodCurrentED;
754 __IO uint32_t HcControlHeadED;
755 __IO uint32_t HcControlCurrentED;
756 __IO uint32_t HcBulkHeadED;
757 __IO uint32_t HcBulkCurrentED;
758 __I uint32_t HcDoneHead;
759 __IO uint32_t HcFmInterval;
760 __I uint32_t HcFmRemaining;
761 __I uint32_t HcFmNumber;
762 __IO uint32_t HcPeriodicStart;
763 __IO uint32_t HcLSTreshold;
764 __IO uint32_t HcRhDescriptorA;
765 __IO uint32_t HcRhDescriptorB;
766 __IO uint32_t HcRhStatus;
767 __IO uint32_t HcRhPortStatus1;
768 __IO uint32_t HcRhPortStatus2;
769 uint32_t RESERVED0[40];
770 __I uint32_t Module_ID;
771
772 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
773 __IO uint32_t OTGIntEn;
774 __O uint32_t OTGIntSet;
775 __O uint32_t OTGIntClr;
776 __IO uint32_t OTGStCtrl;
777 __IO uint32_t OTGTmr;
778 uint32_t RESERVED1[58];
779
780 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
781 __IO uint32_t USBDevIntEn;
782 __O uint32_t USBDevIntClr;
783 __O uint32_t USBDevIntSet;
784
785 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
786 __I uint32_t USBCmdData;
787
788 __I uint32_t USBRxData; /* USB Device Transfer Registers */
789 __O uint32_t USBTxData;
790 __I uint32_t USBRxPLen;
791 __O uint32_t USBTxPLen;
792 __IO uint32_t USBCtrl;
793 __O uint32_t USBDevIntPri;
794
795 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
796 __IO uint32_t USBEpIntEn;
797 __O uint32_t USBEpIntClr;
798 __O uint32_t USBEpIntSet;
799 __O uint32_t USBEpIntPri;
800
801 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
802 __O uint32_t USBEpInd;
803 __IO uint32_t USBMaxPSize;
804
805 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
806 __O uint32_t USBDMARClr;
807 __O uint32_t USBDMARSet;
808 uint32_t RESERVED2[9];
809 __IO uint32_t USBUDCAH;
810 __I uint32_t USBEpDMASt;
811 __O uint32_t USBEpDMAEn;
812 __O uint32_t USBEpDMADis;
813 __I uint32_t USBDMAIntSt;
814 __IO uint32_t USBDMAIntEn;
815 uint32_t RESERVED3[2];
816 __I uint32_t USBEoTIntSt;
817 __O uint32_t USBEoTIntClr;
818 __O uint32_t USBEoTIntSet;
819 __I uint32_t USBNDDRIntSt;
820 __O uint32_t USBNDDRIntClr;
821 __O uint32_t USBNDDRIntSet;
822 __I uint32_t USBSysErrIntSt;
823 __O uint32_t USBSysErrIntClr;
824 __O uint32_t USBSysErrIntSet;
825 uint32_t RESERVED4[15];
826
827 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
828 __O uint32_t I2C_WO;
829 __I uint32_t I2C_STS;
830 __IO uint32_t I2C_CTL;
831 __IO uint32_t I2C_CLKHI;
832 __O uint32_t I2C_CLKLO;
833 uint32_t RESERVED5[823];
834
835 union {
836 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
837 __IO uint32_t OTGClkCtrl;
838 };
839 union {
840 __I uint32_t USBClkSt;
841 __I uint32_t OTGClkSt;
842 };
843 } LPC_USB_TypeDef;
844
845 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
846 typedef struct
847 {
848 __IO uint32_t MAC1; /* MAC Registers */
849 __IO uint32_t MAC2;
850 __IO uint32_t IPGT;
851 __IO uint32_t IPGR;
852 __IO uint32_t CLRT;
853 __IO uint32_t MAXF;
854 __IO uint32_t SUPP;
855 __IO uint32_t TEST;
856 __IO uint32_t MCFG;
857 __IO uint32_t MCMD;
858 __IO uint32_t MADR;
859 __O uint32_t MWTD;
860 __I uint32_t MRDD;
861 __I uint32_t MIND;
862 uint32_t RESERVED0[2];
863 __IO uint32_t SA0;
864 __IO uint32_t SA1;
865 __IO uint32_t SA2;
866 uint32_t RESERVED1[45];
867 __IO uint32_t Command; /* Control Registers */
868 __I uint32_t Status;
869 __IO uint32_t RxDescriptor;
870 __IO uint32_t RxStatus;
871 __IO uint32_t RxDescriptorNumber;
872 __I uint32_t RxProduceIndex;
873 __IO uint32_t RxConsumeIndex;
874 __IO uint32_t TxDescriptor;
875 __IO uint32_t TxStatus;
876 __IO uint32_t TxDescriptorNumber;
877 __IO uint32_t TxProduceIndex;
878 __I uint32_t TxConsumeIndex;
879 uint32_t RESERVED2[10];
880 __I uint32_t TSV0;
881 __I uint32_t TSV1;
882 __I uint32_t RSV;
883 uint32_t RESERVED3[3];
884 __IO uint32_t FlowControlCounter;
885 __I uint32_t FlowControlStatus;
886 uint32_t RESERVED4[34];
887 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
888 __IO uint32_t RxFilterWoLStatus;
889 __IO uint32_t RxFilterWoLClear;
890 uint32_t RESERVED5;
891 __IO uint32_t HashFilterL;
892 __IO uint32_t HashFilterH;
893 uint32_t RESERVED6[882];
894 __I uint32_t IntStatus; /* Module Control Registers */
895 __IO uint32_t IntEnable;
896 __O uint32_t IntClear;
897 __O uint32_t IntSet;
898 uint32_t RESERVED7;
899 __IO uint32_t PowerDown;
900 uint32_t RESERVED8;
901 __IO uint32_t Module_ID;
902 } LPC_EMAC_TypeDef;
903
904 #if defined ( __CC_ARM )
905 #pragma no_anon_unions
906 #endif
907
908
909 /******************************************************************************/
910 /* Peripheral memory map */
911 /******************************************************************************/
912 /* Base addresses */
913 #define LPC_FLASH_BASE (0x00000000UL)
914 #define LPC_RAM_BASE (0x10000000UL)
915 #define LPC_GPIO_BASE (0x2009C000UL)
916 #define LPC_APB0_BASE (0x40000000UL)
917 #define LPC_APB1_BASE (0x40080000UL)
918 #define LPC_AHB_BASE (0x50000000UL)
919 #define LPC_CM3_BASE (0xE0000000UL)
920
921 /* APB0 peripherals */
922 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
923 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
924 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
925 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
926 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
927 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
928 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
929 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
930 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
931 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
932 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
933 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
934 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
935 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
936 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
937 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
938 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
939 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
940 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
941
942 /* APB1 peripherals */
943 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
944 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
945 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
946 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
947 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
948 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
949 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
950 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
951 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
952 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
953 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
954 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
955
956 /* AHB peripherals */
957 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
958 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
959 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
960 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
961 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
962 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
963 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
964 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
965 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
966 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
967 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
968
969 /* GPIOs */
970 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
971 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
972 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
973 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
974 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
975
976
977 /******************************************************************************/
978 /* Peripheral declaration */
979 /******************************************************************************/
980 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
981 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
982 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
983 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
984 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
985 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
986 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
987 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
988 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
989 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
990 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
991 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
992 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
993 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
994 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
995 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
996 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
997 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
998 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
999 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
1000 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
1001 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
1002 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
1003 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
1004 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
1005 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
1006 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
1007 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
1008 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
1009 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
1010 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
1011 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
1012 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
1013 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
1014 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
1015 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
1016 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
1017 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
1018 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
1019 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
1020 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
1021 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
1022 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
1023 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
1024 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
1025 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
1026 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
1027
1028 #endif // __LPC17xx_H__
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1 /* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
2 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
3 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
4 * THE AUTHORS SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
5 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. USE IT AT YOUR OWN RISK */
6
7 MEMORY
8 {
9 /* LPC1768 : 512k ROM + 64k SRAM */
10 /*------------------------------ */
11
12 /* On-chip ROM is a readable (r), executable region (x) */
13 /* On-chip SRAM is a readable (r), writable (w) and */
14 /* executable region (x) */
15
16 /* Main ROM region - 512k for LPC1768 */
17 IROM (rx) : ORIGIN = 0x00000000, LENGTH = 512k
18
19 /* local static RAM - 32k for LPC1756 */
20 IRAM0 (rwx) : ORIGIN = 0x10000000, LENGTH = 32k
21
22 /* AHB SRAM - 16k for LPC1756 - often used for USB */
23 IRAM1 (rwx) : ORIGIN = 0x2007C000, LENGTH = 16k
24 IRAM2 (rwx) : ORIGIN = 0x20080000, LENGTH = 16k
25 }
26
27 /* SECTION command : Define mapping of input sections */
28 /* into output sections. */
29
30 SECTIONS
31 {
32 /******************************************/
33 /* code section */
34
35 /* "normal" code */
36
37 .text :
38 {
39 KEEP(*(.isr_vector .isr_vector.*))
40 *(.text .text.*)
41 *(.gnu.linkonce.t.*)
42 *(.glue_7)
43 *(.glue_7t)
44 *(.gcc_except_table)
45 *(.rodata .rodata*)
46 *(.gnu.linkonce.r.*)
47 } >IROM
48
49 /******************************************/
50 /* .ctors .dtors are used for c++ constructors/destructors */
51 .ctors :
52 {
53 . = ALIGN(4);
54 PROVIDE(__ctors_start = .);
55 KEEP(*(SORT(.ctors.*)))
56 KEEP(*(.ctors))
57 PROVIDE(__ctors_end = .);
58 } >IROM
59
60 .dtors :
61 {
62 . = ALIGN(4);
63 PROVIDE(__dtors_start = .);
64 KEEP(*(SORT(.dtors.*)))
65 KEEP(*(.dtors))
66 PROVIDE(__dtors_end = .);
67
68 . = ALIGN(4);
69 /* End Of .text section */
70 _etext = .;
71 _sifastcode = .;
72 } >IROM
73
74 /**************************************************/
75 /* fastcode - copied at startup & executed in RAM */
76
77 .fastcode :
78 {
79 . = ALIGN (4);
80 _sfastcode = . ;
81
82 *(.glue_7t) *(.glue_7)
83 *(.fastcode)
84
85 /* add other modules here ... */
86
87 . = ALIGN (4);
88 _efastcode = . ;
89 _sidata = .;
90 } >IRAM0 AT>IROM
91
92 /******************************************/
93 /* This used for USB RAM section */
94 .usb_ram (NOLOAD):
95 {
96 *.o (USB_RAM)
97 } > IRAM1
98
99 /******************************************/
100 /* data section */
101 .data :
102 {
103 _sidata = LOADADDR (.data);
104 . = ALIGN(4);
105 _sdata = .;
106
107 *(vtable vtable.*)
108 *(.data .data.*)
109 *(.gnu.linkonce.d*)
110
111 . = ALIGN(4);
112 _edata = . ;
113 } >IRAM0 AT>IROM
114
115 /******************************************/
116 /* For no-init variables section */
117 .bss (NOLOAD) :
118 {
119 . = ALIGN(4);
120 _sbss = . ;
121
122 *(.bss .bss.*)
123 *(.gnu.linkonce.b*)
124 *(COMMON)
125
126 . = ALIGN(4);
127 _ebss = . ;
128 } >IRAM0
129
130 /******************************************/
131 /* For stack section */
132 .stackarea (NOLOAD) :
133 {
134 . = ALIGN(8);
135 _sstack = .;
136
137 *(.stackarea .stackarea.*)
138
139 . = ALIGN(8);
140 _estack = .;
141
142 . = ALIGN(4);
143 _end = . ;
144 PROVIDE (end = .);
145
146 } > IRAM0
147
148 /******************************************/
149 /* Stabs debugging sections. */
150 .stab 0 : { *(.stab) }
151 .stabstr 0 : { *(.stabstr) }
152 .stab.excl 0 : { *(.stab.excl) }
153 .stab.exclstr 0 : { *(.stab.exclstr) }
154 .stab.index 0 : { *(.stab.index) }
155 .stab.indexstr 0 : { *(.stab.indexstr) }
156 /* .comment 0 : { *(.comment) } */
157 /* DWARF debug sections.
158 Symbols in the DWARF debugging sections are relative to the beginning
159 of the section so we begin them at 0. */
160 /* DWARF 1 */
161 .debug 0 : { *(.debug) }
162 .line 0 : { *(.line) }
163 /* GNU DWARF 1 extensions */
164 .debug_srcinfo 0 : { *(.debug_srcinfo) }
165 .debug_sfnames 0 : { *(.debug_sfnames) }
166 /* DWARF 1.1 and DWARF 2 */
167 .debug_aranges 0 : { *(.debug_aranges) }
168 .debug_pubnames 0 : { *(.debug_pubnames) }
169 /* DWARF 2 */
170 .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
171 .debug_abbrev 0 : { *(.debug_abbrev) }
172 .debug_line 0 : { *(.debug_line) }
173 .debug_frame 0 : { *(.debug_frame) }
174 .debug_str 0 : { *(.debug_str) }
175 .debug_loc 0 : { *(.debug_loc) }
176 .debug_macinfo 0 : { *(.debug_macinfo) }
177 /* SGI/MIPS DWARF 2 extensions */
178 .debug_weaknames 0 : { *(.debug_weaknames) }
179 .debug_funcnames 0 : { *(.debug_funcnames) }
180 .debug_typenames 0 : { *(.debug_typenames) }
181 .debug_varnames 0 : { *(.debug_varnames) }
182 }
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1 /**************************************************************************//**
2 * @file core_cm3.c
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
4 * @version V1.30
5 * @date 30. October 2009
6 *
7 * @note
8 * Copyright (C) 2009 ARM Limited. All rights reserved.
9 *
10 * @par
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * @par
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 *
22 ******************************************************************************/
23
24 #include <stdint.h>
25
26 /* define compiler specific symbols */
27 #if defined ( __CC_ARM )
28 #define __ASM __asm /*!< asm keyword for ARM Compiler */
29 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
30
31 #elif defined ( __ICCARM__ )
32 #define __ASM __asm /*!< asm keyword for IAR Compiler */
33 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
34
35 #elif defined ( __GNUC__ )
36 #define __ASM __asm /*!< asm keyword for GNU Compiler */
37 #define __INLINE inline /*!< inline keyword for GNU Compiler */
38
39 #elif defined ( __TASKING__ )
40 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
41 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
42
43 #endif
44
45
46 /* ################### Compiler specific Intrinsics ########################### */
47
48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
49 /* ARM armcc specific functions */
50
51 /**
52 * @brief Return the Process Stack Pointer
53 *
54 * @return ProcessStackPointer
55 *
56 * Return the actual process stack pointer
57 */
58 __ASM uint32_t __get_PSP(void)
59 {
60 mrs r0, psp
61 bx lr
62 }
63
64 /**
65 * @brief Set the Process Stack Pointer
66 *
67 * @param topOfProcStack Process Stack Pointer
68 *
69 * Assign the value ProcessStackPointer to the MSP
70 * (process stack pointer) Cortex processor register
71 */
72 __ASM void __set_PSP(uint32_t topOfProcStack)
73 {
74 msr psp, r0
75 bx lr
76 }
77
78 /**
79 * @brief Return the Main Stack Pointer
80 *
81 * @return Main Stack Pointer
82 *
83 * Return the current value of the MSP (main stack pointer)
84 * Cortex processor register
85 */
86 __ASM uint32_t __get_MSP(void)
87 {
88 mrs r0, msp
89 bx lr
90 }
91
92 /**
93 * @brief Set the Main Stack Pointer
94 *
95 * @param topOfMainStack Main Stack Pointer
96 *
97 * Assign the value mainStackPointer to the MSP
98 * (main stack pointer) Cortex processor register
99 */
100 __ASM void __set_MSP(uint32_t mainStackPointer)
101 {
102 msr msp, r0
103 bx lr
104 }
105
106 /**
107 * @brief Reverse byte order in unsigned short value
108 *
109 * @param value value to reverse
110 * @return reversed value
111 *
112 * Reverse byte order in unsigned short value
113 */
114 __ASM uint32_t __REV16(uint16_t value)
115 {
116 rev16 r0, r0
117 bx lr
118 }
119
120 /**
121 * @brief Reverse byte order in signed short value with sign extension to integer
122 *
123 * @param value value to reverse
124 * @return reversed value
125 *
126 * Reverse byte order in signed short value with sign extension to integer
127 */
128 __ASM int32_t __REVSH(int16_t value)
129 {
130 revsh r0, r0
131 bx lr
132 }
133
134
135 #if (__ARMCC_VERSION < 400000)
136
137 /**
138 * @brief Remove the exclusive lock created by ldrex
139 *
140 * Removes the exclusive lock which is created by ldrex.
141 */
142 __ASM void __CLREX(void)
143 {
144 clrex
145 }
146
147 /**
148 * @brief Return the Base Priority value
149 *
150 * @return BasePriority
151 *
152 * Return the content of the base priority register
153 */
154 __ASM uint32_t __get_BASEPRI(void)
155 {
156 mrs r0, basepri
157 bx lr
158 }
159
160 /**
161 * @brief Set the Base Priority value
162 *
163 * @param basePri BasePriority
164 *
165 * Set the base priority register
166 */
167 __ASM void __set_BASEPRI(uint32_t basePri)
168 {
169 msr basepri, r0
170 bx lr
171 }
172
173 /**
174 * @brief Return the Priority Mask value
175 *
176 * @return PriMask
177 *
178 * Return state of the priority mask bit from the priority mask register
179 */
180 __ASM uint32_t __get_PRIMASK(void)
181 {
182 mrs r0, primask
183 bx lr
184 }
185
186 /**
187 * @brief Set the Priority Mask value
188 *
189 * @param priMask PriMask
190 *
191 * Set the priority mask bit in the priority mask register
192 */
193 __ASM void __set_PRIMASK(uint32_t priMask)
194 {
195 msr primask, r0
196 bx lr
197 }
198
199 /**
200 * @brief Return the Fault Mask value
201 *
202 * @return FaultMask
203 *
204 * Return the content of the fault mask register
205 */
206 __ASM uint32_t __get_FAULTMASK(void)
207 {
208 mrs r0, faultmask
209 bx lr
210 }
211
212 /**
213 * @brief Set the Fault Mask value
214 *
215 * @param faultMask faultMask value
216 *
217 * Set the fault mask register
218 */
219 __ASM void __set_FAULTMASK(uint32_t faultMask)
220 {
221 msr faultmask, r0
222 bx lr
223 }
224
225 /**
226 * @brief Return the Control Register value
227 *
228 * @return Control value
229 *
230 * Return the content of the control register
231 */
232 __ASM uint32_t __get_CONTROL(void)
233 {
234 mrs r0, control
235 bx lr
236 }
237
238 /**
239 * @brief Set the Control Register value
240 *
241 * @param control Control value
242 *
243 * Set the control register
244 */
245 __ASM void __set_CONTROL(uint32_t control)
246 {
247 msr control, r0
248 bx lr
249 }
250
251 #endif /* __ARMCC_VERSION */
252
253
254
255 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
256 /* IAR iccarm specific functions */
257 #pragma diag_suppress=Pe940
258
259 /**
260 * @brief Return the Process Stack Pointer
261 *
262 * @return ProcessStackPointer
263 *
264 * Return the actual process stack pointer
265 */
266 uint32_t __get_PSP(void)
267 {
268 __ASM("mrs r0, psp");
269 __ASM("bx lr");
270 }
271
272 /**
273 * @brief Set the Process Stack Pointer
274 *
275 * @param topOfProcStack Process Stack Pointer
276 *
277 * Assign the value ProcessStackPointer to the MSP
278 * (process stack pointer) Cortex processor register
279 */
280 void __set_PSP(uint32_t topOfProcStack)
281 {
282 __ASM("msr psp, r0");
283 __ASM("bx lr");
284 }
285
286 /**
287 * @brief Return the Main Stack Pointer
288 *
289 * @return Main Stack Pointer
290 *
291 * Return the current value of the MSP (main stack pointer)
292 * Cortex processor register
293 */
294 uint32_t __get_MSP(void)
295 {
296 __ASM("mrs r0, msp");
297 __ASM("bx lr");
298 }
299
300 /**
301 * @brief Set the Main Stack Pointer
302 *
303 * @param topOfMainStack Main Stack Pointer
304 *
305 * Assign the value mainStackPointer to the MSP
306 * (main stack pointer) Cortex processor register
307 */
308 void __set_MSP(uint32_t topOfMainStack)
309 {
310 __ASM("msr msp, r0");
311 __ASM("bx lr");
312 }
313
314 /**
315 * @brief Reverse byte order in unsigned short value
316 *
317 * @param value value to reverse
318 * @return reversed value
319 *
320 * Reverse byte order in unsigned short value
321 */
322 uint32_t __REV16(uint16_t value)
323 {
324 __ASM("rev16 r0, r0");
325 __ASM("bx lr");
326 }
327
328 /**
329 * @brief Reverse bit order of value
330 *
331 * @param value value to reverse
332 * @return reversed value
333 *
334 * Reverse bit order of value
335 */
336 uint32_t __RBIT(uint32_t value)
337 {
338 __ASM("rbit r0, r0");
339 __ASM("bx lr");
340 }
341
342 /**
343 * @brief LDR Exclusive (8 bit)
344 *
345 * @param *addr address pointer
346 * @return value of (*address)
347 *
348 * Exclusive LDR command for 8 bit values)
349 */
350 uint8_t __LDREXB(uint8_t *addr)
351 {
352 __ASM("ldrexb r0, [r0]");
353 __ASM("bx lr");
354 }
355
356 /**
357 * @brief LDR Exclusive (16 bit)
358 *
359 * @param *addr address pointer
360 * @return value of (*address)
361 *
362 * Exclusive LDR command for 16 bit values
363 */
364 uint16_t __LDREXH(uint16_t *addr)
365 {
366 __ASM("ldrexh r0, [r0]");
367 __ASM("bx lr");
368 }
369
370 /**
371 * @brief LDR Exclusive (32 bit)
372 *
373 * @param *addr address pointer
374 * @return value of (*address)
375 *
376 * Exclusive LDR command for 32 bit values
377 */
378 uint32_t __LDREXW(uint32_t *addr)
379 {
380 __ASM("ldrex r0, [r0]");
381 __ASM("bx lr");
382 }
383
384 /**
385 * @brief STR Exclusive (8 bit)
386 *
387 * @param value value to store
388 * @param *addr address pointer
389 * @return successful / failed
390 *
391 * Exclusive STR command for 8 bit values
392 */
393 uint32_t __STREXB(uint8_t value, uint8_t *addr)
394 {
395 __ASM("strexb r0, r0, [r1]");
396 __ASM("bx lr");
397 }
398
399 /**
400 * @brief STR Exclusive (16 bit)
401 *
402 * @param value value to store
403 * @param *addr address pointer
404 * @return successful / failed
405 *
406 * Exclusive STR command for 16 bit values
407 */
408 uint32_t __STREXH(uint16_t value, uint16_t *addr)
409 {
410 __ASM("strexh r0, r0, [r1]");
411 __ASM("bx lr");
412 }
413
414 /**
415 * @brief STR Exclusive (32 bit)
416 *
417 * @param value value to store
418 * @param *addr address pointer
419 * @return successful / failed
420 *
421 * Exclusive STR command for 32 bit values
422 */
423 uint32_t __STREXW(uint32_t value, uint32_t *addr)
424 {
425 __ASM("strex r0, r0, [r1]");
426 __ASM("bx lr");
427 }
428
429 #pragma diag_default=Pe940
430
431
432 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
433 /* GNU gcc specific functions */
434
435 /**
436 * @brief Return the Process Stack Pointer
437 *
438 * @return ProcessStackPointer
439 *
440 * Return the actual process stack pointer
441 */
442 uint32_t __get_PSP(void) __attribute__( ( naked ) );
443 uint32_t __get_PSP(void)
444 {
445 uint32_t result=0;
446
447 __ASM volatile ("MRS %0, psp\n\t"
448 "MOV r0, %0 \n\t"
449 "BX lr \n\t" : "=r" (result) );
450 return(result);
451 }
452
453 /**
454 * @brief Set the Process Stack Pointer
455 *
456 * @param topOfProcStack Process Stack Pointer
457 *
458 * Assign the value ProcessStackPointer to the MSP
459 * (process stack pointer) Cortex processor register
460 */
461 void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
462 void __set_PSP(uint32_t topOfProcStack)
463 {
464 __ASM volatile ("MSR psp, %0\n\t"
465 "BX lr \n\t" : : "r" (topOfProcStack) );
466 }
467
468 /**
469 * @brief Return the Main Stack Pointer
470 *
471 * @return Main Stack Pointer
472 *
473 * Return the current value of the MSP (main stack pointer)
474 * Cortex processor register
475 */
476 uint32_t __get_MSP(void) __attribute__( ( naked ) );
477 uint32_t __get_MSP(void)
478 {
479 uint32_t result=0;
480
481 __ASM volatile ("MRS %0, msp\n\t"
482 "MOV r0, %0 \n\t"
483 "BX lr \n\t" : "=r" (result) );
484 return(result);
485 }
486
487 /**
488 * @brief Set the Main Stack Pointer
489 *
490 * @param topOfMainStack Main Stack Pointer
491 *
492 * Assign the value mainStackPointer to the MSP
493 * (main stack pointer) Cortex processor register
494 */
495 void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
496 void __set_MSP(uint32_t topOfMainStack)
497 {
498 __ASM volatile ("MSR msp, %0\n\t"
499 "BX lr \n\t" : : "r" (topOfMainStack) );
500 }
501
502 /**
503 * @brief Return the Base Priority value
504 *
505 * @return BasePriority
506 *
507 * Return the content of the base priority register
508 */
509 uint32_t __get_BASEPRI(void)
510 {
511 uint32_t result=0;
512
513 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
514 return(result);
515 }
516
517 /**
518 * @brief Set the Base Priority value
519 *
520 * @param basePri BasePriority
521 *
522 * Set the base priority register
523 */
524 void __set_BASEPRI(uint32_t value)
525 {
526 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
527 }
528
529 /**
530 * @brief Return the Priority Mask value
531 *
532 * @return PriMask
533 *
534 * Return state of the priority mask bit from the priority mask register
535 */
536 uint32_t __get_PRIMASK(void)
537 {
538 uint32_t result=0;
539
540 __ASM volatile ("MRS %0, primask" : "=r" (result) );
541 return(result);
542 }
543
544 /**
545 * @brief Set the Priority Mask value
546 *
547 * @param priMask PriMask
548 *
549 * Set the priority mask bit in the priority mask register
550 */
551 void __set_PRIMASK(uint32_t priMask)
552 {
553 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
554 }
555
556 /**
557 * @brief Return the Fault Mask value
558 *
559 * @return FaultMask
560 *
561 * Return the content of the fault mask register
562 */
563 uint32_t __get_FAULTMASK(void)
564 {
565 uint32_t result=0;
566
567 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
568 return(result);
569 }
570
571 /**
572 * @brief Set the Fault Mask value
573 *
574 * @param faultMask faultMask value
575 *
576 * Set the fault mask register
577 */
578 void __set_FAULTMASK(uint32_t faultMask)
579 {
580 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
581 }
582
583 /**
584 * @brief Return the Control Register value
585 *
586 * @return Control value
587 *
588 * Return the content of the control register
589 */
590 uint32_t __get_CONTROL(void)
591 {
592 uint32_t result=0;
593
594 __ASM volatile ("MRS %0, control" : "=r" (result) );
595 return(result);
596 }
597
598 /**
599 * @brief Set the Control Register value
600 *
601 * @param control Control value
602 *
603 * Set the control register
604 */
605 void __set_CONTROL(uint32_t control)
606 {
607 __ASM volatile ("MSR control, %0" : : "r" (control) );
608 }
609
610
611 /**
612 * @brief Reverse byte order in integer value
613 *
614 * @param value value to reverse
615 * @return reversed value
616 *
617 * Reverse byte order in integer value
618 */
619 uint32_t __REV(uint32_t value)
620 {
621 uint32_t result=0;
622
623 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
624 return(result);
625 }
626
627 /**
628 * @brief Reverse byte order in unsigned short value
629 *
630 * @param value value to reverse
631 * @return reversed value
632 *
633 * Reverse byte order in unsigned short value
634 */
635 uint32_t __REV16(uint16_t value)
636 {
637 uint32_t result=0;
638
639 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
640 return(result);
641 }
642
643 /**
644 * @brief Reverse byte order in signed short value with sign extension to integer
645 *
646 * @param value value to reverse
647 * @return reversed value
648 *
649 * Reverse byte order in signed short value with sign extension to integer
650 */
651 int32_t __REVSH(int16_t value)
652 {
653 uint32_t result=0;
654
655 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
656 return(result);
657 }
658
659 /**
660 * @brief Reverse bit order of value
661 *
662 * @param value value to reverse
663 * @return reversed value
664 *
665 * Reverse bit order of value
666 */
667 uint32_t __RBIT(uint32_t value)
668 {
669 uint32_t result=0;
670
671 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
672 return(result);
673 }
674
675 /**
676 * @brief LDR Exclusive (8 bit)
677 *
678 * @param *addr address pointer
679 * @return value of (*address)
680 *
681 * Exclusive LDR command for 8 bit value
682 */
683 uint8_t __LDREXB(uint8_t *addr)
684 {
685 uint8_t result=0;
686
687 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
688 return(result);
689 }
690
691 /**
692 * @brief LDR Exclusive (16 bit)
693 *
694 * @param *addr address pointer
695 * @return value of (*address)
696 *
697 * Exclusive LDR command for 16 bit values
698 */
699 uint16_t __LDREXH(uint16_t *addr)
700 {
701 uint16_t result=0;
702
703 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
704 return(result);
705 }
706
707 /**
708 * @brief LDR Exclusive (32 bit)
709 *
710 * @param *addr address pointer
711 * @return value of (*address)
712 *
713 * Exclusive LDR command for 32 bit values
714 */
715 uint32_t __LDREXW(uint32_t *addr)
716 {
717 uint32_t result=0;
718
719 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
720 return(result);
721 }
722
723 /**
724 * @brief STR Exclusive (8 bit)
725 *
726 * @param value value to store
727 * @param *addr address pointer
728 * @return successful / failed
729 *
730 * Exclusive STR command for 8 bit values
731 */
732 uint32_t __STREXB(uint8_t value, uint8_t *addr)
733 {
734 uint32_t result=0;
735
736 __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
737 return(result);
738 }
739
740 /**
741 * @brief STR Exclusive (16 bit)
742 *
743 * @param value value to store
744 * @param *addr address pointer
745 * @return successful / failed
746 *
747 * Exclusive STR command for 16 bit values
748 */
749 uint32_t __STREXH(uint16_t value, uint16_t *addr)
750 {
751 uint32_t result=0;
752
753 __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
754 return(result);
755 }
756
757 /**
758 * @brief STR Exclusive (32 bit)
759 *
760 * @param value value to store
761 * @param *addr address pointer
762 * @return successful / failed
763 *
764 * Exclusive STR command for 32 bit values
765 */
766 uint32_t __STREXW(uint32_t value, uint32_t *addr)
767 {
768 uint32_t result=0;
769
770 __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
771 return(result);
772 }
773
774
775 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
776 /* TASKING carm specific functions */
777
778 /*
779 * The CMSIS functions have been implemented as intrinsics in the compiler.
780 * Please use "carm -?i" to get an up to date list of all instrinsics,
781 * Including the CMSIS ones.
782 */
783
784 #endif
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1 core_cm3.o: /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/core_cm3.c
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1 /**************************************************************************//**
2 * @file core_cm3.h
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4 * @version V1.30
5 * @date 30. October 2009
6 *
7 * @note
8 * Copyright (C) 2009 ARM Limited. All rights reserved.
9 *
10 * @par
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * @par
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 *
22 ******************************************************************************/
23
24 #ifndef __CM3_CORE_H__
25 #define __CM3_CORE_H__
26
27 /** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
28 *
29 * List of Lint messages which will be suppressed and not shown:
30 * - Error 10: \n
31 * register uint32_t __regBasePri __asm("basepri"); \n
32 * Error 10: Expecting ';'
33 * .
34 * - Error 530: \n
35 * return(__regBasePri); \n
36 * Warning 530: Symbol '__regBasePri' (line 264) not initialized
37 * .
38 * - Error 550: \n
39 * __regBasePri = (basePri & 0x1ff); \n
40 * Warning 550: Symbol '__regBasePri' (line 271) not accessed
41 * .
42 * - Error 754: \n
43 * uint32_t RESERVED0[24]; \n
44 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
45 * .
46 * - Error 750: \n
47 * #define __CM3_CORE_H__ \n
48 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
49 * .
50 * - Error 528: \n
51 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
52 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
53 * .
54 * - Error 751: \n
55 * } InterruptType_Type; \n
56 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
57 * .
58 * Note: To re-enable a Message, insert a space before 'lint' *
59 *
60 */
61
62 /*lint -save */
63 /*lint -e10 */
64 /*lint -e530 */
65 /*lint -e550 */
66 /*lint -e754 */
67 /*lint -e750 */
68 /*lint -e528 */
69 /*lint -e751 */
70
71
72 /** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
73 This file defines all structures and symbols for CMSIS core:
74 - CMSIS version number
75 - Cortex-M core registers and bitfields
76 - Cortex-M core peripheral base address
77 @{
78 */
79
80 #ifdef __cplusplus
81 extern "C" {
82 #endif
83
84 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
85 #define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
86 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
87
88 #define __CORTEX_M (0x03) /*!< Cortex core */
89
90 #include <stdint.h> /* Include standard types */
91
92 #if defined (__ICCARM__)
93 #include <intrinsics.h> /* IAR Intrinsics */
94 #endif
95
96
97 #ifndef __NVIC_PRIO_BITS
98 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
99 #endif
100
101
102
103
104 /**
105 * IO definitions
106 *
107 * define access restrictions to peripheral registers
108 */
109
110 #ifdef __cplusplus
111 #define __I volatile /*!< defines 'read only' permissions */
112 #else
113 #define __I volatile const /*!< defines 'read only' permissions */
114 #endif
115 #define __O volatile /*!< defines 'write only' permissions */
116 #define __IO volatile /*!< defines 'read / write' permissions */
117
118
119
120 /*******************************************************************************
121 * Register Abstraction
122 ******************************************************************************/
123 /** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
124 @{
125 */
126
127
128 /** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
129 memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
130 @{
131 */
132 typedef struct
133 {
134 __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
135 uint32_t RESERVED0[24];
136 __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
137 uint32_t RSERVED1[24];
138 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
139 uint32_t RESERVED2[24];
140 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
141 uint32_t RESERVED3[24];
142 __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
143 uint32_t RESERVED4[56];
144 __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
145 uint32_t RESERVED5[644];
146 __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
147 } NVIC_Type;
148 /*@}*/ /* end of group CMSIS_CM3_NVIC */
149
150
151 /** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
152 memory mapped structure for System Control Block (SCB)
153 @{
154 */
155 typedef struct
156 {
157 __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
158 __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
159 __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
160 __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
161 __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
162 __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
163 __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
164 __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
165 __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
166 __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
167 __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
168 __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
169 __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
170 __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
171 __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
172 __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
173 __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
174 __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
175 __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
176 } SCB_Type;
177
178 /* SCB CPUID Register Definitions */
179 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
180 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
181
182 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
183 #define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
184
185 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
186 #define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
187
188 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
189 #define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
190
191 /* SCB Interrupt Control State Register Definitions */
192 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
193 #define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
194
195 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
196 #define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
197
198 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
199 #define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
200
201 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
202 #define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
203
204 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
205 #define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
206
207 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
208 #define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
209
210 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
211 #define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
212
213 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
214 #define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
215
216 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
217 #define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
218
219 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
220 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
221
222 /* SCB Interrupt Control State Register Definitions */
223 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
224 #define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
225
226 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
227 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
228
229 /* SCB Application Interrupt and Reset Control Register Definitions */
230 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
231 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
232
233 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
234 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
235
236 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
237 #define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
238
239 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
240 #define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
241
242 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
243 #define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
244
245 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
246 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
247
248 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
249 #define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
250
251 /* SCB System Control Register Definitions */
252 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
253 #define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
254
255 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
256 #define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
257
258 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
259 #define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
260
261 /* SCB Configuration Control Register Definitions */
262 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
263 #define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
264
265 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
266 #define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
267
268 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
269 #define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
270
271 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
272 #define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
273
274 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
275 #define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
276
277 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
278 #define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
279
280 /* SCB System Handler Control and State Register Definitions */
281 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
282 #define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
283
284 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
285 #define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
286
287 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
288 #define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
289
290 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
291 #define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
292
293 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
294 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
295
296 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
297 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
298
299 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
300 #define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
301
302 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
303 #define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
304
305 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
306 #define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
307
308 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
309 #define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
310
311 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
312 #define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
313
314 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
315 #define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
316
317 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
318 #define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
319
320 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
321 #define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
322
323 /* SCB Configurable Fault Status Registers Definitions */
324 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
325 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
326
327 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
328 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
329
330 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
331 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
332
333 /* SCB Hard Fault Status Registers Definitions */
334 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
335 #define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
336
337 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
338 #define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
339
340 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
341 #define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
342
343 /* SCB Debug Fault Status Register Definitions */
344 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
345 #define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
346
347 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
348 #define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
349
350 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
351 #define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
352
353 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
354 #define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
355
356 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
357 #define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
358 /*@}*/ /* end of group CMSIS_CM3_SCB */
359
360
361 /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
362 memory mapped structure for SysTick
363 @{
364 */
365 typedef struct
366 {
367 __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
368 __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
369 __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
370 __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
371 } SysTick_Type;
372
373 /* SysTick Control / Status Register Definitions */
374 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
375 #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
376
377 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
378 #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
379
380 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
381 #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
382
383 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
384 #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
385
386 /* SysTick Reload Register Definitions */
387 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
388 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
389
390 /* SysTick Current Register Definitions */
391 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
392 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
393
394 /* SysTick Calibration Register Definitions */
395 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
396 #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
397
398 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
399 #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
400
401 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
402 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
403 /*@}*/ /* end of group CMSIS_CM3_SysTick */
404
405
406 /** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
407 memory mapped structure for Instrumentation Trace Macrocell (ITM)
408 @{
409 */
410 typedef struct
411 {
412 __O union
413 {
414 __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
415 __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
416 __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
417 } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
418 uint32_t RESERVED0[864];
419 __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
420 uint32_t RESERVED1[15];
421 __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
422 uint32_t RESERVED2[15];
423 __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
424 uint32_t RESERVED3[29];
425 __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
426 __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
427 __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
428 uint32_t RESERVED4[43];
429 __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
430 __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
431 uint32_t RESERVED5[6];
432 __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
433 __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
434 __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
435 __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
436 __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
437 __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
438 __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
439 __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
440 __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
441 __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
442 __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
443 __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
444 } ITM_Type;
445
446 /* ITM Trace Privilege Register Definitions */
447 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
448 #define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
449
450 /* ITM Trace Control Register Definitions */
451 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
452 #define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
453
454 #define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
455 #define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
456
457 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
458 #define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
459
460 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
461 #define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
462
463 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
464 #define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
465
466 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
467 #define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
468
469 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
470 #define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
471
472 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
473 #define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
474
475 /* ITM Integration Write Register Definitions */
476 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
477 #define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
478
479 /* ITM Integration Read Register Definitions */
480 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
481 #define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
482
483 /* ITM Integration Mode Control Register Definitions */
484 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
485 #define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
486
487 /* ITM Lock Status Register Definitions */
488 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
489 #define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
490
491 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
492 #define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
493
494 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
495 #define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
496 /*@}*/ /* end of group CMSIS_CM3_ITM */
497
498
499 /** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
500 memory mapped structure for Interrupt Type
501 @{
502 */
503 typedef struct
504 {
505 uint32_t RESERVED0;
506 __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
507 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
508 __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
509 #else
510 uint32_t RESERVED1;
511 #endif
512 } InterruptType_Type;
513
514 /* Interrupt Controller Type Register Definitions */
515 #define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
516 #define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
517
518 /* Auxiliary Control Register Definitions */
519 #define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
520 #define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
521
522 #define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
523 #define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
524
525 #define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
526 #define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
527 /*@}*/ /* end of group CMSIS_CM3_InterruptType */
528
529
530 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
531 /** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
532 memory mapped structure for Memory Protection Unit (MPU)
533 @{
534 */
535 typedef struct
536 {
537 __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
538 __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
539 __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
540 __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
541 __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
542 __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
543 __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
544 __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
545 __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
546 __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
547 __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
548 } MPU_Type;
549
550 /* MPU Type Register */
551 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
552 #define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
553
554 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
555 #define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
556
557 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
558 #define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
559
560 /* MPU Control Register */
561 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
562 #define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
563
564 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
565 #define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
566
567 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
568 #define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
569
570 /* MPU Region Number Register */
571 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
572 #define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
573
574 /* MPU Region Base Address Register */
575 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
576 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
577
578 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
579 #define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
580
581 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
582 #define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
583
584 /* MPU Region Attribute and Size Register */
585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
586 #define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
587
588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
589 #define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
590
591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
592 #define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
593
594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
595 #define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
596
597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
598 #define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
599
600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
601 #define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
602
603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
604 #define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
605
606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
607 #define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
608
609 #define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
610 #define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
611
612 /*@}*/ /* end of group CMSIS_CM3_MPU */
613 #endif
614
615
616 /** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
617 memory mapped structure for Core Debug Register
618 @{
619 */
620 typedef struct
621 {
622 __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
623 __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
624 __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
625 __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
626 } CoreDebug_Type;
627
628 /* Debug Halting Control and Status Register */
629 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
630 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
631
632 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
633 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
634
635 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
636 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
637
638 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
639 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
640
641 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
642 #define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
643
644 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
645 #define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
646
647 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
648 #define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
649
650 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
651 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
652
653 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
654 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
655
656 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
657 #define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
658
659 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
660 #define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
661
662 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
663 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
664
665 /* Debug Core Register Selector Register */
666 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
667 #define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
668
669 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
670 #define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
671
672 /* Debug Exception and Monitor Control Register */
673 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
674 #define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
675
676 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
677 #define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
678
679 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
680 #define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
681
682 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
683 #define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
684
685 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
686 #define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
687
688 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
689 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
690
691 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
692 #define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
693
694 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
695 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
696
697 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
698 #define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
699
700 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
701 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
702
703 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
704 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
705
706 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
707 #define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
708
709 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
710 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
711 /*@}*/ /* end of group CMSIS_CM3_CoreDebug */
712
713
714 /* Memory mapping of Cortex-M3 Hardware */
715 #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
716 #define ITM_BASE (0xE0000000) /*!< ITM Base Address */
717 #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
718 #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
719 #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
720 #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
721
722 #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
723 #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
724 #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
725 #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
726 #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
727 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
728
729 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
730 #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
731 #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
732 #endif
733
734 /*@}*/ /* end of group CMSIS_CM3_core_register */
735
736
737 /*******************************************************************************
738 * Hardware Abstraction Layer
739 ******************************************************************************/
740
741 #if defined ( __CC_ARM )
742 #define __ASM __asm /*!< asm keyword for ARM Compiler */
743 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
744
745 #elif defined ( __ICCARM__ )
746 #define __ASM __asm /*!< asm keyword for IAR Compiler */
747 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
748
749 #elif defined ( __GNUC__ )
750 #define __ASM __asm /*!< asm keyword for GNU Compiler */
751 #define __INLINE inline /*!< inline keyword for GNU Compiler */
752
753 #elif defined ( __TASKING__ )
754 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
755 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
756
757 #endif
758
759
760 /* ################### Compiler specific Intrinsics ########################### */
761
762 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
763 /* ARM armcc specific functions */
764
765 #define __enable_fault_irq __enable_fiq
766 #define __disable_fault_irq __disable_fiq
767
768 #define __NOP __nop
769 #define __WFI __wfi
770 #define __WFE __wfe
771 #define __SEV __sev
772 #define __ISB() __isb(0)
773 #define __DSB() __dsb(0)
774 #define __DMB() __dmb(0)
775 #define __REV __rev
776 #define __RBIT __rbit
777 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
778 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
779 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
780 #define __STREXB(value, ptr) __strex(value, ptr)
781 #define __STREXH(value, ptr) __strex(value, ptr)
782 #define __STREXW(value, ptr) __strex(value, ptr)
783
784
785 /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
786 /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
787 /* intrinsic void __enable_irq(); */
788 /* intrinsic void __disable_irq(); */
789
790
791 /**
792 * @brief Return the Process Stack Pointer
793 *
794 * @return ProcessStackPointer
795 *
796 * Return the actual process stack pointer
797 */
798 extern uint32_t __get_PSP(void);
799
800 /**
801 * @brief Set the Process Stack Pointer
802 *
803 * @param topOfProcStack Process Stack Pointer
804 *
805 * Assign the value ProcessStackPointer to the MSP
806 * (process stack pointer) Cortex processor register
807 */
808 extern void __set_PSP(uint32_t topOfProcStack);
809
810 /**
811 * @brief Return the Main Stack Pointer
812 *
813 * @return Main Stack Pointer
814 *
815 * Return the current value of the MSP (main stack pointer)
816 * Cortex processor register
817 */
818 extern uint32_t __get_MSP(void);
819
820 /**
821 * @brief Set the Main Stack Pointer
822 *
823 * @param topOfMainStack Main Stack Pointer
824 *
825 * Assign the value mainStackPointer to the MSP
826 * (main stack pointer) Cortex processor register
827 */
828 extern void __set_MSP(uint32_t topOfMainStack);
829
830 /**
831 * @brief Reverse byte order in unsigned short value
832 *
833 * @param value value to reverse
834 * @return reversed value
835 *
836 * Reverse byte order in unsigned short value
837 */
838 extern uint32_t __REV16(uint16_t value);
839
840 /**
841 * @brief Reverse byte order in signed short value with sign extension to integer
842 *
843 * @param value value to reverse
844 * @return reversed value
845 *
846 * Reverse byte order in signed short value with sign extension to integer
847 */
848 extern int32_t __REVSH(int16_t value);
849
850
851 #if (__ARMCC_VERSION < 400000)
852
853 /**
854 * @brief Remove the exclusive lock created by ldrex
855 *
856 * Removes the exclusive lock which is created by ldrex.
857 */
858 extern void __CLREX(void);
859
860 /**
861 * @brief Return the Base Priority value
862 *
863 * @return BasePriority
864 *
865 * Return the content of the base priority register
866 */
867 extern uint32_t __get_BASEPRI(void);
868
869 /**
870 * @brief Set the Base Priority value
871 *
872 * @param basePri BasePriority
873 *
874 * Set the base priority register
875 */
876 extern void __set_BASEPRI(uint32_t basePri);
877
878 /**
879 * @brief Return the Priority Mask value
880 *
881 * @return PriMask
882 *
883 * Return state of the priority mask bit from the priority mask register
884 */
885 extern uint32_t __get_PRIMASK(void);
886
887 /**
888 * @brief Set the Priority Mask value
889 *
890 * @param priMask PriMask
891 *
892 * Set the priority mask bit in the priority mask register
893 */
894 extern void __set_PRIMASK(uint32_t priMask);
895
896 /**
897 * @brief Return the Fault Mask value
898 *
899 * @return FaultMask
900 *
901 * Return the content of the fault mask register
902 */
903 extern uint32_t __get_FAULTMASK(void);
904
905 /**
906 * @brief Set the Fault Mask value
907 *
908 * @param faultMask faultMask value
909 *
910 * Set the fault mask register
911 */
912 extern void __set_FAULTMASK(uint32_t faultMask);
913
914 /**
915 * @brief Return the Control Register value
916 *
917 * @return Control value
918 *
919 * Return the content of the control register
920 */
921 extern uint32_t __get_CONTROL(void);
922
923 /**
924 * @brief Set the Control Register value
925 *
926 * @param control Control value
927 *
928 * Set the control register
929 */
930 extern void __set_CONTROL(uint32_t control);
931
932 #else /* (__ARMCC_VERSION >= 400000) */
933
934 /**
935 * @brief Remove the exclusive lock created by ldrex
936 *
937 * Removes the exclusive lock which is created by ldrex.
938 */
939 #define __CLREX __clrex
940
941 /**
942 * @brief Return the Base Priority value
943 *
944 * @return BasePriority
945 *
946 * Return the content of the base priority register
947 */
948 static __INLINE uint32_t __get_BASEPRI(void)
949 {
950 register uint32_t __regBasePri __ASM("basepri");
951 return(__regBasePri);
952 }
953
954 /**
955 * @brief Set the Base Priority value
956 *
957 * @param basePri BasePriority
958 *
959 * Set the base priority register
960 */
961 static __INLINE void __set_BASEPRI(uint32_t basePri)
962 {
963 register uint32_t __regBasePri __ASM("basepri");
964 __regBasePri = (basePri & 0xff);
965 }
966
967 /**
968 * @brief Return the Priority Mask value
969 *
970 * @return PriMask
971 *
972 * Return state of the priority mask bit from the priority mask register
973 */
974 static __INLINE uint32_t __get_PRIMASK(void)
975 {
976 register uint32_t __regPriMask __ASM("primask");
977 return(__regPriMask);
978 }
979
980 /**
981 * @brief Set the Priority Mask value
982 *
983 * @param priMask PriMask
984 *
985 * Set the priority mask bit in the priority mask register
986 */
987 static __INLINE void __set_PRIMASK(uint32_t priMask)
988 {
989 register uint32_t __regPriMask __ASM("primask");
990 __regPriMask = (priMask);
991 }
992
993 /**
994 * @brief Return the Fault Mask value
995 *
996 * @return FaultMask
997 *
998 * Return the content of the fault mask register
999 */
1000 static __INLINE uint32_t __get_FAULTMASK(void)
1001 {
1002 register uint32_t __regFaultMask __ASM("faultmask");
1003 return(__regFaultMask);
1004 }
1005
1006 /**
1007 * @brief Set the Fault Mask value
1008 *
1009 * @param faultMask faultMask value
1010 *
1011 * Set the fault mask register
1012 */
1013 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
1014 {
1015 register uint32_t __regFaultMask __ASM("faultmask");
1016 __regFaultMask = (faultMask & 1);
1017 }
1018
1019 /**
1020 * @brief Return the Control Register value
1021 *
1022 * @return Control value
1023 *
1024 * Return the content of the control register
1025 */
1026 static __INLINE uint32_t __get_CONTROL(void)
1027 {
1028 register uint32_t __regControl __ASM("control");
1029 return(__regControl);
1030 }
1031
1032 /**
1033 * @brief Set the Control Register value
1034 *
1035 * @param control Control value
1036 *
1037 * Set the control register
1038 */
1039 static __INLINE void __set_CONTROL(uint32_t control)
1040 {
1041 register uint32_t __regControl __ASM("control");
1042 __regControl = control;
1043 }
1044
1045 #endif /* __ARMCC_VERSION */
1046
1047
1048
1049 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
1050 /* IAR iccarm specific functions */
1051
1052 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
1053 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
1054
1055 static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
1056 static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
1057
1058 #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
1059 static __INLINE void __WFI() { __ASM ("wfi"); }
1060 static __INLINE void __WFE() { __ASM ("wfe"); }
1061 static __INLINE void __SEV() { __ASM ("sev"); }
1062 static __INLINE void __CLREX() { __ASM ("clrex"); }
1063
1064 /* intrinsic void __ISB(void) */
1065 /* intrinsic void __DSB(void) */
1066 /* intrinsic void __DMB(void) */
1067 /* intrinsic void __set_PRIMASK(); */
1068 /* intrinsic void __get_PRIMASK(); */
1069 /* intrinsic void __set_FAULTMASK(); */
1070 /* intrinsic void __get_FAULTMASK(); */
1071 /* intrinsic uint32_t __REV(uint32_t value); */
1072 /* intrinsic uint32_t __REVSH(uint32_t value); */
1073 /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
1074 /* intrinsic unsigned long __LDREX(unsigned long *); */
1075
1076
1077 /**
1078 * @brief Return the Process Stack Pointer
1079 *
1080 * @return ProcessStackPointer
1081 *
1082 * Return the actual process stack pointer
1083 */
1084 extern uint32_t __get_PSP(void);
1085
1086 /**
1087 * @brief Set the Process Stack Pointer
1088 *
1089 * @param topOfProcStack Process Stack Pointer
1090 *
1091 * Assign the value ProcessStackPointer to the MSP
1092 * (process stack pointer) Cortex processor register
1093 */
1094 extern void __set_PSP(uint32_t topOfProcStack);
1095
1096 /**
1097 * @brief Return the Main Stack Pointer
1098 *
1099 * @return Main Stack Pointer
1100 *
1101 * Return the current value of the MSP (main stack pointer)
1102 * Cortex processor register
1103 */
1104 extern uint32_t __get_MSP(void);
1105
1106 /**
1107 * @brief Set the Main Stack Pointer
1108 *
1109 * @param topOfMainStack Main Stack Pointer
1110 *
1111 * Assign the value mainStackPointer to the MSP
1112 * (main stack pointer) Cortex processor register
1113 */
1114 extern void __set_MSP(uint32_t topOfMainStack);
1115
1116 /**
1117 * @brief Reverse byte order in unsigned short value
1118 *
1119 * @param value value to reverse
1120 * @return reversed value
1121 *
1122 * Reverse byte order in unsigned short value
1123 */
1124 extern uint32_t __REV16(uint16_t value);
1125
1126 /**
1127 * @brief Reverse bit order of value
1128 *
1129 * @param value value to reverse
1130 * @return reversed value
1131 *
1132 * Reverse bit order of value
1133 */
1134 extern uint32_t __RBIT(uint32_t value);
1135
1136 /**
1137 * @brief LDR Exclusive (8 bit)
1138 *
1139 * @param *addr address pointer
1140 * @return value of (*address)
1141 *
1142 * Exclusive LDR command for 8 bit values)
1143 */
1144 extern uint8_t __LDREXB(uint8_t *addr);
1145
1146 /**
1147 * @brief LDR Exclusive (16 bit)
1148 *
1149 * @param *addr address pointer
1150 * @return value of (*address)
1151 *
1152 * Exclusive LDR command for 16 bit values
1153 */
1154 extern uint16_t __LDREXH(uint16_t *addr);
1155
1156 /**
1157 * @brief LDR Exclusive (32 bit)
1158 *
1159 * @param *addr address pointer
1160 * @return value of (*address)
1161 *
1162 * Exclusive LDR command for 32 bit values
1163 */
1164 extern uint32_t __LDREXW(uint32_t *addr);
1165
1166 /**
1167 * @brief STR Exclusive (8 bit)
1168 *
1169 * @param value value to store
1170 * @param *addr address pointer
1171 * @return successful / failed
1172 *
1173 * Exclusive STR command for 8 bit values
1174 */
1175 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
1176
1177 /**
1178 * @brief STR Exclusive (16 bit)
1179 *
1180 * @param value value to store
1181 * @param *addr address pointer
1182 * @return successful / failed
1183 *
1184 * Exclusive STR command for 16 bit values
1185 */
1186 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
1187
1188 /**
1189 * @brief STR Exclusive (32 bit)
1190 *
1191 * @param value value to store
1192 * @param *addr address pointer
1193 * @return successful / failed
1194 *
1195 * Exclusive STR command for 32 bit values
1196 */
1197 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
1198
1199
1200
1201 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
1202 /* GNU gcc specific functions */
1203
1204 static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
1205 static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
1206
1207 static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
1208 static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
1209
1210 static __INLINE void __NOP() { __ASM volatile ("nop"); }
1211 static __INLINE void __WFI() { __ASM volatile ("wfi"); }
1212 static __INLINE void __WFE() { __ASM volatile ("wfe"); }
1213 static __INLINE void __SEV() { __ASM volatile ("sev"); }
1214 static __INLINE void __ISB() { __ASM volatile ("isb"); }
1215 static __INLINE void __DSB() { __ASM volatile ("dsb"); }
1216 static __INLINE void __DMB() { __ASM volatile ("dmb"); }
1217 static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
1218
1219
1220 /**
1221 * @brief Return the Process Stack Pointer
1222 *
1223 * @return ProcessStackPointer
1224 *
1225 * Return the actual process stack pointer
1226 */
1227 extern uint32_t __get_PSP(void);
1228
1229 /**
1230 * @brief Set the Process Stack Pointer
1231 *
1232 * @param topOfProcStack Process Stack Pointer
1233 *
1234 * Assign the value ProcessStackPointer to the MSP
1235 * (process stack pointer) Cortex processor register
1236 */
1237 extern void __set_PSP(uint32_t topOfProcStack);
1238
1239 /**
1240 * @brief Return the Main Stack Pointer
1241 *
1242 * @return Main Stack Pointer
1243 *
1244 * Return the current value of the MSP (main stack pointer)
1245 * Cortex processor register
1246 */
1247 extern uint32_t __get_MSP(void);
1248
1249 /**
1250 * @brief Set the Main Stack Pointer
1251 *
1252 * @param topOfMainStack Main Stack Pointer
1253 *
1254 * Assign the value mainStackPointer to the MSP
1255 * (main stack pointer) Cortex processor register
1256 */
1257 extern void __set_MSP(uint32_t topOfMainStack);
1258
1259 /**
1260 * @brief Return the Base Priority value
1261 *
1262 * @return BasePriority
1263 *
1264 * Return the content of the base priority register
1265 */
1266 extern uint32_t __get_BASEPRI(void);
1267
1268 /**
1269 * @brief Set the Base Priority value
1270 *
1271 * @param basePri BasePriority
1272 *
1273 * Set the base priority register
1274 */
1275 extern void __set_BASEPRI(uint32_t basePri);
1276
1277 /**
1278 * @brief Return the Priority Mask value
1279 *
1280 * @return PriMask
1281 *
1282 * Return state of the priority mask bit from the priority mask register
1283 */
1284 extern uint32_t __get_PRIMASK(void);
1285
1286 /**
1287 * @brief Set the Priority Mask value
1288 *
1289 * @param priMask PriMask
1290 *
1291 * Set the priority mask bit in the priority mask register
1292 */
1293 extern void __set_PRIMASK(uint32_t priMask);
1294
1295 /**
1296 * @brief Return the Fault Mask value
1297 *
1298 * @return FaultMask
1299 *
1300 * Return the content of the fault mask register
1301 */
1302 extern uint32_t __get_FAULTMASK(void);
1303
1304 /**
1305 * @brief Set the Fault Mask value
1306 *
1307 * @param faultMask faultMask value
1308 *
1309 * Set the fault mask register
1310 */
1311 extern void __set_FAULTMASK(uint32_t faultMask);
1312
1313 /**
1314 * @brief Return the Control Register value
1315 *
1316 * @return Control value
1317 *
1318 * Return the content of the control register
1319 */
1320 extern uint32_t __get_CONTROL(void);
1321
1322 /**
1323 * @brief Set the Control Register value
1324 *
1325 * @param control Control value
1326 *
1327 * Set the control register
1328 */
1329 extern void __set_CONTROL(uint32_t control);
1330
1331 /**
1332 * @brief Reverse byte order in integer value
1333 *
1334 * @param value value to reverse
1335 * @return reversed value
1336 *
1337 * Reverse byte order in integer value
1338 */
1339 extern uint32_t __REV(uint32_t value);
1340
1341 /**
1342 * @brief Reverse byte order in unsigned short value
1343 *
1344 * @param value value to reverse
1345 * @return reversed value
1346 *
1347 * Reverse byte order in unsigned short value
1348 */
1349 extern uint32_t __REV16(uint16_t value);
1350
1351 /**
1352 * @brief Reverse byte order in signed short value with sign extension to integer
1353 *
1354 * @param value value to reverse
1355 * @return reversed value
1356 *
1357 * Reverse byte order in signed short value with sign extension to integer
1358 */
1359 extern int32_t __REVSH(int16_t value);
1360
1361 /**
1362 * @brief Reverse bit order of value
1363 *
1364 * @param value value to reverse
1365 * @return reversed value
1366 *
1367 * Reverse bit order of value
1368 */
1369 extern uint32_t __RBIT(uint32_t value);
1370
1371 /**
1372 * @brief LDR Exclusive (8 bit)
1373 *
1374 * @param *addr address pointer
1375 * @return value of (*address)
1376 *
1377 * Exclusive LDR command for 8 bit value
1378 */
1379 extern uint8_t __LDREXB(uint8_t *addr);
1380
1381 /**
1382 * @brief LDR Exclusive (16 bit)
1383 *
1384 * @param *addr address pointer
1385 * @return value of (*address)
1386 *
1387 * Exclusive LDR command for 16 bit values
1388 */
1389 extern uint16_t __LDREXH(uint16_t *addr);
1390
1391 /**
1392 * @brief LDR Exclusive (32 bit)
1393 *
1394 * @param *addr address pointer
1395 * @return value of (*address)
1396 *
1397 * Exclusive LDR command for 32 bit values
1398 */
1399 extern uint32_t __LDREXW(uint32_t *addr);
1400
1401 /**
1402 * @brief STR Exclusive (8 bit)
1403 *
1404 * @param value value to store
1405 * @param *addr address pointer
1406 * @return successful / failed
1407 *
1408 * Exclusive STR command for 8 bit values
1409 */
1410 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
1411
1412 /**
1413 * @brief STR Exclusive (16 bit)
1414 *
1415 * @param value value to store
1416 * @param *addr address pointer
1417 * @return successful / failed
1418 *
1419 * Exclusive STR command for 16 bit values
1420 */
1421 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
1422
1423 /**
1424 * @brief STR Exclusive (32 bit)
1425 *
1426 * @param value value to store
1427 * @param *addr address pointer
1428 * @return successful / failed
1429 *
1430 * Exclusive STR command for 32 bit values
1431 */
1432 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
1433
1434
1435 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
1436 /* TASKING carm specific functions */
1437
1438 /*
1439 * The CMSIS functions have been implemented as intrinsics in the compiler.
1440 * Please use "carm -?i" to get an up to date list of all instrinsics,
1441 * Including the CMSIS ones.
1442 */
1443
1444 #endif
1445
1446
1447 /** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
1448 Core Function Interface containing:
1449 - Core NVIC Functions
1450 - Core SysTick Functions
1451 - Core Reset Functions
1452 */
1453 /*@{*/
1454
1455 /* ########################## NVIC functions #################################### */
1456
1457 /**
1458 * @brief Set the Priority Grouping in NVIC Interrupt Controller
1459 *
1460 * @param PriorityGroup is priority grouping field
1461 *
1462 * Set the priority grouping field using the required unlock sequence.
1463 * The parameter priority_grouping is assigned to the field
1464 * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
1465 * In case of a conflict between priority grouping and available
1466 * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1467 */
1468 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1469 {
1470 uint32_t reg_value;
1471 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1472
1473 reg_value = SCB->AIRCR; /* read old register configuration */
1474 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1475 reg_value = (reg_value |
1476 (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1477 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1478 SCB->AIRCR = reg_value;
1479 }
1480
1481 /**
1482 * @brief Get the Priority Grouping from NVIC Interrupt Controller
1483 *
1484 * @return priority grouping field
1485 *
1486 * Get the priority grouping from NVIC Interrupt Controller.
1487 * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
1488 */
1489 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
1490 {
1491 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1492 }
1493
1494 /**
1495 * @brief Enable Interrupt in NVIC Interrupt Controller
1496 *
1497 * @param IRQn The positive number of the external interrupt to enable
1498 *
1499 * Enable a device specific interupt in the NVIC interrupt controller.
1500 * The interrupt number cannot be a negative value.
1501 */
1502 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1503 {
1504 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1505 }
1506
1507 /**
1508 * @brief Disable the interrupt line for external interrupt specified
1509 *
1510 * @param IRQn The positive number of the external interrupt to disable
1511 *
1512 * Disable a device specific interupt in the NVIC interrupt controller.
1513 * The interrupt number cannot be a negative value.
1514 */
1515 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1516 {
1517 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1518 }
1519
1520 /**
1521 * @brief Read the interrupt pending bit for a device specific interrupt source
1522 *
1523 * @param IRQn The number of the device specifc interrupt
1524 * @return 1 = interrupt pending, 0 = interrupt not pending
1525 *
1526 * Read the pending register in NVIC and return 1 if its status is pending,
1527 * otherwise it returns 0
1528 */
1529 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1530 {
1531 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1532 }
1533
1534 /**
1535 * @brief Set the pending bit for an external interrupt
1536 *
1537 * @param IRQn The number of the interrupt for set pending
1538 *
1539 * Set the pending bit for the specified interrupt.
1540 * The interrupt number cannot be a negative value.
1541 */
1542 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1543 {
1544 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1545 }
1546
1547 /**
1548 * @brief Clear the pending bit for an external interrupt
1549 *
1550 * @param IRQn The number of the interrupt for clear pending
1551 *
1552 * Clear the pending bit for the specified interrupt.
1553 * The interrupt number cannot be a negative value.
1554 */
1555 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1556 {
1557 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1558 }
1559
1560 /**
1561 * @brief Read the active bit for an external interrupt
1562 *
1563 * @param IRQn The number of the interrupt for read active bit
1564 * @return 1 = interrupt active, 0 = interrupt not active
1565 *
1566 * Read the active register in NVIC and returns 1 if its status is active,
1567 * otherwise it returns 0.
1568 */
1569 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1570 {
1571 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1572 }
1573
1574 /**
1575 * @brief Set the priority for an interrupt
1576 *
1577 * @param IRQn The number of the interrupt for set priority
1578 * @param priority The priority to set
1579 *
1580 * Set the priority for the specified interrupt. The interrupt
1581 * number can be positive to specify an external (device specific)
1582 * interrupt, or negative to specify an internal (core) interrupt.
1583 *
1584 * Note: The priority cannot be set for every core interrupt.
1585 */
1586 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1587 {
1588 if(IRQn < 0) {
1589 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
1590 else {
1591 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1592 }
1593
1594 /**
1595 * @brief Read the priority for an interrupt
1596 *
1597 * @param IRQn The number of the interrupt for get priority
1598 * @return The priority for the interrupt
1599 *
1600 * Read the priority for the specified interrupt. The interrupt
1601 * number can be positive to specify an external (device specific)
1602 * interrupt, or negative to specify an internal (core) interrupt.
1603 *
1604 * The returned priority value is automatically aligned to the implemented
1605 * priority bits of the microcontroller.
1606 *
1607 * Note: The priority cannot be set for every core interrupt.
1608 */
1609 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1610 {
1611
1612 if(IRQn < 0) {
1613 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
1614 else {
1615 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1616 }
1617
1618
1619 /**
1620 * @brief Encode the priority for an interrupt
1621 *
1622 * @param PriorityGroup The used priority group
1623 * @param PreemptPriority The preemptive priority value (starting from 0)
1624 * @param SubPriority The sub priority value (starting from 0)
1625 * @return The encoded priority for the interrupt
1626 *
1627 * Encode the priority for an interrupt with the given priority group,
1628 * preemptive priority value and sub priority value.
1629 * In case of a conflict between priority grouping and available
1630 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1631 *
1632 * The returned priority value can be used for NVIC_SetPriority(...) function
1633 */
1634 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1635 {
1636 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1637 uint32_t PreemptPriorityBits;
1638 uint32_t SubPriorityBits;
1639
1640 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1641 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1642
1643 return (
1644 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1645 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1646 );
1647 }
1648
1649
1650 /**
1651 * @brief Decode the priority of an interrupt
1652 *
1653 * @param Priority The priority for the interrupt
1654 * @param PriorityGroup The used priority group
1655 * @param pPreemptPriority The preemptive priority value (starting from 0)
1656 * @param pSubPriority The sub priority value (starting from 0)
1657 *
1658 * Decode an interrupt priority value with the given priority group to
1659 * preemptive priority value and sub priority value.
1660 * In case of a conflict between priority grouping and available
1661 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1662 *
1663 * The priority value can be retrieved with NVIC_GetPriority(...) function
1664 */
1665 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1666 {
1667 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1668 uint32_t PreemptPriorityBits;
1669 uint32_t SubPriorityBits;
1670
1671 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1672 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1673
1674 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1675 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1676 }
1677
1678
1679
1680 /* ################################## SysTick function ############################################ */
1681
1682 #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
1683
1684 /**
1685 * @brief Initialize and start the SysTick counter and its interrupt.
1686 *
1687 * @param ticks number of ticks between two interrupts
1688 * @return 1 = failed, 0 = successful
1689 *
1690 * Initialise the system tick timer and its interrupt and start the
1691 * system tick timer / counter in free running mode to generate
1692 * periodical interrupts.
1693 */
1694 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
1695 {
1696 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1697
1698 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
1699 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
1700 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1701 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1702 SysTick_CTRL_TICKINT_Msk |
1703 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1704 return (0); /* Function successful */
1705 }
1706
1707 #endif
1708
1709
1710
1711
1712 /* ################################## Reset function ############################################ */
1713
1714 /**
1715 * @brief Initiate a system reset request.
1716 *
1717 * Initiate a system reset request to reset the MCU
1718 */
1719 static __INLINE void NVIC_SystemReset(void)
1720 {
1721 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1722 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1723 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1724 __DSB(); /* Ensure completion of memory access */
1725 while(1); /* wait until reset */
1726 }
1727
1728 /*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
1729
1730
1731
1732 /* ##################################### Debug In/Output function ########################################### */
1733
1734 /** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
1735 Core Debug Interface containing:
1736 - Core Debug Receive / Transmit Functions
1737 - Core Debug Defines
1738 - Core Debug Variables
1739 */
1740 /*@{*/
1741
1742 extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
1743 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
1744
1745
1746 /**
1747 * @brief Outputs a character via the ITM channel 0
1748 *
1749 * @param ch character to output
1750 * @return character to output
1751 *
1752 * The function outputs a character via the ITM channel 0.
1753 * The function returns when no debugger is connected that has booked the output.
1754 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
1755 */
1756 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
1757 {
1758 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
1759 (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1760 (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
1761 {
1762 while (ITM->PORT[0].u32 == 0);
1763 ITM->PORT[0].u8 = (uint8_t) ch;
1764 }
1765 return (ch);
1766 }
1767
1768
1769 /**
1770 * @brief Inputs a character via variable ITM_RxBuffer
1771 *
1772 * @return received character, -1 = no character received
1773 *
1774 * The function inputs a character via variable ITM_RxBuffer.
1775 * The function returns when no debugger is connected that has booked the output.
1776 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
1777 */
1778 static __INLINE int ITM_ReceiveChar (void) {
1779 int ch = -1; /* no character available */
1780
1781 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1782 ch = ITM_RxBuffer;
1783 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1784 }
1785
1786 return (ch);
1787 }
1788
1789
1790 /**
1791 * @brief Check if a character via variable ITM_RxBuffer is available
1792 *
1793 * @return 1 = character available, 0 = no character available
1794 *
1795 * The function checks variable ITM_RxBuffer whether a character is available or not.
1796 * The function returns '1' if a character is available and '0' if no character is available.
1797 */
1798 static __INLINE int ITM_CheckChar (void) {
1799
1800 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1801 return (0); /* no character available */
1802 } else {
1803 return (1); /* character available */
1804 }
1805 }
1806
1807 /*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
1808
1809
1810 #ifdef __cplusplus
1811 }
1812 #endif
1813
1814 /*@}*/ /* end of group CMSIS_CM3_core_definitions */
1815
1816 #endif /* __CM3_CORE_H__ */
1817
1818 /*lint -restore */
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1 /****************************************************************************//**
2 * @file : startup_LPC17xx.c
3 * @brief : CMSIS Cortex-M3 Core Device Startup File
4 * @version : V1.01
5 * @date : 4. Feb. 2009
6 *
7 *----------------------------------------------------------------------------
8 *
9 * Copyright (C) 2009 ARM Limited. All rights reserved.
10 *
11 * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
20 *
21 ******************************************************************************/
22
23 // Mod by nio for the .fastcode part
24
25 #include "LPC17xx.h"
26
27 #define WEAK __attribute__ ((weak))
28 //*****************************************************************************
29 //
30 // Forward declaration of the default fault handlers.
31 //
32 //*****************************************************************************
33 /* System exception vector handler */
34 void WEAK Reset_Handler(void); /* Reset Handler */
35 void WEAK NMI_Handler(void); /* NMI Handler */
36 void WEAK HardFault_Handler(void); /* Hard Fault Handler */
37 void WEAK MemManage_Handler(void); /* MPU Fault Handler */
38 void WEAK BusFault_Handler(void); /* Bus Fault Handler */
39 void WEAK UsageFault_Handler(void); /* Usage Fault Handler */
40 void WEAK SVC_Handler(void); /* SVCall Handler */
41 void WEAK DebugMon_Handler(void); /* Debug Monitor Handler */
42 void WEAK PendSV_Handler(void); /* PendSV Handler */
43 void WEAK SysTick_Handler(void); /* SysTick Handler */
44
45 /* External interrupt vector handler */
46 void WEAK WDT_IRQHandler(void); /* Watchdog Timer */
47 void WEAK TIMER0_IRQHandler(void); /* Timer0 */
48 void WEAK TIMER1_IRQHandler(void); /* Timer1 */
49 void WEAK TIMER2_IRQHandler(void); /* Timer2 */
50 void WEAK TIMER3_IRQHandler(void); /* Timer3 */
51 void WEAK UART0_IRQHandler(void); /* UART0 */
52 void WEAK UART1_IRQHandler(void); /* UART1 */
53 void WEAK UART2_IRQHandler(void); /* UART2 */
54 void WEAK UART3_IRQHandler(void); /* UART3 */
55 void WEAK PWM1_IRQHandler(void); /* PWM1 */
56 void WEAK I2C0_IRQHandler(void); /* I2C0 */
57 void WEAK I2C1_IRQHandler(void); /* I2C1 */
58 void WEAK I2C2_IRQHandler(void); /* I2C2 */
59 void WEAK SPI_IRQHandler(void); /* SPI */
60 void WEAK SSP0_IRQHandler(void); /* SSP0 */
61 void WEAK SSP1_IRQHandler(void); /* SSP1 */
62 void WEAK PLL0_IRQHandler(void); /* PLL0 (Main PLL) */
63 void WEAK RTC_IRQHandler(void); /* Real Time Clock */
64 void WEAK EINT0_IRQHandler(void); /* External Interrupt 0 */
65 void WEAK EINT1_IRQHandler(void); /* External Interrupt 1 */
66 void WEAK EINT2_IRQHandler(void); /* External Interrupt 2 */
67 void WEAK EINT3_IRQHandler(void); /* External Interrupt 3 */
68 void WEAK ADC_IRQHandler(void); /* A/D Converter */
69 void WEAK BOD_IRQHandler(void); /* Brown Out Detect */
70 void WEAK USB_IRQHandler(void); /* USB */
71 void WEAK CAN_IRQHandler(void); /* CAN */
72 void WEAK DMA_IRQHandler(void); /* GP DMA */
73 void WEAK I2S_IRQHandler(void); /* I2S */
74 void WEAK ENET_IRQHandler(void); /* Ethernet */
75 void WEAK RIT_IRQHandler(void); /* Repetitive Interrupt Timer */
76 void WEAK MCPWM_IRQHandler(void); /* Motor Control PWM */
77 void WEAK QEI_IRQHandler(void); /* Quadrature Encoder Interface */
78 void WEAK PLL1_IRQHandler(void); /* PLL1 (USB PLL) */
79
80
81
82 /* Exported types --------------------------------------------------------------*/
83 /* Exported constants --------------------------------------------------------*/
84 extern unsigned long _etext;
85 extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */
86 extern unsigned long _sdata; /* start address for the .data section. defined in linker script */
87 extern unsigned long _edata; /* end address for the .data section. defined in linker script */
88
89 extern unsigned long _sifastcode; /* start address for the initialization values of the .fastcode section. defined in linker script */
90 extern unsigned long _sfastcode; /* start address for the .fastcode section. defined in linker script */
91 extern unsigned long _efastcode; /* end address for the .fastcode section. defined in linker script */
92
93 extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */
94 extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */
95
96 extern void _estack; /* init value for the stack pointer. defined in linker script */
97
98
99
100 /* Private typedef -----------------------------------------------------------*/
101 /* function prototypes ------------------------------------------------------*/
102 void Reset_Handler(void) __attribute__((__interrupt__));
103 extern int main(void);
104
105
106 /******************************************************************************
107 *
108 * The minimal vector table for a Cortex M3. Note that the proper constructs
109 * must be placed on this to ensure that it ends up at physical address
110 * 0x0000.0000.
111 *
112 ******************************************************************************/
113 #define STACK_SIZE 0x00000200
114
115 __attribute__ ((section(".stackarea")))
116 /* static */ unsigned long pulStack[STACK_SIZE];
117
118
119 __attribute__ ((section(".isr_vector")))
120 void (* const g_pfnVectors[])(void) =
121 {
122 /* &_estack, // The initial stack pointer */
123 (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), // The initial stack pointer
124 Reset_Handler, /* Reset Handler */
125 NMI_Handler, /* NMI Handler */
126 HardFault_Handler, /* Hard Fault Handler */
127 MemManage_Handler, /* MPU Fault Handler */
128 BusFault_Handler, /* Bus Fault Handler */
129 UsageFault_Handler, /* Usage Fault Handler */
130 0, /* Reserved */
131 0, /* Reserved */
132 0, /* Reserved */
133 0, /* Reserved */
134 SVC_Handler, /* SVCall Handler */
135 DebugMon_Handler, /* Debug Monitor Handler */
136 0, /* Reserved */
137 PendSV_Handler, /* PendSV Handler */
138 SysTick_Handler, /* SysTick Handler */
139
140 // External Interrupts
141 WDT_IRQHandler, /* Watchdog Timer */
142 TIMER0_IRQHandler, /* Timer0 */
143 TIMER1_IRQHandler, /* Timer1 */
144 TIMER2_IRQHandler, /* Timer2 */
145 TIMER3_IRQHandler, /* Timer3 */
146 UART0_IRQHandler, /* UART0 */
147 UART1_IRQHandler, /* UART1 */
148 UART2_IRQHandler, /* UART2 */
149 UART3_IRQHandler, /* UART3 */
150 PWM1_IRQHandler, /* PWM1 */
151 I2C0_IRQHandler, /* I2C0 */
152 I2C1_IRQHandler, /* I2C1 */
153 I2C2_IRQHandler, /* I2C2 */
154 SPI_IRQHandler, /* SPI */
155 SSP0_IRQHandler, /* SSP0 */
156 SSP1_IRQHandler, /* SSP1 */
157 PLL0_IRQHandler, /* PLL0 (Main PLL) */
158 RTC_IRQHandler, /* Real Time Clock */
159 EINT0_IRQHandler, /* External Interrupt 0 */
160 EINT1_IRQHandler, /* External Interrupt 1 */
161 EINT2_IRQHandler, /* External Interrupt 2 */
162 EINT3_IRQHandler, /* External Interrupt 3 */
163 ADC_IRQHandler, /* A/D Converter */
164 BOD_IRQHandler, /* Brown Out Detect */
165 USB_IRQHandler, /* USB */
166 CAN_IRQHandler, /* CAN */
167 DMA_IRQHandler, /* GP DMA */
168 I2S_IRQHandler, /* I2S */
169 ENET_IRQHandler, /* Ethernet */
170 RIT_IRQHandler, /* Repetitive Interrupt Timer */
171 MCPWM_IRQHandler, /* Motor Control PWM */
172 QEI_IRQHandler, /* Quadrature Encoder Interface */
173 PLL1_IRQHandler, /* PLL1 (USB PLL) */
174 };
175
176 /*******************************************************************************
177 * Function Name : Reset_Handler
178 * Description : This is the code that gets called when the processor first starts execution
179 * following a reset event. Only the absolutely necessary set is performed,
180 * after which the application supplied main() routine is called.
181 * Input :
182 * Output :
183 * Return :
184 *******************************************************************************/
185 void Reset_Handler(void)
186 {
187 SystemInit();
188
189 unsigned long *pulDest;
190 unsigned long *pulSrc;
191
192 //
193 // Copy the data segment initializers from flash to SRAM in ROM mode
194 //
195
196 if (&_sidata != &_sdata) { // only if needed
197 pulSrc = &_sidata;
198 for(pulDest = &_sdata; pulDest < &_edata; ) {
199 *(pulDest++) = *(pulSrc++);
200 }
201 }
202
203 // Copy the .fastcode code from ROM to SRAM
204
205 if (&_sifastcode != &_sfastcode) { // only if needed
206 pulSrc = &_sifastcode;
207 for(pulDest = &_sfastcode; pulDest < &_efastcode; ) {
208 *(pulDest++) = *(pulSrc++);
209 }
210 }
211
212 //
213 // Zero fill the bss segment.
214 //
215 for(pulDest = &_sbss; pulDest < &_ebss; )
216 {
217 *(pulDest++) = 0;
218 }
219
220 //
221 // Call the application's entry point.
222 //
223 main();
224 }
225
226 //*****************************************************************************
227 //
228 // Provide weak aliases for each Exception handler to the Default_Handler.
229 // As they are weak aliases, any function with the same name will override
230 // this definition.
231 //
232 //*****************************************************************************
233 #pragma weak MemManage_Handler = Default_Handler /* MPU Fault Handler */
234 #pragma weak BusFault_Handler = Default_Handler /* Bus Fault Handler */
235 #pragma weak UsageFault_Handler = Default_Handler /* Usage Fault Handler */
236 #pragma weak SVC_Handler = Default_Handler /* SVCall Handler */
237 #pragma weak DebugMon_Handler = Default_Handler /* Debug Monitor Handler */
238 #pragma weak PendSV_Handler = Default_Handler /* PendSV Handler */
239 #pragma weak SysTick_Handler = Default_Handler /* SysTick Handler */
240
241 /* External interrupt vector handler */
242 #pragma weak WDT_IRQHandler = Default_Handler /* Watchdog Timer */
243 #pragma weak TIMER0_IRQHandler = Default_Handler /* Timer0 */
244 #pragma weak TIMER1_IRQHandler = Default_Handler /* Timer1 */
245 #pragma weak TIMER2_IRQHandler = Default_Handler /* Timer2 */
246 #pragma weak TIMER3_IRQHandler = Default_Handler /* Timer3 */
247 #pragma weak UART0_IRQHandler = Default_Handler /* UART0 */
248 #pragma weak UART1_IRQHandler = Default_Handler /* UART1 */
249 #pragma weak UART2_IRQHandler = Default_Handler /* UART2 */
250 #pragma weak UART3_IRQHandler = Default_Handler /* UART3 */
251 #pragma weak PWM1_IRQHandler = Default_Handler /* PWM1 */
252 #pragma weak I2C0_IRQHandler = Default_Handler /* I2C0 */
253 #pragma weak I2C1_IRQHandler = Default_Handler /* I2C1 */
254 #pragma weak I2C2_IRQHandler = Default_Handler /* I2C2 */
255 #pragma weak SPI_IRQHandler = Default_Handler /* SPI */
256 #pragma weak SSP0_IRQHandler = Default_Handler /* SSP0 */
257 #pragma weak SSP1_IRQHandler = Default_Handler /* SSP1 */
258 #pragma weak PLL0_IRQHandler = Default_Handler /* PLL0 (Main PLL) */
259 #pragma weak RTC_IRQHandler = Default_Handler /* Real Time Clock */
260 #pragma weak EINT0_IRQHandler = Default_Handler /* External Interrupt 0 */
261 #pragma weak EINT1_IRQHandler = Default_Handler /* External Interrupt 1 */
262 #pragma weak EINT2_IRQHandler = Default_Handler /* External Interrupt 2 */
263 #pragma weak EINT3_IRQHandler = Default_Handler /* External Interrupt 3 */
264 #pragma weak ADC_IRQHandler = Default_Handler /* A/D Converter */
265 #pragma weak BOD_IRQHandler = Default_Handler /* Brown Out Detect */
266 #pragma weak USB_IRQHandler = Default_Handler /* USB */
267 #pragma weak CAN_IRQHandler = Default_Handler /* CAN */
268 #pragma weak DMA_IRQHandler = Default_Handler /* GP DMA */
269 #pragma weak I2S_IRQHandler = Default_Handler /* I2S */
270 #pragma weak ENET_IRQHandler = Default_Handler /* Ethernet */
271 #pragma weak RIT_IRQHandler = Default_Handler /* Repetitive Interrupt Timer */
272 #pragma weak MCPWM_IRQHandler = Default_Handler /* Motor Control PWM */
273 #pragma weak QEI_IRQHandler = Default_Handler /* Quadrature Encoder Interface */
274 #pragma weak PLL1_IRQHandler = Default_Handler /* PLL1 (USB PLL) */
275
276 //*****************************************************************************
277 //
278 // This is the code that gets called when the processor receives an unexpected
279 // interrupt. This simply enters an infinite loop, preserving the system state
280 // for examination by a debugger.
281 //
282 //*****************************************************************************
283 void Default_Handler(void) {
284 // Go into an infinite loop.
285 //
286 while (1) {
287 }
288 }
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1 startup_LPC17xx.o: \
2 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/startup_LPC17xx.c \
3 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/LPC17xx.h \
4 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/core_cm3.h \
5 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/system_LPC17xx.h
6
7 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/LPC17xx.h:
8
9 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/core_cm3.h:
10
11 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/system_LPC17xx.h:
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1 /**************************************************************************//**
2 * @file system_LPC17xx.c
3 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
4 * for the NXP LPC17xx Device Series
5 * @version V1.03
6 * @date 07. October 2009
7 *
8 * @note
9 * Copyright (C) 2009 ARM Limited. All rights reserved.
10 *
11 * @par
12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
13 * processor based microcontrollers. This file can be freely distributed
14 * within development tools that are supporting such ARM based processors.
15 *
16 * @par
17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22 *
23 ******************************************************************************/
24
25
26 #include <stdint.h>
27 #include "LPC17xx.h"
28
29 /*
30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
31 */
32
33 /*--------------------- Clock Configuration ----------------------------------
34 //
35 // <e> Clock Configuration
36 // <h> System Controls and Status Register (SCS)
37 // <o1.4> OSCRANGE: Main Oscillator Range Select
38 // <0=> 1 MHz to 20 MHz
39 // <1=> 15 MHz to 24 MHz
40 // <e1.5> OSCEN: Main Oscillator Enable
41 // </e>
42 // </h>
43 //
44 // <h> Clock Source Select Register (CLKSRCSEL)
45 // <o2.0..1> CLKSRC: PLL Clock Source Selection
46 // <0=> Internal RC oscillator
47 // <1=> Main oscillator
48 // <2=> RTC oscillator
49 // </h>
50 //
51 // <e3> PLL0 Configuration (Main PLL)
52 // <h> PLL0 Configuration Register (PLL0CFG)
53 // <i> F_cco0 = (2 * M * F_in) / N
54 // <i> F_in must be in the range of 32 kHz to 50 MHz
55 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
56 // <o4.0..14> MSEL: PLL Multiplier Selection
57 // <6-32768><#-1>
58 // <i> M Value
59 // <o4.16..23> NSEL: PLL Divider Selection
60 // <1-256><#-1>
61 // <i> N Value
62 // </h>
63 // </e>
64 //
65 // <e5> PLL1 Configuration (USB PLL)
66 // <h> PLL1 Configuration Register (PLL1CFG)
67 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
68 // <i> F_cco1 = F_osc * M * 2 * P
69 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
70 // <o6.0..4> MSEL: PLL Multiplier Selection
71 // <1-32><#-1>
72 // <i> M Value (for USB maximum value is 4)
73 // <o6.5..6> PSEL: PLL Divider Selection
74 // <0=> 1
75 // <1=> 2
76 // <2=> 4
77 // <3=> 8
78 // <i> P Value
79 // </h>
80 // </e>
81 //
82 // <h> CPU Clock Configuration Register (CCLKCFG)
83 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
84 // <3-256><#-1>
85 // </h>
86 //
87 // <h> USB Clock Configuration Register (USBCLKCFG)
88 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
89 // <0-15>
90 // <i> Divide is USBSEL + 1
91 // </h>
92 //
93 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
94 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
95 // <0=> Pclk = Cclk / 4
96 // <1=> Pclk = Cclk
97 // <2=> Pclk = Cclk / 2
98 // <3=> Pclk = Hclk / 8
99 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
100 // <0=> Pclk = Cclk / 4
101 // <1=> Pclk = Cclk
102 // <2=> Pclk = Cclk / 2
103 // <3=> Pclk = Hclk / 8
104 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
105 // <0=> Pclk = Cclk / 4
106 // <1=> Pclk = Cclk
107 // <2=> Pclk = Cclk / 2
108 // <3=> Pclk = Hclk / 8
109 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
110 // <0=> Pclk = Cclk / 4
111 // <1=> Pclk = Cclk
112 // <2=> Pclk = Cclk / 2
113 // <3=> Pclk = Hclk / 8
114 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
115 // <0=> Pclk = Cclk / 4
116 // <1=> Pclk = Cclk
117 // <2=> Pclk = Cclk / 2
118 // <3=> Pclk = Hclk / 8
119 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
120 // <0=> Pclk = Cclk / 4
121 // <1=> Pclk = Cclk
122 // <2=> Pclk = Cclk / 2
123 // <3=> Pclk = Hclk / 8
124 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
125 // <0=> Pclk = Cclk / 4
126 // <1=> Pclk = Cclk
127 // <2=> Pclk = Cclk / 2
128 // <3=> Pclk = Hclk / 8
129 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
130 // <0=> Pclk = Cclk / 4
131 // <1=> Pclk = Cclk
132 // <2=> Pclk = Cclk / 2
133 // <3=> Pclk = Hclk / 8
134 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
135 // <0=> Pclk = Cclk / 4
136 // <1=> Pclk = Cclk
137 // <2=> Pclk = Cclk / 2
138 // <3=> Pclk = Hclk / 8
139 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
140 // <0=> Pclk = Cclk / 4
141 // <1=> Pclk = Cclk
142 // <2=> Pclk = Cclk / 2
143 // <3=> Pclk = Hclk / 8
144 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
145 // <0=> Pclk = Cclk / 4
146 // <1=> Pclk = Cclk
147 // <2=> Pclk = Cclk / 2
148 // <3=> Pclk = Hclk / 8
149 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
150 // <0=> Pclk = Cclk / 4
151 // <1=> Pclk = Cclk
152 // <2=> Pclk = Cclk / 2
153 // <3=> Pclk = Hclk / 6
154 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
155 // <0=> Pclk = Cclk / 4
156 // <1=> Pclk = Cclk
157 // <2=> Pclk = Cclk / 2
158 // <3=> Pclk = Hclk / 6
159 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
160 // <0=> Pclk = Cclk / 4
161 // <1=> Pclk = Cclk
162 // <2=> Pclk = Cclk / 2
163 // <3=> Pclk = Hclk / 6
164 // </h>
165 //
166 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
167 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
168 // <0=> Pclk = Cclk / 4
169 // <1=> Pclk = Cclk
170 // <2=> Pclk = Cclk / 2
171 // <3=> Pclk = Hclk / 8
172 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
173 // <0=> Pclk = Cclk / 4
174 // <1=> Pclk = Cclk
175 // <2=> Pclk = Cclk / 2
176 // <3=> Pclk = Hclk / 8
177 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
178 // <0=> Pclk = Cclk / 4
179 // <1=> Pclk = Cclk
180 // <2=> Pclk = Cclk / 2
181 // <3=> Pclk = Hclk / 8
182 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
183 // <0=> Pclk = Cclk / 4
184 // <1=> Pclk = Cclk
185 // <2=> Pclk = Cclk / 2
186 // <3=> Pclk = Hclk / 8
187 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
188 // <0=> Pclk = Cclk / 4
189 // <1=> Pclk = Cclk
190 // <2=> Pclk = Cclk / 2
191 // <3=> Pclk = Hclk / 8
192 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
193 // <0=> Pclk = Cclk / 4
194 // <1=> Pclk = Cclk
195 // <2=> Pclk = Cclk / 2
196 // <3=> Pclk = Hclk / 8
197 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
198 // <0=> Pclk = Cclk / 4
199 // <1=> Pclk = Cclk
200 // <2=> Pclk = Cclk / 2
201 // <3=> Pclk = Hclk / 8
202 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
203 // <0=> Pclk = Cclk / 4
204 // <1=> Pclk = Cclk
205 // <2=> Pclk = Cclk / 2
206 // <3=> Pclk = Hclk / 8
207 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
208 // <0=> Pclk = Cclk / 4
209 // <1=> Pclk = Cclk
210 // <2=> Pclk = Cclk / 2
211 // <3=> Pclk = Hclk / 8
212 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
213 // <0=> Pclk = Cclk / 4
214 // <1=> Pclk = Cclk
215 // <2=> Pclk = Cclk / 2
216 // <3=> Pclk = Hclk / 8
217 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
218 // <0=> Pclk = Cclk / 4
219 // <1=> Pclk = Cclk
220 // <2=> Pclk = Cclk / 2
221 // <3=> Pclk = Hclk / 8
222 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
223 // <0=> Pclk = Cclk / 4
224 // <1=> Pclk = Cclk
225 // <2=> Pclk = Cclk / 2
226 // <3=> Pclk = Hclk / 8
227 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
228 // <0=> Pclk = Cclk / 4
229 // <1=> Pclk = Cclk
230 // <2=> Pclk = Cclk / 2
231 // <3=> Pclk = Hclk / 8
232 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
233 // <0=> Pclk = Cclk / 4
234 // <1=> Pclk = Cclk
235 // <2=> Pclk = Cclk / 2
236 // <3=> Pclk = Hclk / 8
237 // </h>
238 //
239 // <h> Power Control for Peripherals Register (PCONP)
240 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
241 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
242 // <o11.3> PCUART0: UART 0 power/clock enable
243 // <o11.4> PCUART1: UART 1 power/clock enable
244 // <o11.6> PCPWM1: PWM 1 power/clock enable
245 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
246 // <o11.8> PCSPI: SPI interface power/clock enable
247 // <o11.9> PCRTC: RTC power/clock enable
248 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
249 // <o11.12> PCAD: A/D converter power/clock enable
250 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
251 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
252 // <o11.15> PCGPIO: GPIOs power/clock enable
253 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
254 // <o11.17> PCMC: Motor control PWM power/clock enable
255 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
256 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
257 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
258 // <o11.22> PCTIM2: Timer 2 power/clock enable
259 // <o11.23> PCTIM3: Timer 3 power/clock enable
260 // <o11.24> PCUART2: UART 2 power/clock enable
261 // <o11.25> PCUART3: UART 3 power/clock enable
262 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
263 // <o11.27> PCI2S: I2S interface power/clock enable
264 // <o11.29> PCGPDMA: GP DMA function power/clock enable
265 // <o11.30> PCENET: Ethernet block power/clock enable
266 // <o11.31> PCUSB: USB interface power/clock enable
267 // </h>
268 //
269 // <h> Clock Output Configuration Register (CLKOUTCFG)
270 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
271 // <0=> CPU clock
272 // <1=> Main oscillator
273 // <2=> Internal RC oscillator
274 // <3=> USB clock
275 // <4=> RTC oscillator
276 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
277 // <1-16><#-1>
278 // <o12.8> CLKOUT_EN: CLKOUT enable control
279 // </h>
280 //
281 // </e>
282 */
283 #define CLOCK_SETUP 1
284 #define SCS_Val 0x00000020
285 #define CLKSRCSEL_Val 0x00000001
286 #define PLL0_SETUP 1
287 #define PLL0CFG_Val 0x00050063
288 #define PLL1_SETUP 1
289 #define PLL1CFG_Val 0x00000023
290 #define CCLKCFG_Val 0x00000003
291 #define USBCLKCFG_Val 0x00000000
292 #define PCLKSEL0_Val 0x00000000
293 #define PCLKSEL1_Val 0x00000000
294 #define PCONP_Val 0x042887DE
295 #define CLKOUTCFG_Val 0x00000000
296
297
298 /*--------------------- Flash Accelerator Configuration ----------------------
299 //
300 // <e> Flash Accelerator Configuration
301 // <o1.0..1> FETCHCFG: Fetch Configuration
302 // <0=> Instruction fetches from flash are not buffered
303 // <1=> One buffer is used for all instruction fetch buffering
304 // <2=> All buffers may be used for instruction fetch buffering
305 // <3=> Reserved (do not use this setting)
306 // <o1.2..3> DATACFG: Data Configuration
307 // <0=> Data accesses from flash are not buffered
308 // <1=> One buffer is used for all data access buffering
309 // <2=> All buffers may be used for data access buffering
310 // <3=> Reserved (do not use this setting)
311 // <o1.4> ACCEL: Acceleration Enable
312 // <o1.5> PREFEN: Prefetch Enable
313 // <o1.6> PREFOVR: Prefetch Override
314 // <o1.12..15> FLASHTIM: Flash Access Time
315 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
316 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
317 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
318 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
319 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
320 // <5=> 6 CPU clocks (for any CPU clock)
321 // </e>
322 */
323 #define FLASH_SETUP 1
324 #define FLASHCFG_Val 0x0000303A
325
326 /*
327 //-------- <<< end of configuration section >>> ------------------------------
328 */
329
330 /*----------------------------------------------------------------------------
331 Check the register settings
332 *----------------------------------------------------------------------------*/
333 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
334 #define CHECK_RSVD(val, mask) (val & mask)
335
336 /* Clock Configuration -------------------------------------------------------*/
337 #if (CHECK_RSVD((SCS_Val), ~0x00000030))
338 #error "SCS: Invalid values of reserved bits!"
339 #endif
340
341 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
342 #error "CLKSRCSEL: Value out of range!"
343 #endif
344
345 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
346 #error "PLL0CFG: Invalid values of reserved bits!"
347 #endif
348
349 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
350 #error "PLL1CFG: Invalid values of reserved bits!"
351 #endif
352
353 #if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
354 #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
355 #endif
356
357 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
358 #error "USBCLKCFG: Invalid values of reserved bits!"
359 #endif
360
361 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
362 #error "PCLKSEL0: Invalid values of reserved bits!"
363 #endif
364
365 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
366 #error "PCLKSEL1: Invalid values of reserved bits!"
367 #endif
368
369 #if (CHECK_RSVD((PCONP_Val), 0x10100821))
370 #error "PCONP: Invalid values of reserved bits!"
371 #endif
372
373 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
374 #error "CLKOUTCFG: Invalid values of reserved bits!"
375 #endif
376
377 /* Flash Accelerator Configuration -------------------------------------------*/
378 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
379 #error "FLASHCFG: Invalid values of reserved bits!"
380 #endif
381
382
383 /*----------------------------------------------------------------------------
384 DEFINES
385 *----------------------------------------------------------------------------*/
386
387 /*----------------------------------------------------------------------------
388 Define clocks
389 *----------------------------------------------------------------------------*/
390 #define XTAL (12000000UL) /* Oscillator frequency */
391 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
392 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
393 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
394
395
396 /* F_cco0 = (2 * M * F_in) / N */
397 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
398 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
399 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
400 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
401
402 /* Determine core clock frequency according to settings */
403 #if (PLL0_SETUP)
404 #if ((CLKSRCSEL_Val & 0x03) == 1)
405 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
406 #elif ((CLKSRCSEL_Val & 0x03) == 2)
407 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
408 #else
409 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
410 #endif
411 #else
412 #if ((CLKSRCSEL_Val & 0x03) == 1)
413 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
414 #elif ((CLKSRCSEL_Val & 0x03) == 2)
415 #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
416 #else
417 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
418 #endif
419 #endif
420
421
422 /*----------------------------------------------------------------------------
423 Clock Variable definitions
424 *----------------------------------------------------------------------------*/
425 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
426
427
428 /*----------------------------------------------------------------------------
429 Clock functions
430 *----------------------------------------------------------------------------*/
431 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
432 {
433 /* Determine clock frequency according to clock register values */
434 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
435 switch (LPC_SC->CLKSRCSEL & 0x03) {
436 case 0: /* Int. RC oscillator => PLL0 */
437 case 3: /* Reserved, default to Int. RC */
438 SystemCoreClock = (IRC_OSC *
439 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
440 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
441 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
442 break;
443 case 1: /* Main oscillator => PLL0 */
444 SystemCoreClock = (OSC_CLK *
445 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
446 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
447 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
448 break;
449 case 2: /* RTC oscillator => PLL0 */
450 SystemCoreClock = (RTC_CLK *
451 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
452 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
453 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
454 break;
455 }
456 } else {
457 switch (LPC_SC->CLKSRCSEL & 0x03) {
458 case 0: /* Int. RC oscillator => PLL0 */
459 case 3: /* Reserved, default to Int. RC */
460 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
461 break;
462 case 1: /* Main oscillator => PLL0 */
463 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
464 break;
465 case 2: /* RTC oscillator => PLL0 */
466 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
467 break;
468 }
469 }
470
471 }
472
473 /**
474 * Initialize the system
475 *
476 * @param none
477 * @return none
478 *
479 * @brief Setup the microcontroller system.
480 * Initialize the System.
481 */
482 void SystemInit (void)
483 {
484 #if (CLOCK_SETUP) /* Clock Setup */
485 LPC_SC->SCS = SCS_Val;
486 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
487 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
488 }
489
490 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
491
492 #if (PLL0_SETUP)
493 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
494
495 LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
496 LPC_SC->PLL0FEED = 0xAA;
497 LPC_SC->PLL0FEED = 0x55;
498
499 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
500 LPC_SC->PLL0FEED = 0xAA;
501 LPC_SC->PLL0FEED = 0x55;
502 while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
503
504 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
505 LPC_SC->PLL0FEED = 0xAA;
506 LPC_SC->PLL0FEED = 0x55;
507 while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
508 #endif
509
510 #if (PLL1_SETUP)
511 LPC_SC->PLL1CFG = PLL1CFG_Val;
512 LPC_SC->PLL1FEED = 0xAA;
513 LPC_SC->PLL1FEED = 0x55;
514
515 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
516 LPC_SC->PLL1FEED = 0xAA;
517 LPC_SC->PLL1FEED = 0x55;
518 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
519
520 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
521 LPC_SC->PLL1FEED = 0xAA;
522 LPC_SC->PLL1FEED = 0x55;
523 while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
524 #else
525 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
526 #endif
527
528 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
529 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
530
531 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
532
533 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
534 #endif
535
536 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
537 LPC_SC->FLASHCFG = FLASHCFG_Val;
538 #endif
539 }
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@@ -0,0 +1,11
1 system_LPC17xx.o: \
2 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/system_LPC17xx.c \
3 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/LPC17xx.h \
4 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/core_cm3.h \
5 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/system_LPC17xx.h
6
7 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/LPC17xx.h:
8
9 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/core_cm3.h:
10
11 /opt/libuc2/rules/lpc17XX-arm-noabi-gcc/system_LPC17xx.h:
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@@ -0,0 +1,64
1 /**************************************************************************//**
2 * @file system_LPC17xx.h
3 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
4 * for the NXP LPC17xx Device Series
5 * @version V1.02
6 * @date 08. September 2009
7 *
8 * @note
9 * Copyright (C) 2009 ARM Limited. All rights reserved.
10 *
11 * @par
12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
13 * processor based microcontrollers. This file can be freely distributed
14 * within development tools that are supporting such ARM based processors.
15 *
16 * @par
17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22 *
23 ******************************************************************************/
24
25
26 #ifndef __SYSTEM_LPC17xx_H
27 #define __SYSTEM_LPC17xx_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #include <stdint.h>
34
35 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
36
37
38 /**
39 * Initialize the system
40 *
41 * @param none
42 * @return none
43 *
44 * @brief Setup the microcontroller system.
45 * Initialize the System and update the SystemCoreClock variable.
46 */
47 extern void SystemInit (void);
48
49 /**
50 * Update SystemCoreClock variable
51 *
52 * @param none
53 * @return none
54 *
55 * @brief Updates the SystemCoreClock with current core Clock
56 * retrieved from cpu registers.
57 */
58 extern void SystemCoreClockUpdate (void);
59
60 #ifdef __cplusplus
61 }
62 #endif
63
64 #endif /* __SYSTEM_LPC17xx_H */
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@@ -20,47 +20,4
20 #-- Mail : alexis.jeandet@gmail.com
20 #-- Mail : alexis.jeandet@gmail.com
21 #-------------------------------------------------------------------------------*/
21 #-------------------------------------------------------------------------------*/
22
22
23 all:
23 subdir:
24 @echo "calling rules.mk"
25
26 bindirs:
27 mkdir -p $(OUTBINDIR)
28 mkdir -p $(TEMPDIR)
29
30 libdirs:
31 mkdir -p tmp
32 mkdir -p $(INCPATH)
33 mkdir -p $(LIBDIR)
34
35 $(NAME).elf: bindirs $(FILE).o $(STARTUP).o
36 $(CC) -O3 -nostartfiles -T $(LDSCRIPT) -o $(OUTBINDIR)$(NAME).elf $(TEMPDIR)$(FILE).o $(TEMPDIR)$(STARTUP).o -I$(LPCINCPATH) -I$(BSPINCPATH) -I$(INCPATH) -L $(LIBDIR) -L $(BSPLIBDIR) -static $(LIBS) -lbsp $(FLAGS)
37
38 $(FILE).o:
39 $(CC) -I$(LPCINCPATH) -I$(BSPINCPATH) -I$(INCPATH) -c $(FILE).c -o tmp/$(FILE).o $(FLAGS)
40
41
42 $(STARTUP).o: $(STARTUP)
43 $(CC) -O3 -c -o $(TEMPDIR)$(STARTUP).o $(STARTUP) $(FLAGS)
44
45 run: $(NAME).hex
46 $(FLASHER) -hex -term $(OUTBINDIR)$(NAME).hex $(PORT) $(SPEED) $(OSC)
47
48 $(NAME).hex: $(OUTBINDIR)$(NAME).elf
49 $(OBJCOPY) -O ihex $(OUTBINDIR)$(NAME).elf $(OUTBINDIR)$(NAME).hex
50
51
52 $(FILE).a: libdirs $(FILE).o
53 $(AR) rs $(LIBDIR)$(LIB) tmp/$(FILE).o
54 cp *.h $(INCPATH)
55 rm -R tmp
56 @echo "library "$(LIB)" created"
57 $(READELF) -a $(LIBDIR)$(LIB)
58
59
60
61 bspclean:
62 rm -R -f $(LIBUCROOT)lib/BSP/bin/$(BOARD)
63
64 libclean:
65 rm -f $(LIBDIR)$(LIB)
66 rm -f $(INCPATH)$(FILE).h No newline at end of file
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@@ -0,0 +1,148
1 #/*------------------------------------------------------------------------------
2 #-- This file is a part of the libuc, microcontroler library
3 #-- Copyright (C) 2011, Alexis Jeandet
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #-------------------------------------------------------------------------------
19 #-- Author : Alexis Jeandet
20 #-- Mail : alexis.jeandet@gmail.com
21 #-------------------------------------------------------------------------------*/
22
23 #---------------------------------------------------------------------------------
24 # GCC EXECUTABLES
25 #---------------------------------------------------------------------------------
26 LIBUC_PREFIX = arm-none-eabi-
27 LIBUC_CC = $(LIBUC_PREFIX)gcc
28 LIBUC_CXX = $(LIBUC_PREFIX)g++
29 LIBUC_AR = $(LIBUC_PREFIX)ar
30 LIBUC_AS = $(LIBUC_PREFIX)as
31 LIBUC_LD = $(LIBUC_PREFIX)ld
32 LIBUC_SIZE = $(LIBUC_PREFIX)size
33 LIBUC_STRIP = $(LIBUC_PREFIX)strip -s
34 LIBUC_READELF = $(LIBUC_PREFIX)readelf
35 LIBUC_OBJCOPY=$(LIBUC_PREFIX)objcopy
36 LIBUC_OBJDUMP=$(LIBUC_PREFIX)objdump
37
38
39
40 #---------------------------------------------------------------------------------
41 # GCC FLAGS
42 #---------------------------------------------------------------------------------
43 LIBUC_FMCU = -mcpu=cortex-m3
44 LIBUC_CFLAGS = $(LIBUC_FMCU)
45 LIBUC_CFLAGS = --std=gnu99 -fgnu89-inline -mcpu=cortex-m3 -mthumb
46 LIBUC_CFLAGS += -ffunction-sections -fdata-sections
47 LIBUC_LDFLAGS = --gc-sections
48 LIBUC_ODFLAGS = -x --syms
49 LIBUC_CPFLAGS =
50 LIBUC_CFLAGS_WARN_ON = -Wall
51 LIBUC_CFLAGS_WARN_OFF = -w
52 LIBUC_CFLAGS_RELEASE = -O2
53 LIBUC_CFLAGS_DEBUG = -g
54 LIBUC_CFLAGS_RELEASE_WITH_DEBUGINFO += -O2 -g
55 LIBUC_CFLAGS_STATIC_LIB = -fPIC
56 LIBUC_CFLAGS_SOFT_FPU = -msoft-float
57 LIBUC_CFLAGS_HARD_FPU =
58
59 LIBUC_CXXFLAGS = $(LIBUC_FMCU)
60 LIBUC_CXXFLAGS += -g -gdwarf-2
61 LIBUC_CXXFLAGS += -Wextra -Wundef -Wcast-align -mthumb -msoft-float
62 LIBUC_CXXFLAGS_WARN_ON = -Wall
63 LIBUC_CXXFLAGS_WARN_OFF = -w
64 LIBUC_CXXFLAGS_RELEASE = -O2
65 LIBUC_CXXFLAGS_DEBUG = -g
66 LIBUC_CXXFLAGS_RELEASE_WITH_DEBUGINFO += -O2 -g
67 LIBUC_CXXFLAGS_STATIC_LIB = -fPIC
68 LIBUC_CXXFLAGS_SOFT_FPU = -msoft-float
69 LIBUC_CXXFLAGS_HARD_FPU =
70
71 LIBUC_LIBS =
72 LIBUC_LIBS_UART = -luart
73 LIBUC_LIBS_SPI = -lspi
74 LIBUC_LIBS_IIC = -liic
75 LIBUC_LIBS_ADC = -ladc
76
77 LIBUC_LIBS_DIR = $(LIBUC)/lib/bin/lpc17XX
78 LIBUC_LIBS_DIR_UART = -L $(LIBUC_LIBS_DIR)/UART
79 LIBUC_LIBS_DIR_SPI = -L $(LIBUC_LIBS_DIR)/SPI
80 LIBUC_LIBS_DIR_IIC = -L $(LIBUC_LIBS_DIR)/IIC
81 LIBUC_LIBS_DIR_ADC = -L $(LIBUC_LIBS_DIR)/ADC
82
83 LIBUC_INC_DIR = $(LIBUC)/lib/includes/lpc17XX
84 LIBUC_INC_DIR_UART = -I $(LIBUC_INC_DIR)/UART
85 LIBUC_INC_DIR_SPI = -I $(LIBUC_INC_DIR)/SPI
86 LIBUC_INC_DIR_IIC = -I $(LIBUC_INC_DIR)/IIC
87 LIBUC_INC_DIR_ADC = -I $(LIBUC_INC_DIR)/ADC
88
89 #---------------------------------------------------------------------------------
90 # DEVICE SPECIAL FILES
91 #---------------------------------------------------------------------------------
92 LINKER_SCRIPT = $(ARCH)/LPC17xx.ld
93 SOURCES += $(ARCH)/startup_LPC17xx.c $(ARCH)/core_cm3.c $(ARCH)/system_LPC17xx.c
94 LPC17XX_INCDIR=$(ARCH)
95
96
97 all:
98 @echo "lpc17XX-arm-noabi-gcc rules"
99
100
101 bin: $(TARGET).bin $(TARGET).hex
102 @echo "compile bin"
103
104
105
106 lib: $(TARGET).a
107 @echo "compile lib"
108
109 %.a: $(OBJECTFILES)
110 mkdir -p $(TARGETINSTALLPATH)
111 mkdir -p $(HEADERSINSTALLPATH)
112 ar rcs $(TARGETINSTALLPATH)/$@ $(OBJECTFILES)
113 cp $(HEADERS) $(HEADERSINSTALLPATH)/
114
115
116 %.o: %.c
117 $(LIBUC_CC) -I $(LPC17XX_INCDIR) $(LIBUC_INCLUDES) -MM $< -MF $*.d -MP
118 $(LIBUC_CC) -I $(LPC17XX_INCDIR) $(LIBUC_INCLUDES) -c $(LIBUC_CFLAGS) $< -o $@
119
120
121 %.elf: $(LINKER_SCRIPT) $(OBJECTFILES)
122 $(LIBUC_LD) -Map $(@:.elf=.map) $(LIBUC_LDFLAGS) $(LIBUC_LIBRARIES) -T $^ -o $@
123 $(LIBUC_OBJDUMP) $(LIBUC_ODFLAGS) $@ > $(@:.elf=.dump)
124 $(LIBUC_SIZE) $@
125
126 %.bin: %.elf
127 $(LIBUC_OBJCOPY) $(LIBUC_CPFLAGS) -O binary $< $*.bin
128
129
130 %.hex: %.elf
131 $(LIBUC_OBJCOPY) $(LIBUC_CPFLAGS) -O ihex $< $*.hex
132
133
134 clean:
135 rm -f *.o *.d *.bin *.hex *.dump *.map *.a
136
137 distclean:
138 rm -f $(TARGETINSTALLPATH)/*.bin
139 rm -f $(TARGETINSTALLPATH)/*.a
140
141
142
143
144
145
146
147
148
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@@ -27,7 +27,10 LIBUC_PREFIX = arm-elf-
27 LIBUC_CC = $(LIBUC_PREFIX)gcc
27 LIBUC_CC = $(LIBUC_PREFIX)gcc
28 LIBUC_CXX = $(LIBUC_PREFIX)g++
28 LIBUC_CXX = $(LIBUC_PREFIX)g++
29 LIBUC_AR = $(LIBUC_PREFIX)ar
29 LIBUC_AR = $(LIBUC_PREFIX)ar
30 LIBUC_AS = $(LIBUC_PREFIX)as
31 LIBUC_LD = $(LIBUC_PREFIX)ld
30 LIBUC_SIZE = $(LIBUC_PREFIX)size
32 LIBUC_SIZE = $(LIBUC_PREFIX)size
33 LIBUC_STRIP = $(LIBUC_PREFIX)strip -s
31 LIBUC_READELF = $(LIBUC_PREFIX)readelf
34 LIBUC_READELF = $(LIBUC_PREFIX)readelf
32 LIBUC_OBJCOPY=$(LIBUC_PREFIX)objcopy
35 LIBUC_OBJCOPY=$(LIBUC_PREFIX)objcopy
33
36
@@ -86,4 +89,3 LIBUC_INC_DIR_ADC = -L $(LIBUC_
86
89
87
90
88
91
89
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