##// END OF EJS Templates
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jeandet@PC-DE-JEANDET.lab-lpp.local -
r27:75d21abb7f67 default
parent child
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@@ -1,35 +1,40
1 #include <stdio.h>
1 #include <stdio.h>
2 #include <fat32.h>
2 #include <fat32.h>
3 #include <gpio.h>
3 #include <gpio.h>
4 #include <uart.h>
4 #include <uart.h>
5 #include <stm32f4xx.h>
5 #include <stm32f4xx.h>
6 #include <bsp.h>
6 #include <bsp.h>
7 #include <i2c.h>
7 #include <i2c.h>
8 #include <CS43L22.h>
8
9
9
10
10 extern streamdevice* __opnfiles__[];
11 extern streamdevice* __opnfiles__[];
11
12
12 int main()
13 int main()
13 {
14 {
15 CS43L22_t audioDac1;
16 cs43l22open(&audioDac1,i2c1,0);
17 char id=cs43l22getID(&audioDac1);
18 printf("DAC ID=%c\n\r",0x0ff&id);
14 while(1)
19 while(1)
15 {
20 {
16 for(volatile int i=0;i<1024*2048;i++);
21 for(volatile int i=0;i<1024*2048;i++);
17 gpioset(LED1);
22 gpioset(LED1);
18 gpioclr(LED2);
23 gpioclr(LED2);
19 for(volatile int i=0;i<1024*2048;i++);
24 for(volatile int i=0;i<1024*2048;i++);
20 gpioclr(LED1);
25 gpioclr(LED1);
21 gpioset(LED2);
26 gpioset(LED2);
22 i2cwrite(i2c1,0x4a,"test",1);
27 i2cwrite(i2c1,0x4a,"test",1);
23 }
28 }
24 printf("hello world\n\r");
29 printf("hello world\n\r");
25 return 0;
30 return 0;
26 }
31 }
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@@ -1,87 +1,87
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the libuc, microcontroler library
2 -- This file is a part of the libuc, microcontroler library
3 -- Copyright (C) 2011, Alexis Jeandet
3 -- Copyright (C) 2011, Alexis Jeandet
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@gmail.com
20 -- Mail : alexis.jeandet@gmail.com
21 -------------------------------------------------------------------------------*/
21 -------------------------------------------------------------------------------*/
22 #ifndef CS43L22_H
22 #ifndef CS43L22_H
23 #define CS43L22_H
23 #define CS43L22_H
24
24
25 #include <i2c.h>
25 #include <i2c.h>
26 #include <uhandle.h>
26 #include <uhandle.h>
27
27
28 typedef struct CS43L22_t
28 typedef struct CS43L22_t
29 {
29 {
30 i2c_t i2cdev;
30 i2c_t i2cdev;
31 uint8_t devAddress;
31 uint8_t devAddress;
32 }CS43L22_t;
32 }CS43L22_t;
33
33
34 extern int cs43l22open(CS43L22_t* dev,uint8_t address);
34 extern int cs43l22open(CS43L22_t* dev,i2c_t i2cdev,uint8_t A0);
35 extern uint8_t cs43l22getID(CS43L22_t* dev);
35
36
36
37 #define CS43L22_I2C_ADDRESS 0x4a
37
38
38
39
39
40 #define CS43L22_MAP_ID 1
40 #define CS43L22_MAP_ID 1
41 #define CS43L22_MAP_Power_Ctl_1 2
41 #define CS43L22_MAP_Power_Ctl_1 2
42 #define CS43L22_MAP_Power_Ctl_2 4
42 #define CS43L22_MAP_Power_Ctl_2 4
43 #define CS43L22_MAP_Clocking_Ctl 5
43 #define CS43L22_MAP_Clocking_Ctl 5
44 #define CS43L22_MAP_Interface_Ctl_1 6
44 #define CS43L22_MAP_Interface_Ctl_1 6
45 #define CS43L22_MAP_Interface_Ctl_2 7
45 #define CS43L22_MAP_Interface_Ctl_2 7
46 #define CS43L22_MAP_Passthrough_A 8
46 #define CS43L22_MAP_Passthrough_A 8
47 #define CS43L22_MAP_Passthrough_B 9
47 #define CS43L22_MAP_Passthrough_B 9
48 #define CS43L22_MAP_Analog_ZC_SR 0xA
48 #define CS43L22_MAP_Analog_ZC_SR 0xA
49 #define CS43L22_MAP_Passthrough 0xC
49 #define CS43L22_MAP_Passthrough 0xC
50 #define CS43L22_MAP_Playback_Ctl_1 0xD
50 #define CS43L22_MAP_Playback_Ctl_1 0xD
51 #define CS43L22_MAP_Misc_Ctl 0xE
51 #define CS43L22_MAP_Misc_Ctl 0xE
52 #define CS43L22_MAP_Playback_Ctl_2 0xF
52 #define CS43L22_MAP_Playback_Ctl_2 0xF
53 #define CS43L22_MAP_Passthrough_A 0x14
53 #define CS43L22_MAP_Passthrough_A_Vol 0x14
54 #define CS43L22_MAP_Passthrough_B 0x15
54 #define CS43L22_MAP_Passthrough_B_Vol 0x15
55 #define CS43L22_MAP_PCMA_Vol 0x1A
55 #define CS43L22_MAP_PCMA_Vol 0x1A
56 #define CS43L22_MAP_PCMB_Vol 0x1B
56 #define CS43L22_MAP_PCMB_Vol 0x1B
57 #define CS43L22_MAP_BEEP_Freq 0x1C
57 #define CS43L22_MAP_BEEP_Freq 0x1C
58 #define CS43L22_MAP_BEEP_Vol 0x1d
58 #define CS43L22_MAP_BEEP_Vol 0x1d
59 #define CS43L22_MAP_BEEP_Tone_Cfg 0x1E
59 #define CS43L22_MAP_BEEP_Tone_Cfg 0x1E
60 #define CS43L22_MAP_Tone_Ctl 0x1F
60 #define CS43L22_MAP_Tone_Ctl 0x1F
61 #define CS43L22_MAP_Master_A_Vol 0x20
61 #define CS43L22_MAP_Master_A_Vol 0x20
62 #define CS43L22_MAP_Master_B_Vol 0x21
62 #define CS43L22_MAP_Master_B_Vol 0x21
63 #define CS43L22_MAP_Headphone_A_Vol 0x22
63 #define CS43L22_MAP_Headphone_A_Vol 0x22
64 #define CS43L22_MAP_Headphone_B_Vol 0x23
64 #define CS43L22_MAP_Headphone_B_Vol 0x23
65 #define CS43L22_MAP_Speaker_A_Vol 0x24
65 #define CS43L22_MAP_Speaker_A_Vol 0x24
66 #define CS43L22_MAP_Speaker_B_Vol 0x25
66 #define CS43L22_MAP_Speaker_B_Vol 0x25
67 #define CS43L22_MAP_Channel_Mixer 0x26
67 #define CS43L22_MAP_Channel_Mixer 0x26
68 #define CS43L22_MAP_Limit_Ctl_1 0x27
68 #define CS43L22_MAP_Limit_Ctl_1 0x27
69 #define CS43L22_MAP_Limit Ctl_2 0x28
69 #define CS43L22_MAP_Limit Ctl_2 0x28
70 #define CS43L22_MAP_Limiter_Attack 0x29
70 #define CS43L22_MAP_Limiter_Attack 0x29
71 #define CS43L22_MAP_Overflow_&_Clock_Status 0x2E
71 #define CS43L22_MAP_Overflow_And_Clock_Status 0x2E
72 #define CS43L22_MAP_Battery_Compensation 0x2F
72 #define CS43L22_MAP_Battery_Compensation 0x2F
73 #define CS43L22_MAP_VP_Battery_Level 0x30
73 #define CS43L22_MAP_VP_Battery_Level 0x30
74 #define CS43L22_MAP_Speaker_Status 0x31
74 #define CS43L22_MAP_Speaker_Status 0x31
75 #define CS43L22_MAP_Temperature_Monitor_Control 0x32
75 #define CS43L22_MAP_Temperature_Monitor_Control 0x32
76 #define CS43L22_MAP_Thermal_Foldback 0x33
76 #define CS43L22_MAP_Thermal_Foldback 0x33
77 #define CS43L22_MAP_Charge_Pump_Frequency 0x34
77 #define CS43L22_MAP_Charge_Pump_Frequency 0x34
78
78
79
79
80 #endif
80 #endif
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@@ -1,31 +1,56
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the libuc, microcontroler library
2 -- This file is a part of the libuc, microcontroler library
3 -- Copyright (C) 2012, Alexis Jeandet
3 -- Copyright (C) 2012, Alexis Jeandet
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@gmail.com
20 -- Mail : alexis.jeandet@gmail.com
21 -------------------------------------------------------------------------------*/
21 -------------------------------------------------------------------------------*/
22 #include <CS43L22.h>
23 #include <stdio.h>
24 #include <stddef.h>
25 #include <spi.h>
26
27 int cs43l22open(CS43L22_t* dev,i2c_t i2cdev, uint8_t A0)
28 {
29 if(dev != NULL)
30 {
31 dev->i2cdev=i2cdev;
32 dev->devAddress = CS43L22_I2C_ADDRESS | (A0 & 1);
33 return 1;
34 }
35 return -1;
36 }
37
38 uint8_t cs43l22getID(CS43L22_t* dev)
39 {
40 if(dev != NULL)
41 {
42 char DATA[]={CS43L22_MAP_ID};
43 i2cwrite(dev->i2cdev,dev->devAddress,DATA,1);
44 i2cread(dev->i2cdev,dev->devAddress,DATA,1);
45 return DATA[0];
46 }
47 return -1;
48 }
22
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@@ -1,282 +1,292
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the libuc, microcontroler library
2 -- This file is a part of the libuc, microcontroler library
3 -- Copyright (C) 2012, Alexis Jeandet
3 -- Copyright (C) 2012, Alexis Jeandet
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@gmail.com
20 -- Mail : alexis.jeandet@gmail.com
21 -------------------------------------------------------------------------------*/
21 -------------------------------------------------------------------------------*/
22
22
23 #include <i2c.h>
23 #include <i2c.h>
24 #include <stm32f4xx_usart.h>
24 #include <stm32f4xx_usart.h>
25 #include <stm32f4xx_rcc.h>
25 #include <stm32f4xx_rcc.h>
26 #include <stm32f4xx_gpio.h>
26 #include <stm32f4xx_gpio.h>
27 #include <gpio.h>
27 #include <gpio.h>
28 #include <core.h>
28 #include <core.h>
29
29
30 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
30 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
31 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
31 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
32
32
33
33
34 I2C_TypeDef* _i2c_dev_table[3]={I2C1,I2C2,I2C3};
34 I2C_TypeDef* _i2c_dev_table[3]={I2C1,I2C2,I2C3};
35
35
36 i2c_t i2copen(int count)
36 i2c_t i2copen(int count)
37 {
37 {
38 #define _INIT_DEV(_RCC_) \
38 #define _INIT_DEV(_RCC_) \
39 RCC_APB1PeriphClockCmd(_RCC_, ENABLE); \
39 RCC_APB1PeriphClockCmd(_RCC_, ENABLE); \
40 RCC_APB1PeriphResetCmd(_RCC_, ENABLE); \
40 RCC_APB1PeriphResetCmd(_RCC_, ENABLE); \
41 RCC_APB1PeriphResetCmd(_RCC_, DISABLE); \
41 RCC_APB1PeriphResetCmd(_RCC_, DISABLE); \
42 RCC_APB1PeriphClockCmd(_RCC_, ENABLE);
42 RCC_APB1PeriphClockCmd(_RCC_, ENABLE);
43
43
44 switch(count)
44 switch(count)
45 {
45 {
46 case 0:
46 case i2c1:
47 _INIT_DEV(RCC_APB1Periph_I2C1);
47 _INIT_DEV(RCC_APB1Periph_I2C1);
48 return (i2c_t) 0;
48 return i2c1;
49 break;
49 break;
50 case 1:
50 case i2c2:
51 _INIT_DEV(RCC_APB1Periph_I2C2);
51 _INIT_DEV(RCC_APB1Periph_I2C2);
52 return (i2c_t) 1;
52 return i2c2;
53 break;
53 break;
54 case 2:
54 case i2c3:
55 _INIT_DEV(RCC_APB1Periph_I2C3);
55 _INIT_DEV(RCC_APB1Periph_I2C3);
56 return (i2c_t) 2;
56 return i2c3;
57 break;
57 break;
58 default:
58 default:
59 break;
59 break;
60 }
60 }
61 return -1;
61 return -1;
62 }
62 }
63
63
64 i2c_t i2copenandconfig(int count,uint32_t cfg,uint32_t speed,uint32_t SDA,uint32_t SCL)
64 i2c_t i2copenandconfig(int count,uint32_t cfg,uint32_t speed,uint32_t SDA,uint32_t SCL)
65 {
65 {
66 i2c_t dev = i2copen(count);
66 i2c_t dev = i2copen(count);
67 if(dev!=-1)
67 if(dev!=-1)
68 {
68 {
69 i2cclose(dev);
69 i2cclose(dev);
70 i2csetpins(dev,SDA,SCL);
70 i2csetpins(dev,SDA,SCL);
71 i2copen(count);
71 i2copen(count);
72 i2cenable(count);
72 i2cenable(count);
73 //I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
73 //I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
74 i2csetspeed(dev,speed);
74 i2csetspeed(dev,speed);
75 i2cenable(count);
75 i2cenable(count);
76 }
76 }
77 return dev;
77 return dev;
78 }
78 }
79
79
80 int i2cclose(i2c_t dev)
80 int i2cclose(i2c_t dev)
81 {
81 {
82 switch((int)dev)
82 switch(dev)
83 {
83 {
84 case (int)0:
84 case i2c1:
85 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
85 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
86 break;
86 break;
87 case (int)1:
87 case i2c2:
88 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
88 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
89 break;
89 break;
90 case (int)2:
90 case i2c3:
91 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, ENABLE);
91 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, ENABLE);
92 break;
92 break;
93 default:
93 default:
94 break;
94 break;
95 }
95 }
96 return 1;
96 return 1;
97 }
97 }
98
98
99 int i2csetpins(i2c_t dev, uint32_t SDA, uint32_t SCL)
99 int i2csetpins(i2c_t dev, uint32_t SDA, uint32_t SCL)
100 {
100 {
101 if((dev<3)&&(dev>=0))
101 if((dev<3)&&(dev>=0))
102 {
102 {
103 gpio_t SDApin,SCLpin;
103 gpio_t SDApin,SCLpin;
104 SDApin = gpioopen(SDA);
104 SDApin = gpioopen(SDA);
105 SCLpin = gpioopen(SCL);
105 SCLpin = gpioopen(SCL);
106 SDApin |= gpiolowspeed | gpioaf | gpioopendraintype | gpionopulltype;
106 SDApin |= gpiolowspeed | gpioaf | gpioopendraintype | gpionopulltype;
107 SCLpin |= gpiolowspeed | gpiooutdir | gpioopendraintype | gpionopulltype;
108 gpiosetconfig(&SCLpin);
109 for(int i=0;i<32;i++)
110 {
111 gpioclr(SCLpin);
112 for(int l=0;l<200;l++)
113 {__asm__("nop");}
114 gpioset(SCLpin);
115 for(int l=0;l<200;l++)
116 {__asm__("nop");}
117 }
118 SCLpin = gpioopen(SCL);
107 SCLpin |= gpiolowspeed | gpioaf | gpioopendraintype | gpionopulltype;
119 SCLpin |= gpiolowspeed | gpioaf | gpioopendraintype | gpionopulltype;
108 gpiosetconfig(&SDApin);
120 gpiosetconfig(&SDApin);
109 gpiosetconfig(&SCLpin);
121 gpiosetconfig(&SCLpin);
110 uint8_t gpioAFi2cx = GPIO_AF_I2C1;
122 uint8_t gpioAFi2cx = GPIO_AF_I2C1;
111 switch((int)dev)
123 switch(dev)
112 {
124 {
113 case 0:
125 case i2c1:
114 gpioAFi2cx = GPIO_AF_I2C1;
126 gpioAFi2cx = GPIO_AF_I2C1;
115 break;
127 break;
116 case 1:
128 case i2c2:
117 gpioAFi2cx = GPIO_AF_I2C2;
129 gpioAFi2cx = GPIO_AF_I2C2;
118 break;
130 break;
119 case 2:
131 case i2c3:
120 gpioAFi2cx = GPIO_AF_I2C3;
132 gpioAFi2cx = GPIO_AF_I2C3;
121 break;
133 break;
122 default:
134 default:
123 break;
135 break;
124 }
136 }
125 GPIO_PinAFConfig(GPIOGETPORT(SDApin), (uint8_t)(SDApin & 0xF), gpioAFi2cx);
137 GPIO_PinAFConfig(GPIOGETPORT(SDApin), (uint8_t)(SDApin & 0xF), gpioAFi2cx);
126 GPIO_PinAFConfig(GPIOGETPORT(SCLpin), (uint8_t)(SCLpin & 0xF), gpioAFi2cx);
138 GPIO_PinAFConfig(GPIOGETPORT(SCLpin), (uint8_t)(SCLpin & 0xF), gpioAFi2cx);
127 return 0;
139 return 0;
128 }
140 }
129 return -1;
141 return -1;
130 }
142 }
131
143
132 int i2cenable(i2c_t dev)
144 int i2cenable(i2c_t dev)
133 {
145 {
134 if((dev<3)&&(dev>=0))
146 if((dev<3)&&(dev>=0))
135 {
147 {
136 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
148 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
137 _dev_->CR1 |=1 ;
149 _dev_->CR1 |=1 ;
138 return 0;
150 return 0;
139 }
151 }
140 return -1;
152 return -1;
141 }
153 }
142
154
143 int i2cdisable(i2c_t dev)
155 int i2cdisable(i2c_t dev)
144 {
156 {
145 if((dev<3)&&(dev>=0))
157 if((dev<3)&&(dev>=0))
146 {
158 {
147 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
159 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
148 _dev_->CR1 &= ~1;
160 _dev_->CR1 &= ~1;
149 return 0;
161 return 0;
150 }
162 }
151 return -1;
163 return -1;
152 }
164 }
153
165
154
166
155 int i2csetspeed(i2c_t dev,uint32_t speed)
167 int i2csetspeed(i2c_t dev,uint32_t speed)
156 {
168 {
157 if((dev<3)&&(dev>=0))
169 if((dev<3)&&(dev>=0))
158 {
170 {
159 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
171 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
160 int32_t APB1Freq=getAPB1Freq()/1000000;
172 int32_t APB1Freq=getAPB1Freq()/1000000;
161 if((APB1Freq>1)&&(APB1Freq<43))
173 if((APB1Freq>1)&&(APB1Freq<43))
162 {
174 {
163
175
164 uint16_t tmpreg=_dev_->CR2;
176 uint16_t tmpreg=_dev_->CR2;
165 tmpreg &= ~(0x1f);
177 tmpreg &= ~(0x1f);
166 tmpreg |= APB1Freq;
178 tmpreg |= APB1Freq;
167 _dev_->CR2=tmpreg;
179 _dev_->CR2=tmpreg;
168 i2cdisable(dev);
180 i2cdisable(dev);
169 tmpreg=_dev_->CCR;
181 tmpreg=_dev_->CCR;
170 APB1Freq=getAPB1Freq();
182 APB1Freq=getAPB1Freq();
171 if(speed>100000) //100kHz= standard mode, 400kHz= fast mode
183 if(speed>100000) //100kHz= standard mode, 400kHz= fast mode
172 {
184 {
173 if(speed<=400000)
185 if(speed<=400000)
174 {
186 {
175 tmpreg |= 1<<15;
187 tmpreg |= 1<<15;
176 tmpreg &= ~(1<<14);
188 tmpreg &= ~(1<<14);
177 tmpreg &= ~(0xfff);
189 tmpreg &= ~(0xfff);
178 tmpreg |= 0xfff & (APB1Freq/(3*speed));
190 tmpreg |= 0xfff & (APB1Freq/(3*speed));
179 }
191 }
180 }
192 }
181 else
193 else
182 {
194 {
183 tmpreg &= ~(1<<15);
195 tmpreg &= ~(1<<15);
184 tmpreg &= ~(0xfff);
196 tmpreg &= ~(0xfff);
185 tmpreg |= 0xfff & (APB1Freq/(2*speed));
197 tmpreg |= 0xfff & (APB1Freq/(2*speed));
186 }
198 }
187 _dev_->CCR=tmpreg;
199 _dev_->CCR=tmpreg;
188 tmpreg=_dev_->TRISE;
200 tmpreg=_dev_->TRISE;
189 tmpreg &= ~(0x3f);
201 tmpreg &= ~(0x3f);
190 tmpreg |= (APB1Freq/1000000)+1;
202 tmpreg |= (APB1Freq/1000000)+1;
191 _dev_->TRISE = tmpreg;
203 _dev_->TRISE = tmpreg;
192 i2cenable(dev);
204 i2cenable(dev);
193 return 0;
205 return 0;
194 }
206 }
195 }
207 }
196 return -1;
208 return -1;
197 }
209 }
198
210
199 int i2cbusy(i2c_t dev)
211 int i2cbusy(i2c_t dev)
200 {
212 {
201 if((dev<3)&&(dev>=0))
213 if((dev<3)&&(dev>=0))
202 {
214 {
203 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
215 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
204 if((_dev_->SR2 & 2) ==2) return 1; /* Dev is busy */
216 if((_dev_->SR2 & 2) ==2) return 1; /* Dev is busy */
205 return 0; /* Dev isn't busy */
217 return 0; /* Dev isn't busy */
206 }
218 }
207 return -1; /* Error, dev is out of range */
219 return -1; /* Error, dev is out of range */
208 }
220 }
209
221
210 int i2cwrite(i2c_t dev,char address,char* data,int count)
222 int i2cwrite(i2c_t dev,char address,char* data,int count)
211 {
223 {
212 if((dev<3)&&(dev>=0))
224 if((dev<3)&&(dev>=0))
213 {
225 {
214 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
226 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
215 while(i2cbusy(dev));
227 while(i2cbusy(dev));
216 _dev_->CR1 |= 1<<8;
228 _dev_->CR1 |= 1<<8;
217 while(!i2cStatusCheck(dev,((uint32_t)0x00030001)));
229 while(!i2cStatusCheck(dev,((uint32_t)0x00030001)));
218 _dev_->DR= address<<1;
230 _dev_->DR= address<<1;
219 while(!i2cStatusCheck(dev, ((uint32_t)0x00070082)));
231 while(!i2cStatusCheck(dev, ((uint32_t)0x00070082)));
220 address=_dev_->SR2;
232 address=_dev_->SR2;
221 for(int i=0;i<count;i++)
233 for(int i=0;i<count;i++)
222 {
234 {
223 while(!i2cStatusCheck(dev,((uint32_t)0x00070080)));
235 while(!i2cStatusCheck(dev,((uint32_t)0x00070080)));
224 _dev_->DR= data[i];
236 _dev_->DR= data[i];
225 }
237 }
226 while(!i2cStatusCheck(dev,1<<7));
238 while(!i2cStatusCheck(dev,1<<7));
227 while(!i2cStatusCheck(dev,1<<2));
239 while(!i2cStatusCheck(dev,1<<2));
228 _dev_->CR1 |= 1<<9;
240 _dev_->CR1 |= 1<<9;
229 return count;
241 return count;
230 }
242 }
231 return -1;
243 return -1;
232 }
244 }
233
245
234 int i2cread(i2c_t dev,char address,char* data,int count)
246 int i2cread(i2c_t dev,char address,char* data,int count)
235 {
247 {
236 if((dev<3)&&(dev>=0))
248 if((dev<3)&&(dev>=0))
237 {
249 {
238 while(i2cbusy(dev));
250 while(i2cbusy(dev));
239 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
251 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
240 _dev_->CR1 |= (1<<8) | (1<<10);
252 _dev_->CR1 |= (1<<8) | (1<<10);
253 while(!i2cStatusCheck(dev,0x00030001));
254 _dev_->DR= (address<<1) + 1;
255 while(!i2cStatusCheck(dev, ((uint32_t)0x00070082)));
241 if(count==1)
256 if(count==1)
242 {
257 {
243 _dev_->CR1 &= ~(1<<10);
258 _dev_->CR1 &= ~(1<<10);
244 }
259 }
245 while(!i2cStatusCheck(dev,0x00030001));
246 _dev_->DR= (address<<1) + 1;
247 while(!i2cStatusCheck(dev, ((uint32_t)0x00070082)));
248 address=_dev_->SR2;
260 address=_dev_->SR2;
249 for(int i=0;i<count-1;i++)
261 for(int i=0;i<(count-1);i++)
250 {
262 {
251 while((_dev_->SR1 & (1<<6))==0);
263 while((_dev_->SR1 & (1<<6))==0);
252 data[i]=_dev_->DR;
264 data[i]=_dev_->DR;
253 }
265 }
254 _dev_->CR1 &= ~(1<<10);
266 _dev_->CR1 &= ~(1<<10);
255 _dev_->CR1 |= 1<<9;
267 _dev_->CR1 |= 1<<9;
256 while((_dev_->SR1 & (1<<6))==0);
268 while(!i2cStatusCheck(dev, ((uint32_t)0x10000040)));
257 data[count-1]=_dev_->DR;
269 data[count-1]=_dev_->DR;
270 while(_dev_->CR1 & ((uint16_t)0x0200));
271 _dev_->CR1 |= 1<<10;
258 return count;
272 return count;
259 }
273 }
260 return -1;
274 return -1;
261 }
275 }
262
276
263
277
264 int i2cStatusCheck(i2c_t dev,int32_t flagMask)
278 int i2cStatusCheck(i2c_t dev,int32_t flagMask)
265 {
279 {
266 int32_t flag;
280 int32_t flag;
267 __asm__("nop");
268 __asm__("nop");
269 __asm__("nop");
270 __asm__("nop");
271 if((dev<3)&&(dev>=0))
281 if((dev<3)&&(dev>=0))
272 {
282 {
273 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
283 I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev];
274 flag= _dev_->SR1 + (_dev_->SR2<<16);
284 flag= _dev_->SR1 + (_dev_->SR2<<16);
275 if(flagMask==(flag & flagMask))
285 if(flagMask==(flag & flagMask))
276 return 1;
286 return 1;
277 return 0;
287 return 0;
278 }
288 }
279 return -1;
289 return -1;
280 }
290 }
281
291
282
292
@@ -1,437 +1,437
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the libuc, microcontroler library
2 -- This file is a part of the libuc, microcontroler library
3 -- Copyright (C) 2011, Alexis Jeandet
3 -- Copyright (C) 2011, Alexis Jeandet
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@gmail.com
20 -- Mail : alexis.jeandet@gmail.com
21 -------------------------------------------------------------------------------*/
21 -------------------------------------------------------------------------------*/
22
22
23 #include <spi.h>
23 #include <spi.h>
24 #include <stm32f4xx_rcc.h>
24 #include <stm32f4xx_rcc.h>
25 #include <stm32f4xx_gpio.h>
25 #include <stm32f4xx_gpio.h>
26 #include <gpio.h>
26 #include <gpio.h>
27 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
27 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
28 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
28 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
29
29
30
30
31 SPI_TypeDef* _spi_dev_table[3]={SPI1,SPI2,SPI3};
31 SPI_TypeDef* _spi_dev_table[3]={SPI1,SPI2,SPI3};
32
32
33 spi_t spiopen(int count)
33 spi_t spiopen(int count)
34 {
34 {
35 #define _INIT_DEV(_RCC_) \
35 #define _INIT_DEV(_RCC_) \
36 RCC_APB1PeriphClockCmd(_RCC_, ENABLE); \
36 RCC_APB1PeriphClockCmd(_RCC_, ENABLE); \
37 RCC_APB1PeriphResetCmd(_RCC_, ENABLE); \
37 RCC_APB1PeriphResetCmd(_RCC_, ENABLE); \
38 RCC_APB1PeriphResetCmd(_RCC_, DISABLE); \
38 RCC_APB1PeriphResetCmd(_RCC_, DISABLE); \
39 RCC_APB1PeriphClockCmd(_RCC_, ENABLE);
39 RCC_APB1PeriphClockCmd(_RCC_, ENABLE);
40
40
41 switch(count)
41 switch(count)
42 {
42 {
43 case 0:
43 case spi1:
44 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
44 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
45 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
45 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
46 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
46 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
47 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
47 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
48 return (spi_t) 0;
48 return spi1;
49 break;
49 break;
50 case 1:
50 case spi2:
51 _INIT_DEV(RCC_APB1Periph_SPI2);
51 _INIT_DEV(RCC_APB1Periph_SPI2);
52 return (spi_t) 1;
52 return spi2;
53 break;
53 break;
54 case 2:
54 case spi3:
55 _INIT_DEV(RCC_APB1Periph_SPI3);
55 _INIT_DEV(RCC_APB1Periph_SPI3);
56 return (spi_t) 2;
56 return spi3;
57 break;
57 break;
58 default:
58 default:
59 break;
59 break;
60 }
60 }
61 return -1;
61 return -1;
62 }
62 }
63
63
64 spi_t spiopenandconfig(int count, uint32_t cfg, uint32_t speed, uint32_t MOSIpin, uint32_t MISOpin, uint32_t SCKpin, uint32_t SCSpin)
64 spi_t spiopenandconfig(int count, uint32_t cfg, uint32_t speed, uint32_t MOSIpin, uint32_t MISOpin, uint32_t SCKpin, uint32_t SCSpin)
65 {
65 {
66 spi_t dev = spiopen(count);
66 spi_t dev = spiopen(count);
67 if(dev!=-1)
67 if(dev!=-1)
68 {
68 {
69 spidisable(dev);
69 spidisable(dev);
70 spisetpins(dev,MOSIpin, MISOpin, SCKpin, SCSpin);
70 spisetpins(dev,MOSIpin, MISOpin, SCKpin, SCSpin);
71 spienable(dev);
71 spienable(dev);
72 spisetconfig(dev,cfg,speed);
72 spisetconfig(dev,cfg,speed);
73 }
73 }
74 return dev;
74 return dev;
75 }
75 }
76
76
77
77
78 int spiclose(spi_t spidev)
78 int spiclose(spi_t spidev)
79 {
79 {
80 if((spidev<3)&&(spidev>=0))
80 if((spidev<3)&&(spidev>=0))
81 {
81 {
82 switch(spidev)
82 switch(spidev)
83 {
83 {
84 case 0:
84 case spi1:
85 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
85 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
86 break;
86 break;
87 case 1:
87 case spi2:
88 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
88 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
89 break;
89 break;
90 case 2:
90 case spi3:
91 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
91 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
92 break;
92 break;
93 default:
93 default:
94 return -1;
94 return -1;
95 break;
95 break;
96 }
96 }
97 return 1;
97 return 1;
98 }
98 }
99 return -1;
99 return -1;
100 }
100 }
101
101
102 int spisetpins(spi_t spidev,uint32_t MOSIpin,uint32_t MISOpin,uint32_t SCKpin,uint32_t SCSpin)
102 int spisetpins(spi_t spidev,uint32_t MOSIpin,uint32_t MISOpin,uint32_t SCKpin,uint32_t SCSpin)
103 {
103 {
104 if((spidev<3)&&(spidev>=0))
104 if((spidev<3)&&(spidev>=0))
105 {
105 {
106 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
106 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
107 gpio_t MISO,MOSI,SCK,SCS;
107 gpio_t MISO,MOSI,SCK,SCS;
108 uint8_t gpioAFspix = GPIO_AF_SPI1;
108 uint8_t gpioAFspix = GPIO_AF_SPI1;
109 switch(spidev)
109 switch(spidev)
110 {
110 {
111 case 0:
111 case spi1:
112 gpioAFspix = GPIO_AF_SPI1;
112 gpioAFspix = GPIO_AF_SPI1;
113 break;
113 break;
114 case 1:
114 case spi2:
115 gpioAFspix = GPIO_AF_SPI2;
115 gpioAFspix = GPIO_AF_SPI2;
116 break;
116 break;
117 case 2:
117 case spi3:
118 gpioAFspix = GPIO_AF_SPI3;
118 gpioAFspix = GPIO_AF_SPI3;
119 break;
119 break;
120 default:
120 default:
121 break;
121 break;
122 }
122 }
123 if(MISOpin!=-1)
123 if(MISOpin!=-1)
124 {
124 {
125 MISO = gpioopen(MISOpin);
125 MISO = gpioopen(MISOpin);
126 MISO |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
126 MISO |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
127 gpiosetconfig(&MISO);
127 gpiosetconfig(&MISO);
128 GPIO_PinAFConfig(GPIOGETPORT(MISO), (uint8_t)(MISO & 0xF), gpioAFspix);
128 GPIO_PinAFConfig(GPIOGETPORT(MISO), (uint8_t)(MISO & 0xF), gpioAFspix);
129 }
129 }
130 if(MOSIpin!=-1)
130 if(MOSIpin!=-1)
131 {
131 {
132 MOSI = gpioopen(MOSIpin);
132 MOSI = gpioopen(MOSIpin);
133 MOSI |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
133 MOSI |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
134 gpiosetconfig(&MOSI);
134 gpiosetconfig(&MOSI);
135 GPIO_PinAFConfig(GPIOGETPORT(MOSI), (uint8_t)(MOSI & 0xF), gpioAFspix);
135 GPIO_PinAFConfig(GPIOGETPORT(MOSI), (uint8_t)(MOSI & 0xF), gpioAFspix);
136 }
136 }
137
137
138 if(SCKpin!=-1)
138 if(SCKpin!=-1)
139 {
139 {
140 SCK = gpioopen(SCKpin);
140 SCK = gpioopen(SCKpin);
141 SCK |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
141 SCK |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
142 gpiosetconfig(&SCK);
142 gpiosetconfig(&SCK);
143 GPIO_PinAFConfig(GPIOGETPORT(SCK), (uint8_t)(SCK & 0xF), gpioAFspix);
143 GPIO_PinAFConfig(GPIOGETPORT(SCK), (uint8_t)(SCK & 0xF), gpioAFspix);
144 }
144 }
145
145
146 if(SCSpin!=-1)
146 if(SCSpin!=-1)
147 {
147 {
148 SCS = gpioopen(SCSpin);
148 SCS = gpioopen(SCSpin);
149 SCS |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
149 SCS |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
150 gpiosetconfig(&SCS);
150 gpiosetconfig(&SCS);
151 GPIO_PinAFConfig(GPIOGETPORT(SCS), (uint8_t)(SCS & 0xF), gpioAFspix);
151 GPIO_PinAFConfig(GPIOGETPORT(SCS), (uint8_t)(SCS & 0xF), gpioAFspix);
152 _dev_->CR2 |= (1<<2);
152 _dev_->CR2 |= (1<<2);
153 }
153 }
154 else
154 else
155 {
155 {
156 _dev_->CR2 &= ~(1<<2);
156 _dev_->CR2 &= ~(1<<2);
157 }
157 }
158 return 1;
158 return 1;
159 }
159 }
160 return -1;
160 return -1;
161 }
161 }
162
162
163
163
164 int spienable(spi_t spidev)
164 int spienable(spi_t spidev)
165 {
165 {
166 if((spidev<3)&&(spidev>=0))
166 if((spidev<3)&&(spidev>=0))
167 {
167 {
168 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
168 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
169 _dev_->CR1 |= (1<<6);
169 _dev_->CR1 |= (1<<6);
170 return 1;
170 return 1;
171 }
171 }
172 return -1;
172 return -1;
173 }
173 }
174
174
175
175
176 int spidisable(spi_t spidev)
176 int spidisable(spi_t spidev)
177 {
177 {
178 if((spidev<3)&&(spidev>=0))
178 if((spidev<3)&&(spidev>=0))
179 {
179 {
180 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
180 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
181 _dev_->CR1 &= ~(1<<6);
181 _dev_->CR1 &= ~(1<<6);
182 return 1;
182 return 1;
183 }
183 }
184 return -1;
184 return -1;
185 }
185 }
186
186
187 int spisetconfig(spi_t spidev, uint32_t config, uint32_t speed)
187 int spisetconfig(spi_t spidev, uint32_t config, uint32_t speed)
188 {
188 {
189 if((spidev<3)&&(spidev>=0))
189 if((spidev<3)&&(spidev>=0))
190 {
190 {
191 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
191 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
192 _dev_->CR2 |= (1<<2);
192 _dev_->CR2 |= (1<<2);
193 _dev_->CR1 |= (1<<2);
193 _dev_->CR1 |= (1<<2);
194 spisetspeed(spidev,speed);
194 spisetspeed(spidev,speed);
195 spisetdatabits(spidev,config & SPIBITSMASK);
195 spisetdatabits(spidev,config & SPIBITSMASK);
196 spisetbitorder(spidev,config & SPIBITORDERMASK);
196 spisetbitorder(spidev,config & SPIBITORDERMASK);
197 spisetclkinhlevel(spidev,config & SPICLKINHLVLMASK);
197 spisetclkinhlevel(spidev,config & SPICLKINHLVLMASK);
198 spisetclkphase(spidev,config & SPICLKPHASEMASK);
198 spisetclkphase(spidev,config & SPICLKPHASEMASK);
199 return 0;
199 return 0;
200 }
200 }
201 return 1;
201 return 1;
202 }
202 }
203
203
204 int spisetspeed(spi_t spidev, uint32_t speed)
204 int spisetspeed(spi_t spidev, uint32_t speed)
205 {
205 {
206 if((spidev<3)&&(spidev>=0))
206 if((spidev<3)&&(spidev>=0))
207 {
207 {
208 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
208 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
209 uint32_t apbclock = 0x00;
209 uint32_t apbclock = 0x00;
210 RCC_ClocksTypeDef RCC_ClocksStatus;
210 RCC_ClocksTypeDef RCC_ClocksStatus;
211 RCC_GetClocksFreq(&RCC_ClocksStatus);
211 RCC_GetClocksFreq(&RCC_ClocksStatus);
212 if (_dev_ == SPI1)
212 if (_dev_ == SPI1)
213 {
213 {
214 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
214 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
215 }
215 }
216 else
216 else
217 {
217 {
218 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
218 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
219 }
219 }
220 int32_t speederror = 0x7FFFFFFF; //max error
220 int32_t speederror = 0x7FFFFFFF; //max error
221 int32_t prev_speederror = 0x7FFFFFFF;
221 int32_t prev_speederror = 0x7FFFFFFF;
222 int32_t realspeed = 0;
222 int32_t realspeed = 0;
223 unsigned char divider = 0;
223 unsigned char divider = 0;
224 do
224 do
225 {
225 {
226 divider ++;
226 divider ++;
227 prev_speederror = speederror;
227 prev_speederror = speederror;
228 realspeed = apbclock>>(divider);
228 realspeed = apbclock>>(divider);
229 speederror = realspeed - speed;
229 speederror = realspeed - speed;
230 if(speederror<0)speederror=-speederror;
230 if(speederror<0)speederror=-speederror;
231 if(divider>8)break;
231 if(divider>8)break;
232 }while(speederror<prev_speederror);
232 }while(speederror<prev_speederror);
233 speed = apbclock>>(divider-1);
233 speed = apbclock>>(divider-1);
234 divider-=2;
234 divider-=2;
235 _dev_->CR1 &= 0xFFD7; // clear prescaler bits 3:5
235 _dev_->CR1 &= 0xFFD7; // clear prescaler bits 3:5
236 _dev_->CR1 |= ((0x7 & divider)<<3);
236 _dev_->CR1 |= ((0x7 & divider)<<3);
237 return 1;
237 return 1;
238 }
238 }
239 return -1;
239 return -1;
240 }
240 }
241
241
242
242
243 int spisetdatabits(spi_t spidev,spibits_t bitscnt)
243 int spisetdatabits(spi_t spidev,spibits_t bitscnt)
244 {
244 {
245 if((spidev<3)&&(spidev>=0))
245 if((spidev<3)&&(spidev>=0))
246 {
246 {
247 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
247 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
248 int result = 0;
248 int result = 0;
249 switch(bitscnt)
249 switch(bitscnt)
250 {
250 {
251 case spi8bits:
251 case spi8bits:
252 _dev_->CR1 &= ~(1<<11);
252 _dev_->CR1 &= ~(1<<11);
253 result = 1;
253 result = 1;
254 break;
254 break;
255 case spi16bits:
255 case spi16bits:
256 _dev_->CR1 |= (1<<11);
256 _dev_->CR1 |= (1<<11);
257 result = 1;
257 result = 1;
258 break;
258 break;
259 default:
259 default:
260 result =-1;
260 result =-1;
261 break;
261 break;
262 }
262 }
263 return result;
263 return result;
264 }
264 }
265 return -1;
265 return -1;
266 }
266 }
267
267
268 int spisetbitorder(spi_t spidev,spibitorder_t order)
268 int spisetbitorder(spi_t spidev,spibitorder_t order)
269 {
269 {
270 if((spidev<3)&&(spidev>=0))
270 if((spidev<3)&&(spidev>=0))
271 {
271 {
272 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
272 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
273 if(order==spimsbfirst)
273 if(order==spimsbfirst)
274 {
274 {
275 _dev_->CR1 &= ~(1<<7);
275 _dev_->CR1 &= ~(1<<7);
276 return 1;
276 return 1;
277 }
277 }
278 else
278 else
279 {
279 {
280 if(order==spilsbfirst)
280 if(order==spilsbfirst)
281 {
281 {
282 _dev_->CR1 |= (1<<7);
282 _dev_->CR1 |= (1<<7);
283 return 1;
283 return 1;
284 }
284 }
285 else return -1;
285 else return -1;
286 }
286 }
287 }
287 }
288 return -1;
288 return -1;
289 }
289 }
290
290
291 int spisetclkinhlevel(spi_t spidev,spiclkinhlvl_t level)
291 int spisetclkinhlevel(spi_t spidev,spiclkinhlvl_t level)
292 {
292 {
293 if((spidev<3)&&(spidev>=0))
293 if((spidev<3)&&(spidev>=0))
294 {
294 {
295 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
295 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
296 if(level==spiclkinhlow)
296 if(level==spiclkinhlow)
297 {
297 {
298 _dev_->CR1 &= ~(1<<1);
298 _dev_->CR1 &= ~(1<<1);
299 return 1;
299 return 1;
300 }
300 }
301 else
301 else
302 {
302 {
303 if(level==spiclkinhhigh)
303 if(level==spiclkinhhigh)
304 {
304 {
305 _dev_->CR1 |= (1<<1);
305 _dev_->CR1 |= (1<<1);
306 return 1;
306 return 1;
307 }
307 }
308 else return -1;
308 else return -1;
309 }
309 }
310 }
310 }
311 return -1;
311 return -1;
312 }
312 }
313
313
314 int spisetclkphase(spi_t spidev,spiclkphase_t phase)
314 int spisetclkphase(spi_t spidev,spiclkphase_t phase)
315 {
315 {
316 if((spidev<3)&&(spidev>=0))
316 if((spidev<3)&&(spidev>=0))
317 {
317 {
318 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
318 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
319 if(phase==spiclkfirstedge)
319 if(phase==spiclkfirstedge)
320 {
320 {
321 _dev_->CR1 &= ~1;
321 _dev_->CR1 &= ~1;
322 return 1;
322 return 1;
323 }
323 }
324 else
324 else
325 {
325 {
326 if(phase==spiclksecondedge)
326 if(phase==spiclksecondedge)
327 {
327 {
328 _dev_->CR1 |= 1;
328 _dev_->CR1 |= 1;
329 return 1;
329 return 1;
330 }
330 }
331 else return -1;
331 else return -1;
332 }
332 }
333 }
333 }
334 return -1;
334 return -1;
335 }
335 }
336
336
337 int spiputw(spi_t spidev,uint16_t data)
337 int spiputw(spi_t spidev,uint16_t data)
338 {
338 {
339 if((spidev<3)&&(spidev>=0))
339 if((spidev<3)&&(spidev>=0))
340 {
340 {
341 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
341 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
342 _dev_->DR = data;
342 _dev_->DR = data;
343 while((_dev_->SR & (1<<7)) == (1<<7));
343 while((_dev_->SR & (1<<7)) == (1<<7));
344 return 1;
344 return 1;
345 }
345 }
346 return -1;
346 return -1;
347 }
347 }
348 uint16_t spigetw(spi_t spidev)
348 uint16_t spigetw(spi_t spidev)
349 {
349 {
350 if((spidev<3)&&(spidev>=0))
350 if((spidev<3)&&(spidev>=0))
351 {
351 {
352 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
352 SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
353 while((_dev_->SR & (1<<7)) == (1<<7));
353 while((_dev_->SR & (1<<7)) == (1<<7));
354 _dev_->DR = 0xFFFF;
354 _dev_->DR = 0xFFFF;
355 while((_dev_->SR & (1<<0)) == 0);
355 while((_dev_->SR & (1<<0)) == 0);
356 return _dev_->DR;
356 return _dev_->DR;
357 }
357 }
358 return -1;
358 return -1;
359 }
359 }
360
360
361 int spiputs(spi_t spidev,char* s)
361 int spiputs(spi_t spidev,char* s)
362 {
362 {
363 while (*s) spiputw(spidev,*s++);
363 while (*s) spiputw(spidev,*s++);
364 return 1;
364 return 1;
365 }
365 }
366
366
367 int spigets(spi_t spidev,char* s)
367 int spigets(spi_t spidev,char* s)
368 {
368 {
369 do
369 do
370 {
370 {
371 (*s) = spigetw(spidev);
371 (*s) = spigetw(spidev);
372 }
372 }
373 while(*s++);
373 while(*s++);
374 return 1;
374 return 1;
375 }
375 }
376
376
377 int spiputnw(spi_t spidev,uint16_t* w,int n)
377 int spiputnw(spi_t spidev,uint16_t* w,int n)
378 {
378 {
379 while(n!=0)
379 while(n!=0)
380 {
380 {
381 spiputw(spidev,*w++);
381 spiputw(spidev,*w++);
382 n--;
382 n--;
383 }
383 }
384 return 1;
384 return 1;
385 }
385 }
386
386
387 int spigetnw(spi_t spidev,uint16_t* w,int n)
387 int spigetnw(spi_t spidev,uint16_t* w,int n)
388 {
388 {
389 while(n!=0)
389 while(n!=0)
390 {
390 {
391 *w++=spigetw(spidev);
391 *w++=spigetw(spidev);
392 n--;
392 n--;
393 }
393 }
394 return 1;
394 return 1;
395 }
395 }
396
396
397 int spiputnc(spi_t spidev,char* c,int n)
397 int spiputnc(spi_t spidev,char* c,int n)
398 {
398 {
399 while(n!=0)
399 while(n!=0)
400 {
400 {
401 spiputw(spidev,*c++);
401 spiputw(spidev,*c++);
402 n--;
402 n--;
403 }
403 }
404 return 1;
404 return 1;
405 }
405 }
406
406
407 int spigetnc(spi_t spidev,char* c,int n)
407 int spigetnc(spi_t spidev,char* c,int n)
408 {
408 {
409 while(n!=0)
409 while(n!=0)
410 {
410 {
411 *c++=spigetw(spidev);
411 *c++=spigetw(spidev);
412 n--;
412 n--;
413 }
413 }
414 return 1;
414 return 1;
415 }
415 }
416
416
417 int spiavailiabledata(spi_t spidev)
417 int spiavailiabledata(spi_t spidev)
418 {
418 {
419 return 0;
419 return 0;
420 }
420 }
421
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@@ -1,463 +1,450
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the libuc, microcontroler library
2 -- This file is a part of the libuc, microcontroler library
3 -- Copyright (C) 2011, Alexis Jeandet
3 -- Copyright (C) 2011, Alexis Jeandet
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@gmail.com
20 -- Mail : alexis.jeandet@gmail.com
21 -------------------------------------------------------------------------------*/
21 -------------------------------------------------------------------------------*/
22
22
23 #include <uart.h>
23 #include <uart.h>
24 #include <stm32f4xx_usart.h>
24 #include <stm32f4xx_usart.h>
25 #include <stm32f4xx_rcc.h>
25 #include <stm32f4xx_rcc.h>
26 #include <stm32f4xx_gpio.h>
26 #include <stm32f4xx_gpio.h>
27 #include <gpio.h>
27 #include <gpio.h>
28 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
28 #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
29 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
29 #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
30
30
31 USART_TypeDef* _uart_dev_table[6]={USART1,USART2,USART3,UART4,UART5,USART6};
31 USART_TypeDef* _uart_dev_table[6]={USART1,USART2,USART3,UART4,UART5,USART6};
32
32
33
33
34 uart_t uartopen(int count)
34 uart_t uartopen(int count)
35 {
35 {
36
36
37 switch(count)
37 switch(count)
38 {
38 {
39 case 0:
39 case uart1:
40 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
40 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
41 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
41 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
42 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
42 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
43 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
43 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
44 USART1->CR3 &= ~((1<<8) + (1<<9));
44 USART1->CR3 &= ~((1<<8) + (1<<9));
45 return (uart_t)0;
45 return uart1;
46 break;
46 break;
47 case 1:
47 case uart2:
48 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
48 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
49 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
49 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
50 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
50 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
51 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
51 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
52 USART2->CR3 &= ~((1<<8) + (1<<9));
52 USART2->CR3 &= ~((1<<8) + (1<<9));
53 return (uart_t)1;
53 return uart2;
54 break;
54 break;
55 case 2:
55 case uart3:
56 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
56 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
57 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
57 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
58 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
58 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
59 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
59 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
60 USART3->CR3 &= ~((1<<8) + (1<<9));
60 USART3->CR3 &= ~((1<<8) + (1<<9));
61 return (uart_t)2;
61 return uart3;
62 break;
62 break;
63 case 3:
63 case uart4:
64 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
64 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
65 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
65 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
66 RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
66 RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
67 UART4->CR3 &= ~((1<<8) + (1<<9));
67 UART4->CR3 &= ~((1<<8) + (1<<9));
68 return (uart_t)3;
68 return uart4;
69 break;
69 break;
70 case 4:
70 case uart5:
71 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
71 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
72 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
72 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
73 RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
73 RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
74 return (uart_t)4;
74 return uart5;
75 break;
75 break;
76 case 5:
76 case uart6:
77 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
77 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
78 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
78 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
79 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
79 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
80 return (uart_t)5;
80 return uart6;
81 break;
81 break;
82 default:
82 default:
83 break;
83 break;
84 }
84 }
85 return -1;
85 return -1;
86 }
86 }
87
87
88 uart_t uartopenandconfig(int count, uint32_t cfg, uint32_t speed, uint32_t TXpin, uint32_t RXpin, uint32_t RTSpin, uint32_t CTSpin)
88 uart_t uartopenandconfig(int count, uint32_t cfg, uint32_t speed, uint32_t TXpin, uint32_t RXpin, uint32_t RTSpin, uint32_t CTSpin)
89 {
89 {
90 uart_t dev= uartopen(count);
90 uart_t dev= uartopen(count);
91 uartsetconfig(dev,cfg,speed);
91 uartsetconfig(dev,cfg,speed);
92 uartsetpins(dev,TXpin,RXpin,RTSpin,CTSpin);
92 uartsetpins(dev,TXpin,RXpin,RTSpin,CTSpin);
93 return 1;
93 return dev;
94 }
94 }
95
95
96
96
97 int uartclose(uart_t uart)
97 int uartclose(uart_t uart)
98 {
98 {
99 switch(uart)
99 switch(uart)
100 {
100 {
101 case 0:
101 case uart1:
102 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
102 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
103 break;
103 break;
104 case 1:
104 case uart2:
105 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
105 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
106 break;
106 break;
107 case 2:
107 case uart3:
108 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
108 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
109 break;
109 break;
110 case 3:
110 case uart4:
111 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
111 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
112 break;
112 break;
113 case 4:
113 case uart5:
114 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
114 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
115 break;
115 break;
116 case 5:
116 case uart6:
117 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
117 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
118 break;
118 break;
119 default:
119 default:
120 return -1;
120 return -1;
121 break;
121 break;
122 }
122 }
123 return 1;
123 return 1;
124 }
124 }
125
125
126 int uartsetpins(uart_t uart,uint32_t TXpin,uint32_t RXpin,uint32_t RTSpin,uint32_t CTSpin)
126 int uartsetpins(uart_t uart,uint32_t TXpin,uint32_t RXpin,uint32_t RTSpin,uint32_t CTSpin)
127 {
127 {
128 if(uart >5)return -1;
128 if(uart >5)return -1;
129 if(uart <0)return -1;
129 if(uart <0)return -1;
130 gpio_t TX,RX,CTS,RTS;
130 gpio_t TX,RX,CTS,RTS;
131 TX = gpioopen(TXpin);
131 TX = gpioopen(TXpin);
132 RX = gpioopen(RXpin);
132 RX = gpioopen(RXpin);
133 TX |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
133 TX |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
134 RX |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
134 RX |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
135 gpiosetconfig(&TX);
135 gpiosetconfig(&TX);
136 gpiosetconfig(&RX);
136 gpiosetconfig(&RX);
137 uint8_t gpioAFuartx = GPIO_AF_USART1;
137 uint8_t gpioAFuartx = GPIO_AF_USART1;
138 switch(uart)
138 switch(uart)
139 {
139 {
140 case 0:
140 case uart1:
141 gpioAFuartx = GPIO_AF_USART1;
141 gpioAFuartx = GPIO_AF_USART1;
142 break;
142 break;
143 case 1:
143 case uart2:
144 gpioAFuartx = GPIO_AF_USART2;
144 gpioAFuartx = GPIO_AF_USART2;
145 break;
145 break;
146 case 2:
146 case uart3:
147 gpioAFuartx = GPIO_AF_USART3;
147 gpioAFuartx = GPIO_AF_USART3;
148 break;
148 break;
149 case 3:
149 case uart4:
150 gpioAFuartx = GPIO_AF_UART4;
150 gpioAFuartx = GPIO_AF_UART4;
151 break;
151 break;
152 case 4:
152 case uart5:
153 gpioAFuartx = GPIO_AF_UART5;
153 gpioAFuartx = GPIO_AF_UART5;
154 break;
154 break;
155 case 5:
155 case uart6:
156 gpioAFuartx = GPIO_AF_USART6;
156 gpioAFuartx = GPIO_AF_USART6;
157 break;
157 break;
158 default:
158 default:
159 return -1;
159 return -1;
160 break;
160 break;
161 }
161 }
162 GPIO_PinAFConfig(GPIOGETPORT(TX), (uint8_t)(TX & 0xF), gpioAFuartx);
162 GPIO_PinAFConfig(GPIOGETPORT(TX), (uint8_t)(TX & 0xF), gpioAFuartx);
163 GPIO_PinAFConfig(GPIOGETPORT(RX), (uint8_t)(RX & 0xF), gpioAFuartx);
163 GPIO_PinAFConfig(GPIOGETPORT(RX), (uint8_t)(RX & 0xF), gpioAFuartx);
164 if((gpioAFuartx!=GPIO_AF_UART5) && (gpioAFuartx!=GPIO_AF_UART4))
164 if((gpioAFuartx!=GPIO_AF_UART5) && (gpioAFuartx!=GPIO_AF_UART4))
165 {
165 {
166 if(CTSpin!=-1)
166 if(CTSpin!=-1)
167 {
167 {
168 CTS = gpioopen(CTSpin);
168 CTS = gpioopen(CTSpin);
169 CTS |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
169 CTS |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
170 gpiosetconfig(&CTS);
170 gpiosetconfig(&CTS);
171 GPIO_PinAFConfig(GPIOGETPORT(CTS), (uint8_t)(CTS & 0xF), gpioAFuartx);
171 GPIO_PinAFConfig(GPIOGETPORT(CTS), (uint8_t)(CTS & 0xF), gpioAFuartx);
172 }
172 }
173
173
174 if(RTSpin!=-1)
174 if(RTSpin!=-1)
175 {
175 {
176 RTS = gpioopen(RTSpin);
176 RTS = gpioopen(RTSpin);
177 RTS |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
177 RTS |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
178 gpiosetconfig(&RTS);
178 gpiosetconfig(&RTS);
179 GPIO_PinAFConfig(GPIOGETPORT(RTS), (uint8_t)(RTS & 0xF), gpioAFuartx);
179 GPIO_PinAFConfig(GPIOGETPORT(RTS), (uint8_t)(RTS & 0xF), gpioAFuartx);
180 }
180 }
181 }
181 }
182 return 1;
182 return 1;
183 }
183 }
184
184
185 int uartsetconfig(uart_t uart, uint32_t cfg, uint32_t speed)
185 int uartsetconfig(uart_t uart, uint32_t cfg, uint32_t speed)
186 {
186 {
187 int res=1;
187 int res=1;
188 uartdisable(uart);
188 uartdisable(uart);
189 uartsetspeed(uart,speed);
189 uartsetspeed(uart,speed);
190 uartsetparity(uart,cfg & UARTPARITYMASK);
190 uartsetparity(uart,cfg & UARTPARITYMASK);
191 uartsetdatabits(uart,cfg & UARTBITSMASK);
191 uartsetdatabits(uart,cfg & UARTBITSMASK);
192 uartsetstopbits(uart,cfg & UARTSTOPBITSMASK);
192 uartsetstopbits(uart,cfg & UARTSTOPBITSMASK);
193 uartenable(uart);
193 uartenable(uart);
194 return res;
194 return res;
195 }
195 }
196
196
197 int uartenable(uart_t uart)
197 int uartenable(uart_t uart)
198 {
198 {
199 if((uart<6)&&(uart>=0))
199 if((uart<6)&&(uart>=0))
200 {
200 {
201 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
201 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
202 _dev_->CR1 |= (1<<13);
202 _dev_->CR1 |= (1<<13);
203 _dev_->CR1 |= (1<<2) + (1<<3);
203 _dev_->CR1 |= (1<<2) + (1<<3);
204 _dev_->DR = ' ';
204 _dev_->DR = ' ';
205 return 1;
205 return 1;
206 }
206 }
207 return -1;
207 return -1;
208 }
208 }
209
209
210 int uartdisable(uart_t uart)
210 int uartdisable(uart_t uart)
211 {
211 {
212 if((uart<6)&&(uart>=0))
212 if((uart<6)&&(uart>=0))
213 {
213 {
214 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
214 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
215 if((_dev_->CR1 & ((1<<3) +(1<<13)))==((1<<3) +(1<<13)))
215 if((_dev_->CR1 & ((1<<3) +(1<<13)))==((1<<3) +(1<<13)))
216 {
216 {
217 while((_dev_->SR & (uint16_t)(1<<7))!=(uint16_t)(1<<7));
217 while((_dev_->SR & (uint16_t)(1<<7))!=(uint16_t)(1<<7));
218 }
218 }
219 _dev_->CR1 &= ~((1<<2) + (1<<3) +(1<<13));
219 _dev_->CR1 &= ~((1<<2) + (1<<3) +(1<<13));
220 return 1;
220 return 1;
221 }
221 }
222 return -1;
222 return -1;
223 }
223 }
224
224
225 int uartsetspeed(uart_t uart,uint32_t speed)
225 int uartsetspeed(uart_t uart,uint32_t speed)
226 {
226 {
227 if((uart<6)&&(uart>=0))
227 if((uart<6)&&(uart>=0))
228 {
228 {
229 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
229 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
230 uint32_t tmpreg = 0x00, apbclock = 0x00;
230 uint32_t tmpreg = 0x00, apbclock = 0x00;
231 uint32_t integerdivider = 0x00;
231 uint32_t integerdivider = 0x00;
232 uint32_t fractionaldivider = 0x00;
232 uint32_t fractionaldivider = 0x00;
233 RCC_ClocksTypeDef RCC_ClocksStatus;
233 RCC_ClocksTypeDef RCC_ClocksStatus;
234 RCC_GetClocksFreq(&RCC_ClocksStatus);
234 RCC_GetClocksFreq(&RCC_ClocksStatus);
235
235
236 if ((_dev_ == USART1) || ((_dev_ == USART6)))
236 if ((_dev_ == USART1) || ((_dev_ == USART6)))
237 {
237 {
238 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
238 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
239 }
239 }
240 else
240 else
241 {
241 {
242 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
242 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
243 }
243 }
244 if (((_dev_->CR1) & USART_CR1_OVER8) != (uint16_t)0)
244 if (((_dev_->CR1) & USART_CR1_OVER8) != (uint16_t)0)
245 {
245 {
246 integerdivider = ((25 * apbclock) / (2 * (speed)));
246 integerdivider = ((25 * apbclock) / (2 * (speed)));
247 }
247 }
248 else
248 else
249 {
249 {
250 integerdivider = ((25 * apbclock) / (4 * (speed)));
250 integerdivider = ((25 * apbclock) / (4 * (speed)));
251 }
251 }
252 tmpreg = (integerdivider / 100) << 4;
252 tmpreg = (integerdivider / 100) << 4;
253 fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
253 fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
254 if ((_dev_->CR1 & USART_CR1_OVER8) != (uint16_t)0)
254 if ((_dev_->CR1 & USART_CR1_OVER8) != (uint16_t)0)
255 {
255 {
256 tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
256 tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
257 }
257 }
258 else
258 else
259 {
259 {
260 tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
260 tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
261 }
261 }
262 _dev_->BRR = (uint16_t)tmpreg;
262 _dev_->BRR = (uint16_t)tmpreg;
263 return 1;
263 return 1;
264 }
264 }
265 return -1;
265 return -1;
266 }
266 }
267
267
268 int uartsetparity(uart_t uart,uartparity_t parity)
268 int uartsetparity(uart_t uart,uartparity_t parity)
269 {
269 {
270 if((uart<6)&&(uart>=0))
270 if((uart<6)&&(uart>=0))
271 {
271 {
272 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
272 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
273 _dev_->CR1 &= ~(((1<<9)+(1<<10)));
273 _dev_->CR1 &= ~(((1<<9)+(1<<10)));
274 switch(parity)
274 switch(parity)
275 {
275 {
276 case uartparityeven:
276 case uartparityeven:
277 _dev_->CR1 |= (1<<10);
277 _dev_->CR1 |= (1<<10);
278 break;
278 break;
279 case uartparityodd:
279 case uartparityodd:
280 _dev_->CR1 |= (1<<10) + (1<<9);
280 _dev_->CR1 |= (1<<10) + (1<<9);
281 break;
281 break;
282 case uartparitynone:
282 case uartparitynone:
283 break;
283 break;
284 default :
284 default :
285 return 0;
285 return 0;
286 break;
286 break;
287 }
287 }
288 return 1;
288 return 1;
289 }
289 }
290 return -1;
290 return -1;
291 }
291 }
292
292
293 int uartsetdatabits(uart_t uart,uartbits_t databits)
293 int uartsetdatabits(uart_t uart,uartbits_t databits)
294 {
294 {
295 if((uart<6)&&(uart>=0))
295 if((uart<6)&&(uart>=0))
296 {
296 {
297 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
297 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
298 _dev_->CR1 &= ~(((1<<12)));
298 _dev_->CR1 &= ~(((1<<12)));
299 switch(databits)
299 switch(databits)
300 {
300 {
301 case uart7bits:
301 case uart7bits:
302 return 0;
302 return 0;
303 break;
303 break;
304 case uart8bits:
304 case uart8bits:
305 break;
305 break;
306 case uart9bits:
306 case uart9bits:
307 _dev_->CR1 |= (1<<12);
307 _dev_->CR1 |= (1<<12);
308 break;
308 break;
309 default :
309 default :
310 return 0;
310 return 0;
311 break;
311 break;
312 }
312 }
313 return 1;
313 return 1;
314 }
314 }
315 return -1;
315 return -1;
316 }
316 }
317
317
318 int uartsetstopbits(uart_t uart,uartstopbits_t stopbits)
318 int uartsetstopbits(uart_t uart,uartstopbits_t stopbits)
319 {
319 {
320 if((uart<6)&&(uart>=0))
320 if((uart<6)&&(uart>=0))
321 {
321 {
322 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
322 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
323 _dev_->CR2 &= ~(((1<<12)+(1<<13)));
323 _dev_->CR2 &= ~(((1<<12)+(1<<13)));
324 switch(stopbits)
324 switch(stopbits)
325 {
325 {
326 case uarthalfstop:
326 case uarthalfstop:
327 _dev_->CR2 |= (1<<12);
327 _dev_->CR2 |= (1<<12);
328 break;
328 break;
329 case uartonestop:
329 case uartonestop:
330 break;
330 break;
331 case uartonehalfstop:
331 case uartonehalfstop:
332 _dev_->CR2 |= (1<<12) + (1<<13);
332 _dev_->CR2 |= (1<<12) + (1<<13);
333 break;
333 break;
334 case uarttwostop:
334 case uarttwostop:
335 _dev_->CR2 |= (1<<13);
335 _dev_->CR2 |= (1<<13);
336 break;
336 break;
337 default :
337 default :
338 return 0;
338 return 0;
339 break;
339 break;
340 }
340 }
341 return 1;
341 return 1;
342 }
342 }
343 return -1;
343 return -1;
344 }
344 }
345
345
346 int uartputc(uart_t uart,char c)
346 int uartputc(uart_t uart,char c)
347 {
347 {
348 if((uart<6)&&(uart>=0))
348 if((uart<6)&&(uart>=0))
349 {
349 {
350 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
350 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
351 while((_dev_->SR & (uint16_t)(1<<7))!=(uint16_t)(1<<7));
351 while((_dev_->SR & (uint16_t)(1<<7))!=(uint16_t)(1<<7));
352 _dev_->DR = c;
352 _dev_->DR = c;
353 return 1;
353 return 1;
354 }
354 }
355 return -1;
355 return -1;
356 }
356 }
357
357
358 char uartgetc(uart_t uart)
358 char uartgetc(uart_t uart)
359 {
359 {
360 if((uart<6)&&(uart>=0))
360 if((uart<6)&&(uart>=0))
361 {
361 {
362 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
362 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
363 while(!(_dev_->SR & (1<<5)));
363 while(!(_dev_->SR & (1<<5)));
364 return (char)_dev_->DR;
364 return (char)_dev_->DR;
365 }
365 }
366 return -1;
366 return -1;
367 }
367 }
368
368
369 int uartputs(uart_t uart,char* s)
369 int uartputs(uart_t uart,char* s)
370 {
370 {
371 while (*s) uartputc(uart,*s++);
371 while (*s) uartputc(uart,*s++);
372 return 1;
372 return 1;
373 }
373 }
374
374
375 int uartgets(uart_t uart,char* s)
375 int uartgets(uart_t uart,char* s)
376 {
376 {
377 do
377 do
378 {
378 {
379 (*s) = uartgetc(uart);
379 (*s) = uartgetc(uart);
380 }
380 }
381 while(*s++);
381 while(*s++);
382 return 1;
382 return 1;
383 }
383 }
384
384
385 int uartputnc(uart_t uart,char* c,int n)
385 int uartputnc(uart_t uart,char* c,int n)
386 {
386 {
387 int l=0;
387 int l=0;
388 while(l<n)
388 while(l<n)
389 {
389 {
390 uartputc(uart,*c++);
390 uartputc(uart,*c++);
391 l++;
391 l++;
392 }
392 }
393 return n;
393 return n;
394 }
394 }
395
395
396 int uartgetnc(uart_t uart,char* c,int n)
396 int uartgetnc(uart_t uart,char* c,int n)
397 {
397 {
398 int l=0;
398 int l=0;
399 while(l<n)
399 while(l<n)
400 {
400 {
401 *c++=uartgetc(uart);
401 *c++=uartgetc(uart);
402 l++;
402 l++;
403 }
403 }
404 return n;
404 return n;
405 }
405 }
406
406
407 int uartavailiabledata(uart_t uart)
407 int uartavailiabledata(uart_t uart)
408 {
408 {
409 if((uart<6)&&(uart>=0))
409 if((uart<6)&&(uart>=0))
410 {
410 {
411 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
411 USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
412 if(!(_dev_->SR & (1<<5)))
412 if(!(_dev_->SR & (1<<5)))
413 return 0;
413 return 0;
414 else
414 else
415 return 1;
415 return 1;
416 }
416 }
417 return -1;
417 return -1;
418 }
418 }
419
419
420
420
421 int _uartstrwrite(streamdevice* device,void* data,int size, int n)
421 int _uartstrwrite(streamdevice* device,void* data,int size, int n)
422 {
422 {
423 return uartputnc((uart_t) device->_stream,(char*) data,size*n);
423 return uartputnc((uart_t) device->_stream,(char*) data,size*n);
424 }
424 }
425
425
426 int _uartstrread(streamdevice* device,void* data,int size, int n)
426 int _uartstrread(streamdevice* device,void* data,int size, int n)
427 {
427 {
428 return uartgetnc((uart_t) device->_stream,(char*) data,size*n);
428 return uartgetnc((uart_t) device->_stream,(char*) data,size*n);
429 }
429 }
430
430
431 int _uartstrsetpos(streamdevice* device,int pos)
431 int _uartstrsetpos(streamdevice* device,int pos)
432 {
432 {
433 return 1;
433 return 1;
434 }
434 }
435
435
436 int uartmkstreamdev(uart_t uart,streamdevice* strdev)
436 int uartmkstreamdev(uart_t uart,streamdevice* strdev)
437 {
437 {
438 strdev->_stream = (UHANDLE)uart;
438 strdev->_stream = (UHANDLE)uart;
439 strdev->write = (write_t)&_uartstrwrite;
439 strdev->write = (write_t)&_uartstrwrite;
440 strdev->read = (read_t)&_uartstrread;
440 strdev->read = (read_t)&_uartstrread;
441 strdev->setpos = (setpos_t)&_uartstrsetpos;
441 strdev->setpos = (setpos_t)&_uartstrsetpos;
442 strdev->streamPt = 0;
442 strdev->streamPt = 0;
443 return 1;
443 return 1;
444 }
444 }
445
445
446
446
447
447
448
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@@ -1,212 +1,215
1 #---------------------------------------------------------------------------------
1 #---------------------------------------------------------------------------------
2 # LIBRARY DEFINITIONS
2 # LIBRARY DEFINITIONS
3 #---------------------------------------------------------------------------------
3 #---------------------------------------------------------------------------------
4 LIBUC_LIBS_DIR = $$libuc2/lib
4 LIBUC_LIBS_DIR = $$libuc2/lib
5
5
6 INCLUDEPATH += $$LIBUC_LIBS_DIR/includes \
6 INCLUDEPATH += $$LIBUC_LIBS_DIR/includes \
7 $$LIBUC_LIBS_DIR/includes/$$ARCH
7 $$LIBUC_LIBS_DIR/includes/$$ARCH
8
8
9 LIBUC_BIN_LIBS_DIR = $$LIBUC_LIBS_DIR/bin/$$ARCH
9 LIBUC_BIN_LIBS_DIR = $$LIBUC_LIBS_DIR/bin/$$ARCH
10
10
11 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
11 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
12 -lCS43L22
13
14 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
12 -lsdcard
15 -lsdcard
13
16
14 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
17 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
15 -lfat32
18 -lfat32
16
19
17 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
20 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
18 -lmbr
21 -lmbr
19
22
20 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
23 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
21 -luart
24 -luart
22
25
23 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
26 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
24 -li2c
27 -li2c
25
28
26 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
29 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
27 -lgpio
30 -lgpio
28
31
29 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
32 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
30 -lspi
33 -lspi
31
34
32 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
35 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
33 -lcpu
36 -lcpu
34
37
35 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
38 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \
36 -lcore
39 -lcore
37
40
38
41
39
42
40
43
41 LIBUC_LIBS_CORE = -L $(LIBUC_LIBS_DIR_CORE) -static -lcore
44 LIBUC_LIBS_CORE = -L $(LIBUC_LIBS_DIR_CORE) -static -lcore
42 LIBUC_LIBS_DIR_CORE = $(LIBUC_LIBS_DIR)
45 LIBUC_LIBS_DIR_CORE = $(LIBUC_LIBS_DIR)
43 LIBUC_LIBS_DIR_CORE_CMD = -L $(LIBUC_LIBS_DIR_CORE)
46 LIBUC_LIBS_DIR_CORE_CMD = -L $(LIBUC_LIBS_DIR_CORE)
44 LIBUC_INC_DIR_CORE = $(LIBUC_INC_DIR)
47 LIBUC_INC_DIR_CORE = $(LIBUC_INC_DIR)
45 LIBUC_INC_DIR_CORE_CMD =
48 LIBUC_INC_DIR_CORE_CMD =
46
49
47 LIBUC_LIBS_CPU = -static -lcpu
50 LIBUC_LIBS_CPU = -static -lcpu
48 LIBUC_LIBS_DIR_CPU = $(LIBUC_LIBS_DIR)
51 LIBUC_LIBS_DIR_CPU = $(LIBUC_LIBS_DIR)
49 LIBUC_LIBS_DIR_CPU_CMD = -L $(LIBUC_LIBS_DIR_CPU)
52 LIBUC_LIBS_DIR_CPU_CMD = -L $(LIBUC_LIBS_DIR_CPU)
50 LIBUC_INC_DIR_CPU = $(LIBUC_INC_DIR)/$(ARCH)
53 LIBUC_INC_DIR_CPU = $(LIBUC_INC_DIR)/$(ARCH)
51 LIBUC_INC_DIR_CPU_CMD = -I $(LIBUC_INC_DIR_CPU)
54 LIBUC_INC_DIR_CPU_CMD = -I $(LIBUC_INC_DIR_CPU)
52
55
53 LIBUC_LIBS_GPIO = -static -lgpio
56 LIBUC_LIBS_GPIO = -static -lgpio
54 LIBUC_LIBS_DIR_GPIO = $(LIBUC_LIBS_DIR)
57 LIBUC_LIBS_DIR_GPIO = $(LIBUC_LIBS_DIR)
55 LIBUC_LIBS_DIR_GPIO_CMD = -L $(LIBUC_LIBS_DIR_GPIO)
58 LIBUC_LIBS_DIR_GPIO_CMD = -L $(LIBUC_LIBS_DIR_GPIO)
56 LIBUC_INC_DIR_GPIO = $(LIBUC_INC_DIR)
59 LIBUC_INC_DIR_GPIO = $(LIBUC_INC_DIR)
57 LIBUC_INC_DIR_GPIO_CMD =
60 LIBUC_INC_DIR_GPIO_CMD =
58
61
59 LIBUC_LIBS_APB = -static -lapb
62 LIBUC_LIBS_APB = -static -lapb
60 LIBUC_LIBS_DIR_APB = $(LIBUC_LIBS_DIR)
63 LIBUC_LIBS_DIR_APB = $(LIBUC_LIBS_DIR)
61 LIBUC_LIBS_DIR_APB_CMD = -L $(LIBUC_LIBS_DIR_APB)
64 LIBUC_LIBS_DIR_APB_CMD = -L $(LIBUC_LIBS_DIR_APB)
62 LIBUC_INC_DIR_APB = $(LIBUC_INC_DIR)
65 LIBUC_INC_DIR_APB = $(LIBUC_INC_DIR)
63 LIBUC_INC_DIR_APB_CMD =
66 LIBUC_INC_DIR_APB_CMD =
64
67
65 LIBUC_LIBS_UCSTRINGS = -static -lucstrings
68 LIBUC_LIBS_UCSTRINGS = -static -lucstrings
66 LIBUC_LIBS_DIR_UCSTRINGS = $(LIBUC_LIBS_DIR)
69 LIBUC_LIBS_DIR_UCSTRINGS = $(LIBUC_LIBS_DIR)
67 LIBUC_LIBS_DIR_UCSTRINGS_CMD = -L $(LIBUC_LIBS_DIR_UCSTRINGS)
70 LIBUC_LIBS_DIR_UCSTRINGS_CMD = -L $(LIBUC_LIBS_DIR_UCSTRINGS)
68 LIBUC_INC_DIR_UCSTRINGS = $(LIBUC_INC_DIR)
71 LIBUC_INC_DIR_UCSTRINGS = $(LIBUC_INC_DIR)
69 LIBUC_INC_DIR_UCSTRINGS_CMD =
72 LIBUC_INC_DIR_UCSTRINGS_CMD =
70
73
71 LIBUC_LIBS_UART = -static -luart
74 LIBUC_LIBS_UART = -static -luart
72 LIBUC_LIBS_DIR_UART = $(LIBUC_LIBS_DIR)
75 LIBUC_LIBS_DIR_UART = $(LIBUC_LIBS_DIR)
73 LIBUC_LIBS_DIR_UART_CMD = -L $(LIBUC_LIBS_DIR_UART)
76 LIBUC_LIBS_DIR_UART_CMD = -L $(LIBUC_LIBS_DIR_UART)
74 LIBUC_INC_DIR_UART = $(LIBUC_INC_DIR)
77 LIBUC_INC_DIR_UART = $(LIBUC_INC_DIR)
75 LIBUC_INC_DIR_UART_CMD =
78 LIBUC_INC_DIR_UART_CMD =
76
79
77 LIBUC_LIBS_SPI = -static -lspi
80 LIBUC_LIBS_SPI = -static -lspi
78 LIBUC_LIBS_DIR_SPI = $(LIBUC_LIBS_DIR)
81 LIBUC_LIBS_DIR_SPI = $(LIBUC_LIBS_DIR)
79 LIBUC_LIBS_DIR_SPI_CMD = -L $(LIBUC_LIBS_DIR_SPI)
82 LIBUC_LIBS_DIR_SPI_CMD = -L $(LIBUC_LIBS_DIR_SPI)
80 LIBUC_INC_DIR_SPI = $(LIBUC_INC_DIR)
83 LIBUC_INC_DIR_SPI = $(LIBUC_INC_DIR)
81 LIBUC_INC_DIR_SPI_CMD =
84 LIBUC_INC_DIR_SPI_CMD =
82
85
83 LIBUC_LIBS_SSP = -static -lssp
86 LIBUC_LIBS_SSP = -static -lssp
84 LIBUC_LIBS_DIR_SSP = $(LIBUC_LIBS_DIR)
87 LIBUC_LIBS_DIR_SSP = $(LIBUC_LIBS_DIR)
85 LIBUC_LIBS_DIR_SSP_CMD = -L $(LIBUC_LIBS_DIR_SSP)
88 LIBUC_LIBS_DIR_SSP_CMD = -L $(LIBUC_LIBS_DIR_SSP)
86 LIBUC_INC_DIR_SSP = $(LIBUC_INC_DIR)
89 LIBUC_INC_DIR_SSP = $(LIBUC_INC_DIR)
87 LIBUC_INC_DIR_SSP_CMD =
90 LIBUC_INC_DIR_SSP_CMD =
88
91
89 LIBUC_LIBS_IIC = -static -liic
92 LIBUC_LIBS_IIC = -static -liic
90 LIBUC_LIBS_DIR_IIC = $(LIBUC_LIBS_DIR)
93 LIBUC_LIBS_DIR_IIC = $(LIBUC_LIBS_DIR)
91 LIBUC_LIBS_DIR_IIC_CMD = -L $(LIBUC_LIBS_DIR_IIC)
94 LIBUC_LIBS_DIR_IIC_CMD = -L $(LIBUC_LIBS_DIR_IIC)
92 LIBUC_INC_DIR_IIC = $(LIBUC_INC_DIR)
95 LIBUC_INC_DIR_IIC = $(LIBUC_INC_DIR)
93 LIBUC_INC_DIR_IIC_CMD =
96 LIBUC_INC_DIR_IIC_CMD =
94
97
95 LIBUC_LIBS_ADC = -static -ladc
98 LIBUC_LIBS_ADC = -static -ladc
96 LIBUC_LIBS_DIR_ADC = $(LIBUC_LIBS_DIR)
99 LIBUC_LIBS_DIR_ADC = $(LIBUC_LIBS_DIR)
97 LIBUC_LIBS_DIR_ADC_CMD = -L $(LIBUC_LIBS_DIR_ADC)
100 LIBUC_LIBS_DIR_ADC_CMD = -L $(LIBUC_LIBS_DIR_ADC)
98 LIBUC_INC_DIR_ADC = $(LIBUC_INC_DIR)
101 LIBUC_INC_DIR_ADC = $(LIBUC_INC_DIR)
99 LIBUC_INC_DIR_ADC_CMD =
102 LIBUC_INC_DIR_ADC_CMD =
100
103
101 LIBUC_LIBS_24LC0X = -static -l24lc0X
104 LIBUC_LIBS_24LC0X = -static -l24lc0X
102 LIBUC_LIBS_DIR_24LC0X = $(LIBUC_LIBS_DIR)
105 LIBUC_LIBS_DIR_24LC0X = $(LIBUC_LIBS_DIR)
103 LIBUC_LIBS_DIR_24LC0X_CMD = -L $(LIBUC_LIBS_DIR_24LC0X)
106 LIBUC_LIBS_DIR_24LC0X_CMD = -L $(LIBUC_LIBS_DIR_24LC0X)
104 LIBUC_INC_DIR_24LC0X = $(LIBUC_INC_DIR)
107 LIBUC_INC_DIR_24LC0X = $(LIBUC_INC_DIR)
105 LIBUC_INC_DIR_24LC0X_CMD =
108 LIBUC_INC_DIR_24LC0X_CMD =
106
109
107 LIBUC_LIBS_SDCARD = -static -lsdcard
110 LIBUC_LIBS_SDCARD = -static -lsdcard
108 LIBUC_LIBS_DIR_SDCARD = $(LIBUC_LIBS_DIR)
111 LIBUC_LIBS_DIR_SDCARD = $(LIBUC_LIBS_DIR)
109 LIBUC_LIBS_DIR_SDCARD_CMD = -L $(LIBUC_LIBS_DIR_SDCARD)
112 LIBUC_LIBS_DIR_SDCARD_CMD = -L $(LIBUC_LIBS_DIR_SDCARD)
110 LIBUC_INC_DIR_SDCARD = $(LIBUC_INC_DIR)
113 LIBUC_INC_DIR_SDCARD = $(LIBUC_INC_DIR)
111 LIBUC_INC_DIR_SDCARD_CMD =
114 LIBUC_INC_DIR_SDCARD_CMD =
112
115
113 LIBUC_LIBS_VS10XX = -static -lvs10XX
116 LIBUC_LIBS_VS10XX = -static -lvs10XX
114 LIBUC_LIBS_DIR_VS10XX = $(LIBUC_LIBS_DIR)
117 LIBUC_LIBS_DIR_VS10XX = $(LIBUC_LIBS_DIR)
115 LIBUC_LIBS_DIR_VS10XX_CMD = -L $(LIBUC_LIBS_DIR_VS10XX)
118 LIBUC_LIBS_DIR_VS10XX_CMD = -L $(LIBUC_LIBS_DIR_VS10XX)
116 LIBUC_INC_DIR_VS10XX = $(LIBUC_INC_DIR)
119 LIBUC_INC_DIR_VS10XX = $(LIBUC_INC_DIR)
117 LIBUC_INC_DIR_VS10XX_CMD =
120 LIBUC_INC_DIR_VS10XX_CMD =
118
121
119 LIBUC_LIBS_BLKDEVICE = -static -lblkdevice
122 LIBUC_LIBS_BLKDEVICE = -static -lblkdevice
120 LIBUC_LIBS_DIR_BLKDEVICE = $(LIBUC_LIBS_DIR)
123 LIBUC_LIBS_DIR_BLKDEVICE = $(LIBUC_LIBS_DIR)
121 LIBUC_LIBS_DIR_BLKDEVICE_CMD = -L $(LIBUC_LIBS_DIR_BLKDEVICE)
124 LIBUC_LIBS_DIR_BLKDEVICE_CMD = -L $(LIBUC_LIBS_DIR_BLKDEVICE)
122 LIBUC_INC_DIR_BLKDEVICE = $(LIBUC_INC_DIR)
125 LIBUC_INC_DIR_BLKDEVICE = $(LIBUC_INC_DIR)
123 LIBUC_INC_DIR_BLKDEVICE_CMD =
126 LIBUC_INC_DIR_BLKDEVICE_CMD =
124
127
125 LIBUC_LIBS_FAT32 = -static -lfat32
128 LIBUC_LIBS_FAT32 = -static -lfat32
126 LIBUC_LIBS_DIR_FAT32 = $(LIBUC_LIBS_DIR)
129 LIBUC_LIBS_DIR_FAT32 = $(LIBUC_LIBS_DIR)
127 LIBUC_LIBS_DIR_FAT32_CMD = -L $(LIBUC_LIBS_DIR_FAT32)
130 LIBUC_LIBS_DIR_FAT32_CMD = -L $(LIBUC_LIBS_DIR_FAT32)
128 LIBUC_INC_DIR_FAT32 = $(LIBUC_INC_DIR)
131 LIBUC_INC_DIR_FAT32 = $(LIBUC_INC_DIR)
129 LIBUC_INC_DIR_FAT32_CMD =
132 LIBUC_INC_DIR_FAT32_CMD =
130
133
131 LIBUC_LIBS_UHANDLE = -static -luhandle
134 LIBUC_LIBS_UHANDLE = -static -luhandle
132 LIBUC_LIBS_DIR_UHANDLE = $(LIBUC_LIBS_DIR)
135 LIBUC_LIBS_DIR_UHANDLE = $(LIBUC_LIBS_DIR)
133 LIBUC_LIBS_DIR_UHANDLE_CMD = -L $(LIBUC_LIBS_DIR_UHANDLE)
136 LIBUC_LIBS_DIR_UHANDLE_CMD = -L $(LIBUC_LIBS_DIR_UHANDLE)
134 LIBUC_INC_DIR_UHANDLE = $(LIBUC_INC_DIR)
137 LIBUC_INC_DIR_UHANDLE = $(LIBUC_INC_DIR)
135 LIBUC_INC_DIR_UHANDLE_CMD =
138 LIBUC_INC_DIR_UHANDLE_CMD =
136
139
137 LIBUC_LIBS_STREAMDEVICES = -static -lstreamdevices
140 LIBUC_LIBS_STREAMDEVICES = -static -lstreamdevices
138 LIBUC_LIBS_DIR_STREAMDEVICES = $(LIBUC_LIBS_DIR)
141 LIBUC_LIBS_DIR_STREAMDEVICES = $(LIBUC_LIBS_DIR)
139 LIBUC_LIBS_DIR_STREAMDEVICES_CMD = -L $(LIBUC_LIBS_DIR_STREAMDEVICES)
142 LIBUC_LIBS_DIR_STREAMDEVICES_CMD = -L $(LIBUC_LIBS_DIR_STREAMDEVICES)
140 LIBUC_INC_DIR_STREAMDEVICES = $(LIBUC_INC_DIR)
143 LIBUC_INC_DIR_STREAMDEVICES = $(LIBUC_INC_DIR)
141 LIBUC_INC_DIR_STREAMDEVICES_CMD =
144 LIBUC_INC_DIR_STREAMDEVICES_CMD =
142
145
143 LIBUC_LIBS_HEXVIEWER = -static -lhexviewer
146 LIBUC_LIBS_HEXVIEWER = -static -lhexviewer
144 LIBUC_LIBS_DIR_HEXVIEWER = $(LIBUC_LIBS_DIR)
147 LIBUC_LIBS_DIR_HEXVIEWER = $(LIBUC_LIBS_DIR)
145 LIBUC_LIBS_DIR_HEXVIEWER_CMD = -L $(LIBUC_LIBS_DIR_HEXVIEWER)
148 LIBUC_LIBS_DIR_HEXVIEWER_CMD = -L $(LIBUC_LIBS_DIR_HEXVIEWER)
146 LIBUC_INC_DIR_HEXVIEWER = $(LIBUC_INC_DIR)
149 LIBUC_INC_DIR_HEXVIEWER = $(LIBUC_INC_DIR)
147 LIBUC_INC_DIR_HEXVIEWER_CMD =
150 LIBUC_INC_DIR_HEXVIEWER_CMD =
148
151
149 LIBUC_LIBS_MBR = -static -lmbr
152 LIBUC_LIBS_MBR = -static -lmbr
150 LIBUC_LIBS_DIR_MBR = $(LIBUC_LIBS_DIR)
153 LIBUC_LIBS_DIR_MBR = $(LIBUC_LIBS_DIR)
151 LIBUC_LIBS_DIR_MBR_CMD = -L $(LIBUC_LIBS_DIR_MBR)
154 LIBUC_LIBS_DIR_MBR_CMD = -L $(LIBUC_LIBS_DIR_MBR)
152 LIBUC_INC_DIR_MBR = $(LIBUC_INC_DIR)
155 LIBUC_INC_DIR_MBR = $(LIBUC_INC_DIR)
153 LIBUC_INC_DIR_MBR_CMD =
156 LIBUC_INC_DIR_MBR_CMD =
154
157
155 LIBUC_LIBS_UCDIRENT = -static -lucdirent
158 LIBUC_LIBS_UCDIRENT = -static -lucdirent
156 LIBUC_LIBS_DIR_UCDIRENT = $(LIBUC_LIBS_DIR)
159 LIBUC_LIBS_DIR_UCDIRENT = $(LIBUC_LIBS_DIR)
157 LIBUC_LIBS_DIR_UCDIRENT_CMD = -L $(LIBUC_LIBS_DIR_UCDIRENT)
160 LIBUC_LIBS_DIR_UCDIRENT_CMD = -L $(LIBUC_LIBS_DIR_UCDIRENT)
158 LIBUC_INC_DIR_UCDIRENT = $(LIBUC_INC_DIR)
161 LIBUC_INC_DIR_UCDIRENT = $(LIBUC_INC_DIR)
159 LIBUC_INC_DIR_UCDIRENT_CMD =
162 LIBUC_INC_DIR_UCDIRENT_CMD =
160
163
161 LIBUC_LIBS_FS = -static -lfs
164 LIBUC_LIBS_FS = -static -lfs
162 LIBUC_LIBS_DIR_FS = $(LIBUC_LIBS_DIR)
165 LIBUC_LIBS_DIR_FS = $(LIBUC_LIBS_DIR)
163 LIBUC_LIBS_DIR_FS_CMD = -L $(LIBUC_LIBS_DIR_FS)
166 LIBUC_LIBS_DIR_FS_CMD = -L $(LIBUC_LIBS_DIR_FS)
164 LIBUC_INC_DIR_FS = $(LIBUC_INC_DIR)
167 LIBUC_INC_DIR_FS = $(LIBUC_INC_DIR)
165 LIBUC_INC_DIR_FS_CMD =
168 LIBUC_INC_DIR_FS_CMD =
166
169
167 LIBUC_LIBS_FSEXPLORER = -static -lfsexplorer
170 LIBUC_LIBS_FSEXPLORER = -static -lfsexplorer
168 LIBUC_LIBS_DIR_FSEXPLORER = $(LIBUC_LIBS_DIR)
171 LIBUC_LIBS_DIR_FSEXPLORER = $(LIBUC_LIBS_DIR)
169 LIBUC_LIBS_DIR_FSEXPLORER_CMD = -L $(LIBUC_LIBS_DIR_FSEXPLORER)
172 LIBUC_LIBS_DIR_FSEXPLORER_CMD = -L $(LIBUC_LIBS_DIR_FSEXPLORER)
170 LIBUC_INC_DIR_FSEXPLORER = $(LIBUC_INC_DIR)
173 LIBUC_INC_DIR_FSEXPLORER = $(LIBUC_INC_DIR)
171 LIBUC_INC_DIR_FSEXPLORER_CMD =
174 LIBUC_INC_DIR_FSEXPLORER_CMD =
172
175
173 LIBUC_LIBS_DIR_ALLFS_CMD = $(LIBUC_LIBS_DIR_UCDIRENT_CMD) $(LIBUC_LIBS_DIR_FS_CMD) $(LIBUC_LIBS_DIR_MBR_CMD) $(LIBUC_LIBS_DIR_FAT32_CMD) $(LIBUC_LIBS_DIR_SDCARD_CMD) $(LIBUC_LIBS_DIR_BLKDEVICE_CMD)
176 LIBUC_LIBS_DIR_ALLFS_CMD = $(LIBUC_LIBS_DIR_UCDIRENT_CMD) $(LIBUC_LIBS_DIR_FS_CMD) $(LIBUC_LIBS_DIR_MBR_CMD) $(LIBUC_LIBS_DIR_FAT32_CMD) $(LIBUC_LIBS_DIR_SDCARD_CMD) $(LIBUC_LIBS_DIR_BLKDEVICE_CMD)
174 LIBUC_INC_DIR_ALLFS_CMD = $(LIBUC_INC_DIR_UCDIRENT_CMD) $(LIBUC_INC_DIR_FS_CMD) $(LIBUC_INC_DIR_MBR_CMD) $(LIBUC_INC_DIR_FAT32_CMD) $(LIBUC_INC_DIR_SDCARD_CMD) $(LIBUC_INC_DIR_BLKDEVICE_CMD)
177 LIBUC_INC_DIR_ALLFS_CMD = $(LIBUC_INC_DIR_UCDIRENT_CMD) $(LIBUC_INC_DIR_FS_CMD) $(LIBUC_INC_DIR_MBR_CMD) $(LIBUC_INC_DIR_FAT32_CMD) $(LIBUC_INC_DIR_SDCARD_CMD) $(LIBUC_INC_DIR_BLKDEVICE_CMD)
175 LIBUC_LIBS_ALLFS = $(LIBUC_LIBS_UCDIRENT) $(LIBUC_LIBS_FS) $(LIBUC_LIBS_MBR) $(LIBUC_LIBS_FAT32) $(LIBUC_LIBS_SDCARD) $(LIBUC_LIBS_BLKDEVICE)
178 LIBUC_LIBS_ALLFS = $(LIBUC_LIBS_UCDIRENT) $(LIBUC_LIBS_FS) $(LIBUC_LIBS_MBR) $(LIBUC_LIBS_FAT32) $(LIBUC_LIBS_SDCARD) $(LIBUC_LIBS_BLKDEVICE)
176
179
177
180
178 LIBUC_LIBS_ADS127X = -static -lads127X
181 LIBUC_LIBS_ADS127X = -static -lads127X
179 LIBUC_LIBS_DIR_ADS127X = $(LIBUC_LIBS_DIR)
182 LIBUC_LIBS_DIR_ADS127X = $(LIBUC_LIBS_DIR)
180 LIBUC_LIBS_DIR_ADS127X_CMD = -L $(LIBUC_LIBS_DIR_ADS127X)
183 LIBUC_LIBS_DIR_ADS127X_CMD = -L $(LIBUC_LIBS_DIR_ADS127X)
181 LIBUC_INC_DIR_ADS127X = $(LIBUC_INC_DIR)
184 LIBUC_INC_DIR_ADS127X = $(LIBUC_INC_DIR)
182 LIBUC_INC_DIR_ADS127X_CMD =
185 LIBUC_INC_DIR_ADS127X_CMD =
183
186
184
187
185 LIBUC_LIBS_NXPLIB = -static -lnxplib
188 LIBUC_LIBS_NXPLIB = -static -lnxplib
186 LIBUC_LIBS_DIR_NXPLIB = $(LIBUC_LIBS_DIR)
189 LIBUC_LIBS_DIR_NXPLIB = $(LIBUC_LIBS_DIR)
187 LIBUC_LIBS_DIR_NXPLIB_CMD = -L $(LIBUC_LIBS_DIR_NXPLIB)
190 LIBUC_LIBS_DIR_NXPLIB_CMD = -L $(LIBUC_LIBS_DIR_NXPLIB)
188 LIBUC_INC_DIR_NXPLIB = $(LIBUC_INC_DIR)/LPCXXXX
191 LIBUC_INC_DIR_NXPLIB = $(LIBUC_INC_DIR)/LPCXXXX
189 LIBUC_INC_DIR_NXPLIB_CMD = -I $(LIBUC_INC_DIR_NXPLIB)
192 LIBUC_INC_DIR_NXPLIB_CMD = -I $(LIBUC_INC_DIR_NXPLIB)
190
193
191 LIBUC_LIBS_ARMMATH = -static -larmmath
194 LIBUC_LIBS_ARMMATH = -static -larmmath
192 LIBUC_LIBS_DIR_ARMMATH = $(LIBUC_LIBS_DIR)
195 LIBUC_LIBS_DIR_ARMMATH = $(LIBUC_LIBS_DIR)
193 LIBUC_LIBS_DIR_ARMMATH_CMD = -L $(LIBUC_LIBS_DIR_ARMMATH)
196 LIBUC_LIBS_DIR_ARMMATH_CMD = -L $(LIBUC_LIBS_DIR_ARMMATH)
194 LIBUC_INC_DIR_ARMMATH = $(LIBUC_INC_DIR)/ARM
197 LIBUC_INC_DIR_ARMMATH = $(LIBUC_INC_DIR)/ARM
195 LIBUC_INC_DIR_ARMMATH_CMD = $(LIBUC_INC_DIR_ARMMATH)
198 LIBUC_INC_DIR_ARMMATH_CMD = $(LIBUC_INC_DIR_ARMMATH)
196
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