@@ -5,12 +5,17 | |||||
5 | #include <stm32f4xx.h> |
|
5 | #include <stm32f4xx.h> | |
6 | #include <bsp.h> |
|
6 | #include <bsp.h> | |
7 | #include <i2c.h> |
|
7 | #include <i2c.h> | |
|
8 | #include <CS43L22.h> | |||
8 |
|
9 | |||
9 |
|
10 | |||
10 | extern streamdevice* __opnfiles__[]; |
|
11 | extern streamdevice* __opnfiles__[]; | |
11 |
|
12 | |||
12 | int main() |
|
13 | int main() | |
13 | { |
|
14 | { | |
|
15 | CS43L22_t audioDac1; | |||
|
16 | cs43l22open(&audioDac1,i2c1,0); | |||
|
17 | char id=cs43l22getID(&audioDac1); | |||
|
18 | printf("DAC ID=%c\n\r",0x0ff&id); | |||
14 | while(1) |
|
19 | while(1) | |
15 | { |
|
20 | { | |
16 | for(volatile int i=0;i<1024*2048;i++); |
|
21 | for(volatile int i=0;i<1024*2048;i++); |
@@ -31,10 +31,10 typedef struct CS43L22_t | |||||
31 | uint8_t devAddress; |
|
31 | uint8_t devAddress; | |
32 | }CS43L22_t; |
|
32 | }CS43L22_t; | |
33 |
|
33 | |||
34 |
extern int cs43l22open(CS43L22_t* dev,uint8_t |
|
34 | extern int cs43l22open(CS43L22_t* dev,i2c_t i2cdev,uint8_t A0); | |
|
35 | extern uint8_t cs43l22getID(CS43L22_t* dev); | |||
35 |
|
36 | |||
36 |
|
37 | #define CS43L22_I2C_ADDRESS 0x4a | ||
37 |
|
||||
38 |
|
38 | |||
39 |
|
39 | |||
40 | #define CS43L22_MAP_ID 1 |
|
40 | #define CS43L22_MAP_ID 1 | |
@@ -50,8 +50,8 extern int cs43l22open(CS43L22_t* dev,ui | |||||
50 | #define CS43L22_MAP_Playback_Ctl_1 0xD |
|
50 | #define CS43L22_MAP_Playback_Ctl_1 0xD | |
51 | #define CS43L22_MAP_Misc_Ctl 0xE |
|
51 | #define CS43L22_MAP_Misc_Ctl 0xE | |
52 | #define CS43L22_MAP_Playback_Ctl_2 0xF |
|
52 | #define CS43L22_MAP_Playback_Ctl_2 0xF | |
53 |
#define CS43L22_MAP_Passthrough_A |
|
53 | #define CS43L22_MAP_Passthrough_A_Vol 0x14 | |
54 |
#define CS43L22_MAP_Passthrough_B |
|
54 | #define CS43L22_MAP_Passthrough_B_Vol 0x15 | |
55 | #define CS43L22_MAP_PCMA_Vol 0x1A |
|
55 | #define CS43L22_MAP_PCMA_Vol 0x1A | |
56 | #define CS43L22_MAP_PCMB_Vol 0x1B |
|
56 | #define CS43L22_MAP_PCMB_Vol 0x1B | |
57 | #define CS43L22_MAP_BEEP_Freq 0x1C |
|
57 | #define CS43L22_MAP_BEEP_Freq 0x1C | |
@@ -68,7 +68,7 extern int cs43l22open(CS43L22_t* dev,ui | |||||
68 | #define CS43L22_MAP_Limit_Ctl_1 0x27 |
|
68 | #define CS43L22_MAP_Limit_Ctl_1 0x27 | |
69 | #define CS43L22_MAP_Limit Ctl_2 0x28 |
|
69 | #define CS43L22_MAP_Limit Ctl_2 0x28 | |
70 | #define CS43L22_MAP_Limiter_Attack 0x29 |
|
70 | #define CS43L22_MAP_Limiter_Attack 0x29 | |
71 |
#define CS43L22_MAP_Overflow_ |
|
71 | #define CS43L22_MAP_Overflow_And_Clock_Status 0x2E | |
72 | #define CS43L22_MAP_Battery_Compensation 0x2F |
|
72 | #define CS43L22_MAP_Battery_Compensation 0x2F | |
73 | #define CS43L22_MAP_VP_Battery_Level 0x30 |
|
73 | #define CS43L22_MAP_VP_Battery_Level 0x30 | |
74 | #define CS43L22_MAP_Speaker_Status 0x31 |
|
74 | #define CS43L22_MAP_Speaker_Status 0x31 |
@@ -19,6 +19,33 | |||||
19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
20 | -- Mail : alexis.jeandet@gmail.com |
|
20 | -- Mail : alexis.jeandet@gmail.com | |
21 | -------------------------------------------------------------------------------*/ |
|
21 | -------------------------------------------------------------------------------*/ | |
|
22 | #include <CS43L22.h> | |||
|
23 | #include <stdio.h> | |||
|
24 | #include <stddef.h> | |||
|
25 | #include <spi.h> | |||
|
26 | ||||
|
27 | int cs43l22open(CS43L22_t* dev,i2c_t i2cdev, uint8_t A0) | |||
|
28 | { | |||
|
29 | if(dev != NULL) | |||
|
30 | { | |||
|
31 | dev->i2cdev=i2cdev; | |||
|
32 | dev->devAddress = CS43L22_I2C_ADDRESS | (A0 & 1); | |||
|
33 | return 1; | |||
|
34 | } | |||
|
35 | return -1; | |||
|
36 | } | |||
|
37 | ||||
|
38 | uint8_t cs43l22getID(CS43L22_t* dev) | |||
|
39 | { | |||
|
40 | if(dev != NULL) | |||
|
41 | { | |||
|
42 | char DATA[]={CS43L22_MAP_ID}; | |||
|
43 | i2cwrite(dev->i2cdev,dev->devAddress,DATA,1); | |||
|
44 | i2cread(dev->i2cdev,dev->devAddress,DATA,1); | |||
|
45 | return DATA[0]; | |||
|
46 | } | |||
|
47 | return -1; | |||
|
48 | } | |||
22 |
|
49 | |||
23 |
|
50 | |||
24 |
|
51 | |||
@@ -27,5 +54,3 | |||||
27 |
|
54 | |||
28 |
|
55 | |||
29 |
|
56 | |||
30 |
|
||||
31 |
|
@@ -43,17 +43,17 i2c_t i2copen(int count) | |||||
43 |
|
43 | |||
44 | switch(count) |
|
44 | switch(count) | |
45 | { |
|
45 | { | |
46 |
case |
|
46 | case i2c1: | |
47 | _INIT_DEV(RCC_APB1Periph_I2C1); |
|
47 | _INIT_DEV(RCC_APB1Periph_I2C1); | |
48 |
return |
|
48 | return i2c1; | |
49 | break; |
|
49 | break; | |
50 |
case |
|
50 | case i2c2: | |
51 | _INIT_DEV(RCC_APB1Periph_I2C2); |
|
51 | _INIT_DEV(RCC_APB1Periph_I2C2); | |
52 |
return |
|
52 | return i2c2; | |
53 | break; |
|
53 | break; | |
54 | case 2: |
|
54 | case i2c3: | |
55 | _INIT_DEV(RCC_APB1Periph_I2C3); |
|
55 | _INIT_DEV(RCC_APB1Periph_I2C3); | |
56 |
return |
|
56 | return i2c3; | |
57 | break; |
|
57 | break; | |
58 | default: |
|
58 | default: | |
59 | break; |
|
59 | break; | |
@@ -79,15 +79,15 i2c_t i2copenandconfig(int count,uint32_ | |||||
79 |
|
79 | |||
80 | int i2cclose(i2c_t dev) |
|
80 | int i2cclose(i2c_t dev) | |
81 | { |
|
81 | { | |
82 |
switch( |
|
82 | switch(dev) | |
83 | { |
|
83 | { | |
84 |
case |
|
84 | case i2c1: | |
85 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); |
|
85 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); | |
86 | break; |
|
86 | break; | |
87 |
case |
|
87 | case i2c2: | |
88 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); |
|
88 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); | |
89 | break; |
|
89 | break; | |
90 |
case |
|
90 | case i2c3: | |
91 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, ENABLE); |
|
91 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, ENABLE); | |
92 | break; |
|
92 | break; | |
93 | default: |
|
93 | default: | |
@@ -104,19 +104,31 int i2csetpins(i2c_t dev, uint32_t SDA, | |||||
104 | SDApin = gpioopen(SDA); |
|
104 | SDApin = gpioopen(SDA); | |
105 | SCLpin = gpioopen(SCL); |
|
105 | SCLpin = gpioopen(SCL); | |
106 | SDApin |= gpiolowspeed | gpioaf | gpioopendraintype | gpionopulltype; |
|
106 | SDApin |= gpiolowspeed | gpioaf | gpioopendraintype | gpionopulltype; | |
|
107 | SCLpin |= gpiolowspeed | gpiooutdir | gpioopendraintype | gpionopulltype; | |||
|
108 | gpiosetconfig(&SCLpin); | |||
|
109 | for(int i=0;i<32;i++) | |||
|
110 | { | |||
|
111 | gpioclr(SCLpin); | |||
|
112 | for(int l=0;l<200;l++) | |||
|
113 | {__asm__("nop");} | |||
|
114 | gpioset(SCLpin); | |||
|
115 | for(int l=0;l<200;l++) | |||
|
116 | {__asm__("nop");} | |||
|
117 | } | |||
|
118 | SCLpin = gpioopen(SCL); | |||
107 | SCLpin |= gpiolowspeed | gpioaf | gpioopendraintype | gpionopulltype; |
|
119 | SCLpin |= gpiolowspeed | gpioaf | gpioopendraintype | gpionopulltype; | |
108 | gpiosetconfig(&SDApin); |
|
120 | gpiosetconfig(&SDApin); | |
109 | gpiosetconfig(&SCLpin); |
|
121 | gpiosetconfig(&SCLpin); | |
110 | uint8_t gpioAFi2cx = GPIO_AF_I2C1; |
|
122 | uint8_t gpioAFi2cx = GPIO_AF_I2C1; | |
111 |
switch( |
|
123 | switch(dev) | |
112 | { |
|
124 | { | |
113 |
case |
|
125 | case i2c1: | |
114 | gpioAFi2cx = GPIO_AF_I2C1; |
|
126 | gpioAFi2cx = GPIO_AF_I2C1; | |
115 | break; |
|
127 | break; | |
116 |
case |
|
128 | case i2c2: | |
117 | gpioAFi2cx = GPIO_AF_I2C2; |
|
129 | gpioAFi2cx = GPIO_AF_I2C2; | |
118 | break; |
|
130 | break; | |
119 | case 2: |
|
131 | case i2c3: | |
120 | gpioAFi2cx = GPIO_AF_I2C3; |
|
132 | gpioAFi2cx = GPIO_AF_I2C3; | |
121 | break; |
|
133 | break; | |
122 | default: |
|
134 | default: | |
@@ -238,23 +250,25 int i2cread(i2c_t dev,char address,char* | |||||
238 | while(i2cbusy(dev)); |
|
250 | while(i2cbusy(dev)); | |
239 | I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev]; |
|
251 | I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev]; | |
240 | _dev_->CR1 |= (1<<8) | (1<<10); |
|
252 | _dev_->CR1 |= (1<<8) | (1<<10); | |
|
253 | while(!i2cStatusCheck(dev,0x00030001)); | |||
|
254 | _dev_->DR= (address<<1) + 1; | |||
|
255 | while(!i2cStatusCheck(dev, ((uint32_t)0x00070082))); | |||
241 | if(count==1) |
|
256 | if(count==1) | |
242 | { |
|
257 | { | |
243 | _dev_->CR1 &= ~(1<<10); |
|
258 | _dev_->CR1 &= ~(1<<10); | |
244 | } |
|
259 | } | |
245 | while(!i2cStatusCheck(dev,0x00030001)); |
|
|||
246 | _dev_->DR= (address<<1) + 1; |
|
|||
247 | while(!i2cStatusCheck(dev, ((uint32_t)0x00070082))); |
|
|||
248 | address=_dev_->SR2; |
|
260 | address=_dev_->SR2; | |
249 | for(int i=0;i<count-1;i++) |
|
261 | for(int i=0;i<(count-1);i++) | |
250 | { |
|
262 | { | |
251 | while((_dev_->SR1 & (1<<6))==0); |
|
263 | while((_dev_->SR1 & (1<<6))==0); | |
252 | data[i]=_dev_->DR; |
|
264 | data[i]=_dev_->DR; | |
253 | } |
|
265 | } | |
254 | _dev_->CR1 &= ~(1<<10); |
|
266 | _dev_->CR1 &= ~(1<<10); | |
255 | _dev_->CR1 |= 1<<9; |
|
267 | _dev_->CR1 |= 1<<9; | |
256 | while((_dev_->SR1 & (1<<6))==0); |
|
268 | while(!i2cStatusCheck(dev, ((uint32_t)0x10000040))); | |
257 | data[count-1]=_dev_->DR; |
|
269 | data[count-1]=_dev_->DR; | |
|
270 | while(_dev_->CR1 & ((uint16_t)0x0200)); | |||
|
271 | _dev_->CR1 |= 1<<10; | |||
258 | return count; |
|
272 | return count; | |
259 | } |
|
273 | } | |
260 | return -1; |
|
274 | return -1; | |
@@ -264,10 +278,6 int i2cread(i2c_t dev,char address,char* | |||||
264 | int i2cStatusCheck(i2c_t dev,int32_t flagMask) |
|
278 | int i2cStatusCheck(i2c_t dev,int32_t flagMask) | |
265 | { |
|
279 | { | |
266 | int32_t flag; |
|
280 | int32_t flag; | |
267 | __asm__("nop"); |
|
|||
268 | __asm__("nop"); |
|
|||
269 | __asm__("nop"); |
|
|||
270 | __asm__("nop"); |
|
|||
271 | if((dev<3)&&(dev>=0)) |
|
281 | if((dev<3)&&(dev>=0)) | |
272 | { |
|
282 | { | |
273 | I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev]; |
|
283 | I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev]; |
@@ -40,20 +40,20 spi_t spiopen(int count) | |||||
40 |
|
40 | |||
41 | switch(count) |
|
41 | switch(count) | |
42 | { |
|
42 | { | |
43 |
case |
|
43 | case spi1: | |
44 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); |
|
44 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); | |
45 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); |
|
45 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); | |
46 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); |
|
46 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); | |
47 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); |
|
47 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); | |
48 |
return |
|
48 | return spi1; | |
49 | break; |
|
49 | break; | |
50 |
case |
|
50 | case spi2: | |
51 | _INIT_DEV(RCC_APB1Periph_SPI2); |
|
51 | _INIT_DEV(RCC_APB1Periph_SPI2); | |
52 |
return |
|
52 | return spi2; | |
53 | break; |
|
53 | break; | |
54 |
case |
|
54 | case spi3: | |
55 | _INIT_DEV(RCC_APB1Periph_SPI3); |
|
55 | _INIT_DEV(RCC_APB1Periph_SPI3); | |
56 |
return |
|
56 | return spi3; | |
57 | break; |
|
57 | break; | |
58 | default: |
|
58 | default: | |
59 | break; |
|
59 | break; | |
@@ -81,13 +81,13 int spiclose(spi_t spidev) | |||||
81 | { |
|
81 | { | |
82 | switch(spidev) |
|
82 | switch(spidev) | |
83 | { |
|
83 | { | |
84 |
case |
|
84 | case spi1: | |
85 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); |
|
85 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); | |
86 | break; |
|
86 | break; | |
87 |
case |
|
87 | case spi2: | |
88 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); |
|
88 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); | |
89 | break; |
|
89 | break; | |
90 |
case |
|
90 | case spi3: | |
91 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); |
|
91 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); | |
92 | break; |
|
92 | break; | |
93 | default: |
|
93 | default: | |
@@ -108,13 +108,13 int spisetpins(spi_t spidev,uint32_t MOS | |||||
108 | uint8_t gpioAFspix = GPIO_AF_SPI1; |
|
108 | uint8_t gpioAFspix = GPIO_AF_SPI1; | |
109 | switch(spidev) |
|
109 | switch(spidev) | |
110 | { |
|
110 | { | |
111 |
case |
|
111 | case spi1: | |
112 | gpioAFspix = GPIO_AF_SPI1; |
|
112 | gpioAFspix = GPIO_AF_SPI1; | |
113 | break; |
|
113 | break; | |
114 |
case |
|
114 | case spi2: | |
115 | gpioAFspix = GPIO_AF_SPI2; |
|
115 | gpioAFspix = GPIO_AF_SPI2; | |
116 | break; |
|
116 | break; | |
117 |
case |
|
117 | case spi3: | |
118 | gpioAFspix = GPIO_AF_SPI3; |
|
118 | gpioAFspix = GPIO_AF_SPI3; | |
119 | break; |
|
119 | break; | |
120 | default: |
|
120 | default: |
@@ -36,48 +36,48 uart_t uartopen(int count) | |||||
36 |
|
36 | |||
37 | switch(count) |
|
37 | switch(count) | |
38 | { |
|
38 | { | |
39 |
case |
|
39 | case uart1: | |
40 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); |
|
40 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); | |
41 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); |
|
41 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); | |
42 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); |
|
42 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); | |
43 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); |
|
43 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); | |
44 | USART1->CR3 &= ~((1<<8) + (1<<9)); |
|
44 | USART1->CR3 &= ~((1<<8) + (1<<9)); | |
45 |
return |
|
45 | return uart1; | |
46 | break; |
|
46 | break; | |
47 |
case |
|
47 | case uart2: | |
48 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); |
|
48 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); | |
49 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); |
|
49 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); | |
50 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); |
|
50 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); | |
51 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); |
|
51 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); | |
52 | USART2->CR3 &= ~((1<<8) + (1<<9)); |
|
52 | USART2->CR3 &= ~((1<<8) + (1<<9)); | |
53 |
return |
|
53 | return uart2; | |
54 | break; |
|
54 | break; | |
55 |
case |
|
55 | case uart3: | |
56 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); |
|
56 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); | |
57 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); |
|
57 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); | |
58 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); |
|
58 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); | |
59 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); |
|
59 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); | |
60 | USART3->CR3 &= ~((1<<8) + (1<<9)); |
|
60 | USART3->CR3 &= ~((1<<8) + (1<<9)); | |
61 |
return |
|
61 | return uart3; | |
62 | break; |
|
62 | break; | |
63 |
case |
|
63 | case uart4: | |
64 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); |
|
64 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); | |
65 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); |
|
65 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); | |
66 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE); |
|
66 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE); | |
67 | UART4->CR3 &= ~((1<<8) + (1<<9)); |
|
67 | UART4->CR3 &= ~((1<<8) + (1<<9)); | |
68 |
return |
|
68 | return uart4; | |
69 | break; |
|
69 | break; | |
70 |
case |
|
70 | case uart5: | |
71 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); |
|
71 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); | |
72 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); |
|
72 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); | |
73 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE); |
|
73 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE); | |
74 |
return |
|
74 | return uart5; | |
75 | break; |
|
75 | break; | |
76 |
case |
|
76 | case uart6: | |
77 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); |
|
77 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); | |
78 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); |
|
78 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); | |
79 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); |
|
79 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); | |
80 |
return |
|
80 | return uart6; | |
81 | break; |
|
81 | break; | |
82 | default: |
|
82 | default: | |
83 | break; |
|
83 | break; | |
@@ -90,7 +90,7 uart_t uartopenandconfig(int count, uint | |||||
90 | uart_t dev= uartopen(count); |
|
90 | uart_t dev= uartopen(count); | |
91 | uartsetconfig(dev,cfg,speed); |
|
91 | uartsetconfig(dev,cfg,speed); | |
92 | uartsetpins(dev,TXpin,RXpin,RTSpin,CTSpin); |
|
92 | uartsetpins(dev,TXpin,RXpin,RTSpin,CTSpin); | |
93 |
return |
|
93 | return dev; | |
94 | } |
|
94 | } | |
95 |
|
95 | |||
96 |
|
96 | |||
@@ -98,22 +98,22 int uartclose(uart_t uart) | |||||
98 | { |
|
98 | { | |
99 | switch(uart) |
|
99 | switch(uart) | |
100 | { |
|
100 | { | |
101 |
case |
|
101 | case uart1: | |
102 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); |
|
102 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); | |
103 | break; |
|
103 | break; | |
104 |
case |
|
104 | case uart2: | |
105 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); |
|
105 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); | |
106 | break; |
|
106 | break; | |
107 |
case |
|
107 | case uart3: | |
108 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); |
|
108 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); | |
109 | break; |
|
109 | break; | |
110 |
case |
|
110 | case uart4: | |
111 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); |
|
111 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); | |
112 | break; |
|
112 | break; | |
113 |
case |
|
113 | case uart5: | |
114 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); |
|
114 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); | |
115 | break; |
|
115 | break; | |
116 |
case |
|
116 | case uart6: | |
117 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); |
|
117 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); | |
118 | break; |
|
118 | break; | |
119 | default: |
|
119 | default: | |
@@ -137,22 +137,22 int uartsetpins(uart_t uart,uint32_t TXp | |||||
137 | uint8_t gpioAFuartx = GPIO_AF_USART1; |
|
137 | uint8_t gpioAFuartx = GPIO_AF_USART1; | |
138 | switch(uart) |
|
138 | switch(uart) | |
139 | { |
|
139 | { | |
140 |
case |
|
140 | case uart1: | |
141 | gpioAFuartx = GPIO_AF_USART1; |
|
141 | gpioAFuartx = GPIO_AF_USART1; | |
142 | break; |
|
142 | break; | |
143 |
case |
|
143 | case uart2: | |
144 | gpioAFuartx = GPIO_AF_USART2; |
|
144 | gpioAFuartx = GPIO_AF_USART2; | |
145 | break; |
|
145 | break; | |
146 |
case |
|
146 | case uart3: | |
147 | gpioAFuartx = GPIO_AF_USART3; |
|
147 | gpioAFuartx = GPIO_AF_USART3; | |
148 | break; |
|
148 | break; | |
149 |
case |
|
149 | case uart4: | |
150 | gpioAFuartx = GPIO_AF_UART4; |
|
150 | gpioAFuartx = GPIO_AF_UART4; | |
151 | break; |
|
151 | break; | |
152 |
case |
|
152 | case uart5: | |
153 | gpioAFuartx = GPIO_AF_UART5; |
|
153 | gpioAFuartx = GPIO_AF_UART5; | |
154 | break; |
|
154 | break; | |
155 |
case |
|
155 | case uart6: | |
156 | gpioAFuartx = GPIO_AF_USART6; |
|
156 | gpioAFuartx = GPIO_AF_USART6; | |
157 | break; |
|
157 | break; | |
158 | default: |
|
158 | default: | |
@@ -448,16 +448,3 int uartmkstreamdev(uart_t uart,streamde | |||||
448 |
|
448 | |||
449 |
|
449 | |||
450 |
|
450 | |||
451 |
|
||||
452 |
|
||||
453 |
|
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454 |
|
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455 |
|
||||
456 |
|
||||
457 |
|
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458 |
|
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459 |
|
||||
460 |
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||||
461 |
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||||
462 |
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||||
463 |
|
@@ -9,6 +9,9 INCLUDEPATH += $$LIBUC_LIBS_DIR/includes | |||||
9 | LIBUC_BIN_LIBS_DIR = $$LIBUC_LIBS_DIR/bin/$$ARCH |
|
9 | LIBUC_BIN_LIBS_DIR = $$LIBUC_LIBS_DIR/bin/$$ARCH | |
10 |
|
10 | |||
11 | LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ |
|
11 | LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ | |
|
12 | -lCS43L22 | |||
|
13 | ||||
|
14 | LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ | |||
12 | -lsdcard |
|
15 | -lsdcard | |
13 |
|
16 | |||
14 | LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ |
|
17 | LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ |
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