@@ -0,0 +1,12 | |||
|
1 | TEMPLATE = app | |
|
2 | CONFIG += console | |
|
3 | CONFIG -= qt | |
|
4 | ||
|
5 | #BSP = BEAGLESYNTH | |
|
6 | BSP = SOLAR_LFR_PSU | |
|
7 | include($$(libuc2)/bsp/cfg/$$BSP/bsp.pri) | |
|
8 | #include($$(libuc2)/rules/stm32f4-arm-none-eabi-gcc/rules.pri) | |
|
9 | ||
|
10 | SOURCES += \ | |
|
11 | main.c | |
|
12 |
@@ -0,0 +1,121 | |||
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1 | #!/usr/bin/python | |
|
2 | ||
|
3 | # Written by Antonio Galea - 2010/11/18 | |
|
4 | # Distributed under Gnu LGPL 3.0 | |
|
5 | # see http://www.gnu.org/licenses/lgpl-3.0.txt | |
|
6 | ||
|
7 | import sys,struct,zlib,os | |
|
8 | from optparse import OptionParser | |
|
9 | ||
|
10 | DEFAULT_DEVICE="0x0483:0xdf11" | |
|
11 | ||
|
12 | def named(tuple,names): | |
|
13 | return dict(zip(names.split(),tuple)) | |
|
14 | def consume(fmt,data,names): | |
|
15 | n = struct.calcsize(fmt) | |
|
16 | return named(struct.unpack(fmt,data[:n]),names),data[n:] | |
|
17 | def cstring(string): | |
|
18 | return string.split('\0',1)[0] | |
|
19 | def compute_crc(data): | |
|
20 | return 0xFFFFFFFF & -zlib.crc32(data) -1 | |
|
21 | ||
|
22 | def parse(file,dump_images=False): | |
|
23 | print 'File: "%s"' % file | |
|
24 | data = open(file,'rb').read() | |
|
25 | crc = compute_crc(data[:-4]) | |
|
26 | prefix, data = consume('<5sBIB',data,'signature version size targets') | |
|
27 | print '%(signature)s v%(version)d, image size: %(size)d, targets: %(targets)d' % prefix | |
|
28 | for t in range(prefix['targets']): | |
|
29 | tprefix, data = consume('<6sBI255s2I',data,'signature altsetting named name size elements') | |
|
30 | tprefix['num'] = t | |
|
31 | if tprefix['named']: | |
|
32 | tprefix['name'] = cstring(tprefix['name']) | |
|
33 | else: | |
|
34 | tprefix['name'] = '' | |
|
35 | print '%(signature)s %(num)d, alt setting: %(altsetting)s, name: "%(name)s", size: %(size)d, elements: %(elements)d' % tprefix | |
|
36 | tsize = tprefix['size'] | |
|
37 | target, data = data[:tsize], data[tsize:] | |
|
38 | for e in range(tprefix['elements']): | |
|
39 | eprefix, target = consume('<2I',target,'address size') | |
|
40 | eprefix['num'] = e | |
|
41 | print ' %(num)d, address: 0x%(address)08x, size: %(size)d' % eprefix | |
|
42 | esize = eprefix['size'] | |
|
43 | image, target = target[:esize], target[esize:] | |
|
44 | if dump_images: | |
|
45 | out = '%s.target%d.image%d.bin' % (file,t,e) | |
|
46 | open(out,'wb').write(image) | |
|
47 | print ' DUMPED IMAGE TO "%s"' % out | |
|
48 | if len(target): | |
|
49 | print "target %d: PARSE ERROR" % t | |
|
50 | suffix = named(struct.unpack('<4H3sBI',data[:16]),'device product vendor dfu ufd len crc') | |
|
51 | print 'usb: %(vendor)04x:%(product)04x, device: 0x%(device)04x, dfu: 0x%(dfu)04x, %(ufd)s, %(len)d, 0x%(crc)08x' % suffix | |
|
52 | if crc != suffix['crc']: | |
|
53 | print "CRC ERROR: computed crc32 is 0x%08x" % crc | |
|
54 | data = data[16:] | |
|
55 | if data: | |
|
56 | print "PARSE ERROR" | |
|
57 | ||
|
58 | def build(file,targets,device=DEFAULT_DEVICE): | |
|
59 | data = '' | |
|
60 | for t,target in enumerate(targets): | |
|
61 | tdata = '' | |
|
62 | for image in target: | |
|
63 | tdata += struct.pack('<2I',image['address'],len(image['data']))+image['data'] | |
|
64 | tdata = struct.pack('<6sBI255s2I','Target',0,1,'ST...',len(tdata),len(target)) + tdata | |
|
65 | data += tdata | |
|
66 | data = struct.pack('<5sBIB','DfuSe',1,len(data)+11,len(targets)) + data | |
|
67 | v,d=map(lambda x: int(x,0) & 0xFFFF, device.split(':',1)) | |
|
68 | data += struct.pack('<4H3sB',0,d,v,0x011a,'UFD',16) | |
|
69 | crc = compute_crc(data) | |
|
70 | data += struct.pack('<I',crc) | |
|
71 | open(file,'wb').write(data) | |
|
72 | ||
|
73 | if __name__=="__main__": | |
|
74 | usage = """ | |
|
75 | %prog [-d|--dump] infile.dfu | |
|
76 | %prog {-b|--build} address:file.bin [-b address:file.bin ...] [{-D|--device}=vendor:device] outfile.dfu""" | |
|
77 | parser = OptionParser(usage=usage) | |
|
78 | parser.add_option("-b", "--build", action="append", dest="binfiles", | |
|
79 | help="build a DFU file from given BINFILES", metavar="BINFILES") | |
|
80 | parser.add_option("-D", "--device", action="store", dest="device", | |
|
81 | help="build for DEVICE, defaults to %s" % DEFAULT_DEVICE, metavar="DEVICE") | |
|
82 | parser.add_option("-d", "--dump", action="store_true", dest="dump_images", | |
|
83 | default=False, help="dump contained images to current directory") | |
|
84 | (options, args) = parser.parse_args() | |
|
85 | ||
|
86 | if options.binfiles and len(args)==1: | |
|
87 | target = [] | |
|
88 | for arg in options.binfiles: | |
|
89 | try: | |
|
90 | address,binfile = arg.split(':',1) | |
|
91 | except ValueError: | |
|
92 | print "Address:file couple '%s' invalid." % arg | |
|
93 | sys.exit(1) | |
|
94 | try: | |
|
95 | address = int(address,0) & 0xFFFFFFFF | |
|
96 | except ValueError: | |
|
97 | print "Address %s invalid." % address | |
|
98 | sys.exit(1) | |
|
99 | if not os.path.isfile(binfile): | |
|
100 | print "Unreadable file '%s'." % binfile | |
|
101 | sys.exit(1) | |
|
102 | target.append({ 'address': address, 'data': open(binfile,'rb').read() }) | |
|
103 | outfile = args[0] | |
|
104 | device = DEFAULT_DEVICE | |
|
105 | if options.device: | |
|
106 | device=options.device | |
|
107 | try: | |
|
108 | v,d=map(lambda x: int(x,0) & 0xFFFF, device.split(':',1)) | |
|
109 | except: | |
|
110 | print "Invalid device '%s'." % device | |
|
111 | sys.exit(1) | |
|
112 | build(outfile,[target],device) | |
|
113 | elif len(args)==1: | |
|
114 | infile = args[0] | |
|
115 | if not os.path.isfile(infile): | |
|
116 | print "Unreadable file '%s'." % infile | |
|
117 | sys.exit(1) | |
|
118 | parse(infile, dump_images=options.dump_images) | |
|
119 | else: | |
|
120 | parser.print_help() | |
|
121 | sys.exit(1) |
@@ -0,0 +1,41 | |||
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1 | #include <stdio.h> | |
|
2 | #include <fat32.h> | |
|
3 | #include <gpio.h> | |
|
4 | #include <uart.h> | |
|
5 | #include <stm32f4xx.h> | |
|
6 | #include <bsp.h> | |
|
7 | #include <i2c.h> | |
|
8 | ||
|
9 | ||
|
10 | extern streamdevice* __opnfiles__[]; | |
|
11 | ||
|
12 | int main() | |
|
13 | { | |
|
14 | //gpioset(PSU_DISABLE); | |
|
15 | printf("i2C Control register 1 (I2C_CR1) = %x\n\r",I2C1->CR1); | |
|
16 | printf("i2C Control register 2 (I2C_CR2) = %x\n\r",I2C1->CR2); | |
|
17 | printf("i2C Status register 1 (I2C_SR1) = %x\n\r",I2C1->SR1); | |
|
18 | printf("i2C Status register 2 (I2C_SR2) = %x\n\r",I2C1->SR2); | |
|
19 | printf("i2C Clock control register (I2C_CCR) = %x\n\r",I2C1->CCR); | |
|
20 | while(1) | |
|
21 | { | |
|
22 | for(volatile int i=0;i<1024*2048;i++); | |
|
23 | gpioset(LED1); | |
|
24 | gpioclr(LED2); | |
|
25 | for(volatile int i=0;i<1024*2048;i++); | |
|
26 | gpioclr(LED1); | |
|
27 | gpioset(LED2); | |
|
28 | i2cwrite(i2c1,0x4a,"test",4); | |
|
29 | } | |
|
30 | printf("hello world\n\r"); | |
|
31 | return 0; | |
|
32 | } | |
|
33 | ||
|
34 | ||
|
35 | ||
|
36 | ||
|
37 | ||
|
38 | ||
|
39 | ||
|
40 | ||
|
41 |
@@ -0,0 +1,71 | |||
|
1 | /*------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the libuc, microcontroler library | |
|
3 | -- Copyright (C) 2012, Alexis Jeandet | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@gmail.com | |
|
21 | -------------------------------------------------------------------------------*/ | |
|
22 | #ifndef I2C_H | |
|
23 | #define I2C_H | |
|
24 | #include <stdint.h> | |
|
25 | #include <uhandle.h> | |
|
26 | #include <streamdevices.h> | |
|
27 | ||
|
28 | #ifdef __cplusplus | |
|
29 | extern "C" { | |
|
30 | #endif | |
|
31 | ||
|
32 | typedef int i2c_t; | |
|
33 | ||
|
34 | #define i2c1 0 | |
|
35 | #define i2c2 1 | |
|
36 | #define i2c3 2 | |
|
37 | #define i2c4 3 | |
|
38 | #define i2c5 4 | |
|
39 | #define i2c6 5 | |
|
40 | #define i2c7 6 | |
|
41 | #define i2c8 7 | |
|
42 | #define i2c9 8 | |
|
43 | ||
|
44 | extern i2c_t i2copen(int count); | |
|
45 | extern i2c_t i2copenandconfig(int count ,uint32_t cfg,uint32_t speed,uint32_t SDA,uint32_t SCL); | |
|
46 | extern int i2cclose(i2c_t dev); | |
|
47 | extern int i2csetpins(i2c_t dev,uint32_t SDA,uint32_t SCL); | |
|
48 | extern int i2cenable(i2c_t dev); | |
|
49 | extern int i2cdisable(i2c_t dev); | |
|
50 | //extern int i2csetconfig(i2c_t dev); | |
|
51 | extern int i2csetspeed(i2c_t dev,uint32_t speed); | |
|
52 | //extern int i2csetdatabits(i2c_t* dev,uartbits_t databits); | |
|
53 | extern int i2cwrite(i2c_t dev,char address,char* data,int count); | |
|
54 | extern int i2cread(i2c_t dev,char address,char* data,int count); | |
|
55 | ||
|
56 | #ifdef __cplusplus | |
|
57 | } | |
|
58 | #endif | |
|
59 | #endif //I2C_H | |
|
60 | ||
|
61 | ||
|
62 | ||
|
63 | ||
|
64 | ||
|
65 | ||
|
66 | ||
|
67 | ||
|
68 | ||
|
69 | ||
|
70 | ||
|
71 |
@@ -0,0 +1,246 | |||
|
1 | /*------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the libuc, microcontroler library | |
|
3 | -- Copyright (C) 2012, Alexis Jeandet | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@gmail.com | |
|
21 | -------------------------------------------------------------------------------*/ | |
|
22 | ||
|
23 | #include <i2c.h> | |
|
24 | #include <stm32f4xx_usart.h> | |
|
25 | #include <stm32f4xx_rcc.h> | |
|
26 | #include <stm32f4xx_gpio.h> | |
|
27 | #include <gpio.h> | |
|
28 | #include <core.h> | |
|
29 | ||
|
30 | #define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA)) | |
|
31 | #define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8) | |
|
32 | ||
|
33 | ||
|
34 | I2C_TypeDef* _i2c_dev_table[3]={I2C1,I2C2,I2C3}; | |
|
35 | ||
|
36 | i2c_t i2copen(int count) | |
|
37 | { | |
|
38 | #define _INIT_DEV(_RCC_) \ | |
|
39 | RCC_APB1PeriphClockCmd(_RCC_, ENABLE); \ | |
|
40 | RCC_APB1PeriphResetCmd(_RCC_, ENABLE); \ | |
|
41 | RCC_APB1PeriphResetCmd(_RCC_, DISABLE); \ | |
|
42 | RCC_APB1PeriphClockCmd(_RCC_, ENABLE); | |
|
43 | ||
|
44 | switch(count) | |
|
45 | { | |
|
46 | case 0: | |
|
47 | _INIT_DEV(RCC_APB1Periph_I2C1); | |
|
48 | return (i2c_t) 0; | |
|
49 | break; | |
|
50 | case 1: | |
|
51 | _INIT_DEV(RCC_APB1Periph_I2C2); | |
|
52 | return (i2c_t) 1; | |
|
53 | break; | |
|
54 | case 2: | |
|
55 | _INIT_DEV(RCC_APB1Periph_I2C3); | |
|
56 | return (i2c_t) 2; | |
|
57 | break; | |
|
58 | default: | |
|
59 | break; | |
|
60 | } | |
|
61 | return -1; | |
|
62 | } | |
|
63 | ||
|
64 | i2c_t i2copenandconfig(int count,uint32_t cfg,uint32_t speed,uint32_t SDA,uint32_t SCL) | |
|
65 | { | |
|
66 | i2c_t dev = i2copen(count); | |
|
67 | printf("dev = %d\n\r",dev); | |
|
68 | if(dev!=-1) | |
|
69 | { | |
|
70 | i2cenable(count); | |
|
71 | I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev]; | |
|
72 | _dev_->CR1 = (1<<15); | |
|
73 | _dev_->CR1 &=~(1<<15); | |
|
74 | i2cdisable(count); | |
|
75 | i2csetpins(dev,SDA,SCL); | |
|
76 | i2csetspeed(dev,speed); | |
|
77 | i2cenable(count); | |
|
78 | } | |
|
79 | return dev; | |
|
80 | } | |
|
81 | ||
|
82 | int i2cclose(i2c_t dev) | |
|
83 | { | |
|
84 | switch((int)dev) | |
|
85 | { | |
|
86 | case (int)0: | |
|
87 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); | |
|
88 | break; | |
|
89 | case (int)1: | |
|
90 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); | |
|
91 | break; | |
|
92 | case (int)2: | |
|
93 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, ENABLE); | |
|
94 | break; | |
|
95 | default: | |
|
96 | break; | |
|
97 | } | |
|
98 | return 1; | |
|
99 | } | |
|
100 | ||
|
101 | int i2csetpins(i2c_t dev, uint32_t SDA, uint32_t SCL) | |
|
102 | { | |
|
103 | if((dev<3)&&(dev>=0)) | |
|
104 | { | |
|
105 | gpio_t SDApin,SCLpin; | |
|
106 | SDApin = gpioopen(SDA); | |
|
107 | SCLpin = gpioopen(SCL); | |
|
108 | SDApin |= gpiolowspeed | gpioaf | gpioopendraintype | gpionopulltype; | |
|
109 | SCLpin |= gpiolowspeed | gpioaf | gpioopendraintype | gpionopulltype; | |
|
110 | gpiosetconfig(&SDApin); | |
|
111 | gpiosetconfig(&SCLpin); | |
|
112 | uint8_t gpioAFi2cx = GPIO_AF_I2C1; | |
|
113 | switch((int)dev) | |
|
114 | { | |
|
115 | case 0: | |
|
116 | gpioAFi2cx = GPIO_AF_I2C1; | |
|
117 | break; | |
|
118 | case 1: | |
|
119 | gpioAFi2cx = GPIO_AF_I2C2; | |
|
120 | break; | |
|
121 | case 2: | |
|
122 | gpioAFi2cx = GPIO_AF_I2C3; | |
|
123 | break; | |
|
124 | default: | |
|
125 | break; | |
|
126 | } | |
|
127 | GPIO_PinAFConfig(GPIOGETPORT(SDApin), (uint8_t)(SDApin & 0xF), gpioAFi2cx); | |
|
128 | GPIO_PinAFConfig(GPIOGETPORT(SCLpin), (uint8_t)(SCLpin & 0xF), gpioAFi2cx); | |
|
129 | return 0; | |
|
130 | } | |
|
131 | return -1; | |
|
132 | } | |
|
133 | ||
|
134 | int i2cenable(i2c_t dev) | |
|
135 | { | |
|
136 | if((dev<3)&&(dev>=0)) | |
|
137 | { | |
|
138 | I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev]; | |
|
139 | _dev_->CR1 |=1 ; | |
|
140 | return 0; | |
|
141 | } | |
|
142 | return -1; | |
|
143 | } | |
|
144 | ||
|
145 | int i2cdisable(i2c_t dev) | |
|
146 | { | |
|
147 | if((dev<3)&&(dev>=0)) | |
|
148 | { | |
|
149 | I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev]; | |
|
150 | _dev_->CR1 &= ~1; | |
|
151 | return 0; | |
|
152 | } | |
|
153 | return -1; | |
|
154 | } | |
|
155 | ||
|
156 | ||
|
157 | int i2csetspeed(i2c_t dev,uint32_t speed) | |
|
158 | { | |
|
159 | if((dev<3)&&(dev>=0)) | |
|
160 | { | |
|
161 | I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev]; | |
|
162 | int32_t APB1Freq=getAPB1Freq()/1000000; | |
|
163 | if((APB1Freq>1)&&(APB1Freq<43)) | |
|
164 | { | |
|
165 | int enabled=((_dev_->CR1&1)==1); | |
|
166 | i2cdisable(dev); | |
|
167 | _dev_->CR2 &= ~(0x1f); | |
|
168 | _dev_->CR2 |= APB1Freq; | |
|
169 | if(speed>100000) //100kHz= standard mode, 400kHz= fast mode | |
|
170 | { | |
|
171 | if(speed<=400000) | |
|
172 | { | |
|
173 | _dev_->CCR |= 1<<15; | |
|
174 | _dev_->CCR &= ~(1<<14); | |
|
175 | _dev_->CCR &= ~(0xfff); | |
|
176 | _dev_->CCR |= 0xfff & (APB1Freq/(3*speed)); | |
|
177 | } | |
|
178 | } | |
|
179 | else | |
|
180 | { | |
|
181 | _dev_->CCR &= ~(1<<15); | |
|
182 | _dev_->CCR &= ~(0xfff); | |
|
183 | _dev_->CCR |= 0xfff & (APB1Freq/(2*speed)); | |
|
184 | } | |
|
185 | if(enabled)i2cenable(dev); | |
|
186 | return 0; | |
|
187 | } | |
|
188 | } | |
|
189 | return -1; | |
|
190 | } | |
|
191 | ||
|
192 | int i2cwrite(i2c_t dev,char address,char* data,int count) | |
|
193 | { | |
|
194 | if((dev<3)&&(dev>=0)) | |
|
195 | { | |
|
196 | I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev]; | |
|
197 | _dev_->CR1 |= 1<<8; | |
|
198 | while((_dev_->SR1&1)==0); | |
|
199 | _dev_->DR= address<<1; | |
|
200 | while((_dev_->SR1 & (1<<3))==0); | |
|
201 | address=_dev_->SR2; | |
|
202 | for(int i=0;i<count;i++) | |
|
203 | { | |
|
204 | while((_dev_->SR1 & (1<<7))==0); | |
|
205 | _dev_->DR= data[i]; | |
|
206 | } | |
|
207 | while((_dev_->SR1 & (1<<7))==0); | |
|
208 | while((_dev_->SR1 & (1<<2))==0); | |
|
209 | _dev_->CR1 |= 1<<9; | |
|
210 | return count; | |
|
211 | } | |
|
212 | return -1; | |
|
213 | } | |
|
214 | ||
|
215 | int i2cread(i2c_t dev,char address,char* data,int count) | |
|
216 | { | |
|
217 | if((dev<3)&&(dev>=0)) | |
|
218 | { | |
|
219 | I2C_TypeDef* _dev_ = _i2c_dev_table[(int)dev]; | |
|
220 | _dev_->CR1 |= (1<<8) | (1<<10); | |
|
221 | if(count==1) | |
|
222 | { | |
|
223 | _dev_->CR1 &= ~(1<<10); | |
|
224 | } | |
|
225 | while((_dev_->SR1&1)==0); | |
|
226 | _dev_->DR= (address<<1) + 1; | |
|
227 | while((_dev_->SR1 & (1<<3))==0); | |
|
228 | address=_dev_->SR2; | |
|
229 | for(int i=0;i<count-1;i++) | |
|
230 | { | |
|
231 | while((_dev_->SR1 & (1<<6))==0); | |
|
232 | data[i]=_dev_->DR; | |
|
233 | } | |
|
234 | _dev_->CR1 &= ~(1<<10); | |
|
235 | _dev_->CR1 |= 1<<9; | |
|
236 | while((_dev_->SR1 & (1<<6))==0); | |
|
237 | data[count-1]=_dev_->DR; | |
|
238 | return count; | |
|
239 | } | |
|
240 | return -1; | |
|
241 | } | |
|
242 | ||
|
243 | ||
|
244 | ||
|
245 | ||
|
246 |
@@ -0,0 +1,13 | |||
|
1 | TEMPLATE = lib | |
|
2 | CONFIG += console | |
|
3 | CONFIG -= qt | |
|
4 | include($$(libuc2)/rules/stm32f4-arm-none-eabi-gcc/rules.pri) | |
|
5 | ||
|
6 | SOURCES += \ | |
|
7 | i2c.c | |
|
8 | ||
|
9 | ||
|
10 | HEADERS += \ | |
|
11 | $$(libuc2)/lib/includes/i2c.h | |
|
12 | ||
|
13 |
@@ -37,8 +37,11 | |||
|
37 | 37 | #endif |
|
38 | 38 | */ |
|
39 | 39 | |
|
40 |
#define LED1 PD |
|
|
41 |
#define LED2 PD |
|
|
40 | #define LED1 PD12 | |
|
41 | #define LED2 PD13 | |
|
42 | #define LED3 PD14 | |
|
43 | #define LED4 PD15 | |
|
44 | ||
|
42 | 45 | |
|
43 | 46 | #define LED3ON GPIOB->BSRRH = GPIO_Pin_15 |
|
44 | 47 | #define LED2ON GPIOD->BSRRH = GPIO_Pin_8 |
@@ -25,6 +25,8 | |||
|
25 | 25 | #include <gpio.h> |
|
26 | 26 | #include <uart.h> |
|
27 | 27 | #include <stdio.h> |
|
28 | #include <i2c.h> | |
|
29 | ||
|
28 | 30 | uint32_t OSC0 =8000000; |
|
29 | 31 | uint32_t INTOSC =16000000; |
|
30 | 32 | uint32_t RTCOSC =32768; |
@@ -42,6 +44,7 int bsp_init() | |||
|
42 | 44 | } |
|
43 | 45 | bsp_GPIO_init(); |
|
44 | 46 | bsp_uart_init(); |
|
47 | bsp_iic_init(); | |
|
45 | 48 | printf("\r================================================================\n\r"); |
|
46 | 49 | printf("================================================================\n\r"); |
|
47 | 50 | printf(BSP); |
@@ -90,7 +93,8 void bsp_spi_init() | |||
|
90 | 93 | |
|
91 | 94 | void bsp_iic_init() |
|
92 | 95 | { |
|
93 | ||
|
96 | if(0==i2copenandconfig(i2c1,0,100000,PB9,PB6))printf("I2C1 opened\n\r"); | |
|
97 | i2cenable(i2c1); | |
|
94 | 98 | } |
|
95 | 99 | |
|
96 | 100 | void bsp_SD_init() |
@@ -2,7 +2,8 TEMPLATE = app | |||
|
2 | 2 | CONFIG += console |
|
3 | 3 | CONFIG -= qt |
|
4 | 4 | |
|
5 | BSP = BEAGLESYNTH | |
|
5 | #BSP = BEAGLESYNTH | |
|
6 | BSP = SOLAR_LFR_PSU | |
|
6 | 7 | include($$(libuc2)/bsp/cfg/$$BSP/bsp.pri) |
|
7 | 8 | #include($$(libuc2)/rules/stm32f4-arm-none-eabi-gcc/rules.pri) |
|
8 | 9 |
@@ -10,7 +10,7 extern streamdevice* __opnfiles__[]; | |||
|
10 | 10 | |
|
11 | 11 | int main() |
|
12 | 12 | { |
|
13 | gpioset(PSU_DISABLE); | |
|
13 | //gpioset(PSU_DISABLE); | |
|
14 | 14 | while(1) |
|
15 | 15 | { |
|
16 | 16 | for(volatile int i=0;i<1024*2048;i++); |
@@ -3,7 +3,8 CONFIG += ordered | |||
|
3 | 3 | SUBDIRS += QtTest/test.pro \ |
|
4 | 4 | SOLAR_PSU_HELLO/hello.pro \ |
|
5 | 5 | SDCARD \ |
|
6 | STM32F4IT | |
|
6 | STM32F4IT \ | |
|
7 | BeagleSynthHello | |
|
7 | 8 | |
|
8 | 9 | |
|
9 | 10 |
@@ -33,8 +33,17 | |||
|
33 | 33 | extern "C" { |
|
34 | 34 | #endif |
|
35 | 35 | |
|
36 | extern void coresetCpuFreq(unsigned int freq); | |
|
37 |
extern u |
|
|
36 | extern uint32_t getAPB1Freq(); | |
|
37 | extern uint32_t getAPB2Freq(); | |
|
38 | extern uint32_t getCpuFreq(); | |
|
39 | extern int setCpuFreq(uint32_t freq); | |
|
40 | extern int optimizePLLcfg(uint32_t freq, uint32_t srcfreq,uint32_t PLLM,uint32_t* PLLP, uint32_t* PLLN,uint8_t* AHBPRindx); | |
|
41 | extern int setPll(uint32_t freq); | |
|
42 | extern void enable_FPU(); | |
|
43 | extern void reset_AHB1(); | |
|
44 | extern void reset_AHB2(); | |
|
45 | extern void reset_APB1(); | |
|
46 | extern void reset_APB2(); | |
|
38 | 47 | |
|
39 | 48 | #ifdef __cplusplus |
|
40 | 49 | } |
@@ -21,25 +21,305 | |||
|
21 | 21 | -------------------------------------------------------------------------------*/ |
|
22 | 22 | #include "core.h" |
|
23 | 23 | #include <stm32f4xx_rcc.h> |
|
24 | #include <stdint.h> | |
|
25 | #include <stdlib.h> | |
|
26 | #include <stdio.h> | |
|
24 | 27 | |
|
25 |
|
|
|
28 | extern uint32_t OSC0; | |
|
26 | 29 | extern uint32_t INTOSC; |
|
27 | 30 | extern uint32_t RTCOSC; |
|
28 | 31 | |
|
29 | void coresetCpuFreq(unsigned int freq) | |
|
32 | ||
|
33 | uint32_t getAPB1Freq() | |
|
30 | 34 | { |
|
35 | RCC_ClocksTypeDef RCC_ClocksStatus; | |
|
36 | RCC_GetClocksFreq(&RCC_ClocksStatus); | |
|
37 | return RCC_ClocksStatus.PCLK1_Frequency; | |
|
38 | } | |
|
39 | ||
|
40 | uint32_t getAPB2Freq() | |
|
41 | { | |
|
42 | RCC_ClocksTypeDef RCC_ClocksStatus; | |
|
43 | RCC_GetClocksFreq(&RCC_ClocksStatus); | |
|
44 | return RCC_ClocksStatus.PCLK2_Frequency; | |
|
45 | } | |
|
31 | 46 | |
|
32 | 47 | |
|
48 | uint32_t getCpuFreq() | |
|
49 | { | |
|
50 | uint32_t cpufreq = OSC0; | |
|
51 | uint32_t PLLN,PLLM,PLLP; | |
|
52 | ||
|
53 | if((RCC->CFGR & 0xC) == 8) //PLL used as sys clk | |
|
54 | { | |
|
55 | uint32_t pllinput=INTOSC; | |
|
56 | if((RCC->PLLCFGR & (1<<22)) == (1<<22)) | |
|
57 | { | |
|
58 | pllinput=OSC0; | |
|
59 | } | |
|
60 | PLLN = (RCC->PLLCFGR>>6) & 0x1FF; | |
|
61 | PLLM = RCC->PLLCFGR & 0x3F; | |
|
62 | PLLP = 1<<(((RCC->PLLCFGR>>16) & 3 )+1); | |
|
63 | cpufreq = (pllinput * PLLN )/(PLLM*PLLP); | |
|
64 | } | |
|
65 | else if((RCC->CFGR & 0xC) == 0) //HSI used as sys clk | |
|
66 | { | |
|
67 | cpufreq=INTOSC; | |
|
68 | } | |
|
69 | if((RCC->CFGR & (1<<7))==1<<7) | |
|
70 | { | |
|
71 | return cpufreq>>((RCC->CFGR & (7<<4))>>4); | |
|
72 | } | |
|
73 | return cpufreq; | |
|
74 | } | |
|
75 | ||
|
76 | void reset_AHB1() | |
|
77 | { | |
|
78 | RCC->AHB1RSTR = -1; | |
|
79 | RCC->AHB1RSTR = 0; | |
|
80 | } | |
|
81 | ||
|
82 | void reset_AHB2() | |
|
83 | { | |
|
84 | RCC->AHB2RSTR = -1; | |
|
85 | RCC->AHB2RSTR = 0; | |
|
86 | } | |
|
87 | ||
|
88 | void reset_APB1() | |
|
89 | { | |
|
90 | RCC->APB1RSTR = -1; | |
|
91 | RCC->APB1RSTR = 0; | |
|
92 | } | |
|
93 | ||
|
94 | void reset_APB2() | |
|
95 | { | |
|
96 | RCC->APB2RSTR = -1; | |
|
97 | RCC->APB2RSTR = 0; | |
|
33 | 98 | } |
|
34 | 99 | |
|
35 | 100 | |
|
36 | 101 | |
|
102 | /* | |
|
103 | | 2.7->3.6V | |
|
104 | ------------------------- | |
|
105 | 0WS | 0<HCLK<=30 | |
|
106 | 1WS | 30<HCLK<=60 | |
|
107 | 2WS | 60<HCLK<=90 | |
|
108 | 3WS | 90<HCLK<=120 | |
|
109 | 4WS | 120<HCLK<=150 | |
|
110 | 5WS | 150<HCLK<=168 | |
|
37 | 111 |
|
|
38 | unsigned int coregetCpuFreq() | |
|
112 | f(VCO clock) = f(PLL clock input) × (PLLN / PLLM) [1] | |
|
113 | 64MHz <= f(VCO clock) <= 432MHz [2] | |
|
114 | ||
|
115 | f(VCO clock input) must be between 1MHz and 2MHz and as close to 2MHz as possible!! [3] | |
|
116 | ||
|
117 | f(PLL general clock output) = f(VCO clock) / PLLP [4] | |
|
118 | ||
|
119 | CPU<168MHz AHB1<168MHz AHB2<168MHz APB1<42MHz APB2<84MHz [5] | |
|
120 | ||
|
121 | ! 63<=PLLN<=432 [6] | |
|
122 | ! 2<=PLLM<=63 [7] | |
|
123 | ! PLLP=2,4,6,8 [8] | |
|
124 | 4<=PLLM*PLLP<=504 | |
|
125 | ||
|
126 | F= f(PLL clock input) * A/B with | |
|
127 | 63<=A<=432 | |
|
128 | 4<=B<=504 | |
|
129 | ||
|
130 | */ | |
|
131 | ||
|
132 | ||
|
133 | int optimizePLLcfg(uint32_t freq, uint32_t srcfreq,uint32_t PLLM,uint32_t* PLLP, uint32_t* PLLN,uint8_t* AHBPRindx) | |
|
134 | { | |
|
135 | uint32_t AHBPRtbl[9]={1,2,4,8,16,64,128,256,512}; | |
|
136 | uint32_t AHBPR=0,AHBPR_r=0,PLLN_r=0,PLLP_r=0; | |
|
137 | uint32_t Fplli=0; | |
|
138 | int32_t f_error=100000000; | |
|
139 | int32_t f_errornw=100000000; | |
|
140 | Fplli = srcfreq / PLLM; | |
|
141 | //not efficient but should find the best parameters | |
|
142 | for((*AHBPRindx)=0;(*AHBPRindx)<9;(*AHBPRindx)++) //lowest priority | |
|
143 | { | |
|
144 | AHBPR = AHBPRtbl[(*AHBPRindx)]; | |
|
145 | for(*PLLP=2;*PLLP<9;*PLLP+=2) | |
|
146 | { | |
|
147 | *PLLN = (freq*(*PLLP)*AHBPR)/Fplli; | |
|
148 | if(((*PLLN)>62) && ((*PLLN)<433) && ((Fplli * (*PLLN)) < 433000000)) | |
|
149 | { | |
|
150 | f_errornw = abs((int32_t)((int32_t)((Fplli*(*PLLN))/((*PLLP)*AHBPR))-freq)); | |
|
151 | if( ( (f_error)>(f_errornw) ) || ( (*AHBPRindx==0)&&(*PLLP==2)&&(*PLLN==63) ) ) | |
|
152 | { | |
|
153 | f_error=f_errornw; | |
|
154 | PLLN_r = *PLLN; | |
|
155 | PLLP_r = *PLLP; | |
|
156 | AHBPR_r=*AHBPRindx; | |
|
157 | if(f_error==0) | |
|
158 | { | |
|
159 | *PLLN = PLLN_r; | |
|
160 | *PLLP = PLLP_r; | |
|
161 | *AHBPRindx = AHBPR_r; | |
|
162 | return 1; | |
|
163 | } | |
|
164 | } | |
|
165 | } | |
|
166 | } | |
|
167 | } | |
|
168 | *PLLN = PLLN_r; | |
|
169 | *PLLP = PLLP_r; | |
|
170 | *AHBPRindx = AHBPR_r; | |
|
171 | return 1; | |
|
172 | } | |
|
173 | ||
|
174 | ||
|
175 | int setPll(uint32_t freq) | |
|
39 | 176 | { |
|
40 | RCC_ClocksTypeDef RCC_ClocksStatus; | |
|
41 | RCC_GetClocksFreq(&RCC_ClocksStatus); | |
|
42 | return RCC_ClocksStatus.SYSCLK_Frequency; | |
|
177 | extern uint32_t OSC0; | |
|
178 | extern uint32_t INTOSC; | |
|
179 | uint32_t srcfreq = INTOSC; | |
|
180 | uint8_t AHBPRindx; | |
|
181 | uint32_t AHBPRtbl[9]={1,2,4,8,16,64,128,256,512}; | |
|
182 | uint32_t PLLN=0,PLLM=0,PLLP=0,AHBPR=0; | |
|
183 | uint32_t Fplli=0; | |
|
184 | if((RCC->PLLCFGR & (1<<22))==(1<<22)) | |
|
185 | { | |
|
186 | srcfreq = OSC0; | |
|
187 | } | |
|
188 | PLLM = srcfreq / 1500000; // [3] | |
|
189 | Fplli = srcfreq / PLLM; | |
|
190 | optimizePLLcfg(freq,srcfreq,PLLM,&PLLP,&PLLN,&AHBPRindx); | |
|
191 | srcfreq = (Fplli*PLLN)/(PLLP*AHBPRtbl[AHBPRindx]); //Put real clk freq in srcfreq for return value | |
|
192 | //now switch to HSIs | |
|
193 | if((RCC->CR & 1)==0)RCC->CR |= 1; //turn ON HSI | |
|
194 | while((RCC->CR & 2)!=2); //wait for HSI Ready | |
|
195 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); | |
|
196 | RCC->CFGR |= RCC_CFGR_SW_HSI; //set HSI as main clk | |
|
197 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_HSI); | |
|
198 | RCC->CR &= ~(1<<24); //Turn OFF PLL | |
|
199 | RCC->PLLCFGR &= ~0x37FFF; //clear PLLP PLLM PLLN | |
|
200 | RCC->PLLCFGR |= PLLM + (PLLN<<6) + (((PLLP>>1) -1)<<16); | |
|
201 | RCC->CR |= RCC_CR_PLLON; //Turn ON PLL | |
|
202 | while((RCC->CR & (1<<25))!=(1<<25)); //wait for PLL Ready | |
|
203 | if(AHBPRindx!=0)AHBPRindx|=0x8; | |
|
204 | RCC->CFGR &= ~(0xF<<4); | |
|
205 | RCC->CFGR |= (uint32_t)(AHBPRindx<<4); | |
|
206 | AHBPR=0; | |
|
207 | while((srcfreq>>AHBPR)>42000000)AHBPR++; //[5] //Thune APB1 prescaler to keep APB1 CLK below 42MHz | |
|
208 | if(AHBPR!=0) | |
|
209 | { | |
|
210 | AHBPR-=1; | |
|
211 | AHBPR|=0x4; | |
|
212 | } | |
|
213 | RCC->CFGR &= ~(0x7<<10); | |
|
214 | RCC->CFGR |= (uint32_t)(AHBPR<<10); | |
|
215 | AHBPR=0; | |
|
216 | while((srcfreq>>AHBPR)>84000000)AHBPR++; //[5] //Thune APB2 prescaler to keep APB2 CLK below 42MHz | |
|
217 | if(AHBPR!=0) | |
|
218 | { | |
|
219 | AHBPR-=1; | |
|
220 | AHBPR|=0x4; | |
|
221 | } | |
|
222 | RCC->CFGR &= ~(0x7<<13); | |
|
223 | RCC->CFGR |= (uint32_t)(AHBPR<<13); | |
|
224 | FLASH->ACR |= FLASH_ACR_LATENCY_7WS; | |
|
225 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));//Switch to PLL as main clk source | |
|
226 | RCC->CFGR |= RCC_CFGR_SW_PLL; | |
|
227 | /* Wait till the main PLL is used as system clock source */ | |
|
228 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); | |
|
229 | if(srcfreq>150000000) | |
|
230 | { | |
|
231 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_5WS; | |
|
232 | } | |
|
233 | if((srcfreq<150000000) && (srcfreq>=120000000)) | |
|
234 | { | |
|
235 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_4WS; | |
|
236 | } | |
|
237 | if((srcfreq<120000000) && (srcfreq>=90000000)) | |
|
238 | { | |
|
239 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_3WS; | |
|
240 | } | |
|
241 | if((srcfreq<90000000) && (srcfreq>=60000000)) | |
|
242 | { | |
|
243 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_2WS; | |
|
244 | } | |
|
245 | if((srcfreq<60000000) && (srcfreq>=30000000)) | |
|
246 | { | |
|
247 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_1WS; | |
|
248 | } | |
|
249 | if(srcfreq<30000000) | |
|
250 | { | |
|
251 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_0WS; | |
|
252 | } | |
|
253 | return srcfreq; | |
|
254 | } | |
|
255 | ||
|
256 | int setCpuFreq(uint32_t freq) | |
|
257 | { | |
|
258 | extern uint32_t OSC0; | |
|
259 | extern uint32_t INTOSC; | |
|
260 | uint8_t i=0; | |
|
261 | uint32_t curentFeq = getCpuFreq(); | |
|
262 | if(curentFeq==freq)return curentFeq; | |
|
263 | if((freq>2000000) && (freq<=250000000)) //be carefull with 250MHz!!! | |
|
264 | { | |
|
265 | if((RCC->CFGR & 0xC) == 8) //PLL used as sys clk | |
|
266 | { | |
|
267 | return setPll(freq); | |
|
268 | } | |
|
269 | else if((RCC->CFGR & 0xC) == 0) //HSI used as sys clk | |
|
270 | { | |
|
271 | if((INTOSC%freq)==0) //now check if we can directly divide HSI | |
|
272 | { | |
|
273 | if(freq==INTOSC) | |
|
274 | { | |
|
275 | RCC->CFGR &= ~(0xF<<4); | |
|
276 | return freq; | |
|
277 | } | |
|
278 | for(i=1;i<8;i++) | |
|
279 | { | |
|
280 | if((freq<<i)==INTOSC) | |
|
281 | { | |
|
282 | RCC->CFGR &= ~(0xF<<4); | |
|
283 | RCC->CFGR |= ((0x8|i)<<4); | |
|
284 | return freq; | |
|
285 | } | |
|
286 | } | |
|
287 | } | |
|
288 | else | |
|
289 | return setPll(freq); | |
|
290 | } | |
|
291 | else //HSE used as sys clk | |
|
292 | { | |
|
293 | if((OSC0%freq)==0) //now check if we can directly divide HSI | |
|
294 | { | |
|
295 | if(freq==OSC0) | |
|
296 | { | |
|
297 | RCC->CFGR &= ~(0xF<<4); | |
|
298 | return freq; | |
|
299 | } | |
|
300 | for(i=1;i<8;i++) | |
|
301 | { | |
|
302 | if((freq<<i)==OSC0) | |
|
303 | { | |
|
304 | RCC->CFGR &= ~(0xF<<4); | |
|
305 | RCC->CFGR |= ((0x8|i)<<4); | |
|
306 | return freq; | |
|
307 | } | |
|
308 | } | |
|
309 | } | |
|
310 | else | |
|
311 | return setPll(freq); | |
|
312 | } | |
|
313 | } | |
|
314 | return 0; | |
|
315 | } | |
|
316 | ||
|
317 | ||
|
318 | void enable_FPU() | |
|
319 | { | |
|
320 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ | |
|
321 | __asm__("dsb"); | |
|
322 | __asm__("isb"); | |
|
43 | 323 | } |
|
44 | 324 | |
|
45 | 325 | |
@@ -47,13 +327,3 unsigned int coregetCpuFreq() | |||
|
47 | 327 | |
|
48 | 328 | |
|
49 | 329 | |
|
50 | ||
|
51 | ||
|
52 | ||
|
53 | ||
|
54 | ||
|
55 | ||
|
56 | ||
|
57 | ||
|
58 | ||
|
59 |
@@ -4,288 +4,10 | |||
|
4 | 4 | #include <stdio.h> |
|
5 | 5 | #include <bsp.h> |
|
6 | 6 | #include <stm32f4xx_rcc.h> |
|
7 | ||
|
8 | void reset_AHB1() | |
|
9 | { | |
|
10 | RCC->AHB1RSTR = -1; | |
|
11 | RCC->AHB1RSTR = 0; | |
|
12 | } | |
|
13 | ||
|
14 | void reset_AHB2() | |
|
15 | { | |
|
16 | RCC->AHB2RSTR = -1; | |
|
17 | RCC->AHB2RSTR = 0; | |
|
18 | } | |
|
19 | ||
|
20 | void reset_APB1() | |
|
21 | { | |
|
22 | RCC->APB1RSTR = -1; | |
|
23 | RCC->APB1RSTR = 0; | |
|
24 | } | |
|
25 | ||
|
26 | void reset_APB2() | |
|
27 | { | |
|
28 | RCC->APB2RSTR = -1; | |
|
29 | RCC->APB2RSTR = 0; | |
|
30 | } | |
|
31 | ||
|
32 | ||
|
33 | ||
|
34 | uint32_t getCpuFreq() | |
|
35 | { | |
|
36 | extern uint32_t OSC0; | |
|
37 | extern uint32_t INTOSC; | |
|
38 | uint32_t cpufreq = OSC0; | |
|
39 | uint32_t PLLN,PLLM,PLLP; | |
|
40 | ||
|
41 | if((RCC->CFGR & 0xC) == 8) //PLL used as sys clk | |
|
42 | { | |
|
43 | uint32_t pllinput=INTOSC; | |
|
44 | if((RCC->PLLCFGR & (1<<22)) == (1<<22)) | |
|
45 | { | |
|
46 | pllinput=OSC0; | |
|
47 | } | |
|
48 | PLLN = (RCC->PLLCFGR>>6) & 0x1FF; | |
|
49 | PLLM = RCC->PLLCFGR & 0x3F; | |
|
50 | PLLP = 1<<(((RCC->PLLCFGR>>16) & 3 )+1); | |
|
51 | cpufreq = (pllinput * PLLN )/(PLLM*PLLP); | |
|
52 | } | |
|
53 | else if((RCC->CFGR & 0xC) == 0) //HSI used as sys clk | |
|
54 | { | |
|
55 | cpufreq=INTOSC; | |
|
56 | } | |
|
57 | if((RCC->CFGR & (1<<7))==1<<7) | |
|
58 | { | |
|
59 | return cpufreq>>((RCC->CFGR & (7<<4))>>4); | |
|
60 | } | |
|
61 | return cpufreq; | |
|
62 | } | |
|
63 | ||
|
64 | ||
|
65 | /* | |
|
66 | | 2.7->3.6V | |
|
67 | ------------------------- | |
|
68 | 0WS | 0<HCLK<=30 | |
|
69 | 1WS | 30<HCLK<=60 | |
|
70 | 2WS | 60<HCLK<=90 | |
|
71 | 3WS | 90<HCLK<=120 | |
|
72 | 4WS | 120<HCLK<=150 | |
|
73 | 5WS | 150<HCLK<=168 | |
|
74 | ||
|
75 | f(VCO clock) = f(PLL clock input) × (PLLN / PLLM) [1] | |
|
76 | 64MHz <= f(VCO clock) <= 432MHz [2] | |
|
77 | ||
|
78 | f(VCO clock input) must be between 1MHz and 2MHz and as close to 2MHz as possible!! [3] | |
|
79 | ||
|
80 | f(PLL general clock output) = f(VCO clock) / PLLP [4] | |
|
81 | ||
|
82 | CPU<168MHz AHB1<168MHz AHB2<168MHz APB1<42MHz APB2<84MHz [5] | |
|
83 | ||
|
84 | ! 63<=PLLN<=432 [6] | |
|
85 | ! 2<=PLLM<=63 [7] | |
|
86 | ! PLLP=2,4,6,8 [8] | |
|
87 | 4<=PLLM*PLLP<=504 | |
|
88 | ||
|
89 | F= f(PLL clock input) * A/B with | |
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90 | 63<=A<=432 | |
|
91 | 4<=B<=504 | |
|
92 | ||
|
93 | */ | |
|
94 | ||
|
95 | ||
|
96 | int optimizePLLcfg(uint32_t freq, uint32_t srcfreq,uint32_t PLLM,uint32_t* PLLP, uint32_t* PLLN,uint8_t* AHBPRindx) | |
|
97 | { | |
|
98 | uint32_t AHBPRtbl[9]={1,2,4,8,16,64,128,256,512}; | |
|
99 | uint32_t AHBPR=0,AHBPR_r=0,PLLN_r=0,PLLP_r=0; | |
|
100 | uint32_t Fplli=0; | |
|
101 | int32_t f_error=100000000; | |
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102 | int32_t f_errornw=100000000; | |
|
103 | Fplli = srcfreq / PLLM; | |
|
104 | //not efficient but should find the best parameters | |
|
105 | for((*AHBPRindx)=0;(*AHBPRindx)<9;(*AHBPRindx)++) //lowest priority | |
|
106 | { | |
|
107 | AHBPR = AHBPRtbl[(*AHBPRindx)]; | |
|
108 | for(*PLLP=2;*PLLP<9;*PLLP+=2) | |
|
109 | { | |
|
110 | *PLLN = (freq*(*PLLP)*AHBPR)/Fplli; | |
|
111 | if(((*PLLN)>62) && ((*PLLN)<433) && ((Fplli * (*PLLN)) < 433000000)) | |
|
112 | { | |
|
113 | f_errornw = abs((int32_t)((int32_t)((Fplli*(*PLLN))/((*PLLP)*AHBPR))-freq)); | |
|
114 | if( ( (f_error)>(f_errornw) ) || ( (*AHBPRindx==0)&&(*PLLP==2)&&(*PLLN==63) ) ) | |
|
115 | { | |
|
116 | f_error=f_errornw; | |
|
117 | PLLN_r = *PLLN; | |
|
118 | PLLP_r = *PLLP; | |
|
119 | AHBPR_r=*AHBPRindx; | |
|
120 | if(f_error==0) | |
|
121 | { | |
|
122 | *PLLN = PLLN_r; | |
|
123 | *PLLP = PLLP_r; | |
|
124 | *AHBPRindx = AHBPR_r; | |
|
125 | return 1; | |
|
126 | } | |
|
127 | } | |
|
128 | } | |
|
129 | } | |
|
130 | } | |
|
131 | *PLLN = PLLN_r; | |
|
132 | *PLLP = PLLP_r; | |
|
133 | *AHBPRindx = AHBPR_r; | |
|
134 | return 1; | |
|
135 | } | |
|
7 | #include <core.h> | |
|
8 | extern int main(); | |
|
136 | 9 | |
|
137 | 10 | |
|
138 | int setPll(uint32_t freq) | |
|
139 | { | |
|
140 | extern uint32_t OSC0; | |
|
141 | extern uint32_t INTOSC; | |
|
142 | uint32_t srcfreq = INTOSC; | |
|
143 | uint8_t AHBPRindx; | |
|
144 | uint32_t AHBPRtbl[9]={1,2,4,8,16,64,128,256,512}; | |
|
145 | uint32_t PLLN=0,PLLM=0,PLLP=0,AHBPR=0; | |
|
146 | uint32_t Fplli=0; | |
|
147 | if((RCC->PLLCFGR & (1<<22))==(1<<22)) | |
|
148 | { | |
|
149 | srcfreq = OSC0; | |
|
150 | } | |
|
151 | PLLM = srcfreq / 1500000; // [3] | |
|
152 | Fplli = srcfreq / PLLM; | |
|
153 | optimizePLLcfg(freq,srcfreq,PLLM,&PLLP,&PLLN,&AHBPRindx); | |
|
154 | srcfreq = (Fplli*PLLN)/(PLLP*AHBPRtbl[AHBPRindx]); //Put real clk freq in srcfreq for return value | |
|
155 | //now switch to HSIs | |
|
156 | if((RCC->CR & 1)==0)RCC->CR |= 1; //turn ON HSI | |
|
157 | while((RCC->CR & 2)!=2); //wait for HSI Ready | |
|
158 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); | |
|
159 | RCC->CFGR |= RCC_CFGR_SW_HSI; //set HSI as main clk | |
|
160 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_HSI); | |
|
161 | RCC->CR &= ~(1<<24); //Turn OFF PLL | |
|
162 | RCC->PLLCFGR &= ~0x37FFF; //clear PLLP PLLM PLLN | |
|
163 | RCC->PLLCFGR |= PLLM + (PLLN<<6) + (((PLLP>>1) -1)<<16); | |
|
164 | RCC->CR |= RCC_CR_PLLON; //Turn ON PLL | |
|
165 | while((RCC->CR & (1<<25))!=(1<<25)); //wait for PLL Ready | |
|
166 | if(AHBPRindx!=0)AHBPRindx|=0x8; | |
|
167 | RCC->CFGR &= ~(0xF<<4); | |
|
168 | RCC->CFGR |= (uint32_t)(AHBPRindx<<4); | |
|
169 | AHBPR=0; | |
|
170 | while((srcfreq>>AHBPR)>42000000)AHBPR++; //[5] //Thune APB1 prescaler to keep APB1 CLK below 42MHz | |
|
171 | if(AHBPR!=0) | |
|
172 | { | |
|
173 | AHBPR-=1; | |
|
174 | AHBPR|=0x4; | |
|
175 | } | |
|
176 | RCC->CFGR &= ~(0x7<<10); | |
|
177 | RCC->CFGR |= (uint32_t)(AHBPR<<10); | |
|
178 | AHBPR=0; | |
|
179 | while((srcfreq>>AHBPR)>84000000)AHBPR++; //[5] //Thune APB2 prescaler to keep APB2 CLK below 42MHz | |
|
180 | if(AHBPR!=0) | |
|
181 | { | |
|
182 | AHBPR-=1; | |
|
183 | AHBPR|=0x4; | |
|
184 | } | |
|
185 | RCC->CFGR &= ~(0x7<<13); | |
|
186 | RCC->CFGR |= (uint32_t)(AHBPR<<13); | |
|
187 | FLASH->ACR |= FLASH_ACR_LATENCY_7WS; | |
|
188 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));//Switch to PLL as main clk source | |
|
189 | RCC->CFGR |= RCC_CFGR_SW_PLL; | |
|
190 | /* Wait till the main PLL is used as system clock source */ | |
|
191 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); | |
|
192 | if(srcfreq>150000000) | |
|
193 | { | |
|
194 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_5WS; | |
|
195 | } | |
|
196 | if((srcfreq<150000000) && (srcfreq>=120000000)) | |
|
197 | { | |
|
198 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_4WS; | |
|
199 | } | |
|
200 | if((srcfreq<120000000) && (srcfreq>=90000000)) | |
|
201 | { | |
|
202 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_3WS; | |
|
203 | } | |
|
204 | if((srcfreq<90000000) && (srcfreq>=60000000)) | |
|
205 | { | |
|
206 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_2WS; | |
|
207 | } | |
|
208 | if((srcfreq<60000000) && (srcfreq>=30000000)) | |
|
209 | { | |
|
210 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_1WS; | |
|
211 | } | |
|
212 | if(srcfreq<30000000) | |
|
213 | { | |
|
214 | FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_0WS; | |
|
215 | } | |
|
216 | return srcfreq; | |
|
217 | } | |
|
218 | ||
|
219 | int setCpuFreq(uint32_t freq) | |
|
220 | { | |
|
221 | extern uint32_t OSC0; | |
|
222 | extern uint32_t INTOSC; | |
|
223 | uint8_t i=0; | |
|
224 | uint32_t curentFeq = getCpuFreq(); | |
|
225 | if(curentFeq==freq)return curentFeq; | |
|
226 | if((freq>2000000) && (freq<=250000000)) //be carefull with 250MHz!!! | |
|
227 | { | |
|
228 | if((RCC->CFGR & 0xC) == 8) //PLL used as sys clk | |
|
229 | { | |
|
230 | return setPll(freq); | |
|
231 | } | |
|
232 | else if((RCC->CFGR & 0xC) == 0) //HSI used as sys clk | |
|
233 | { | |
|
234 | if((INTOSC%freq)==0) //now check if we can directly divide HSI | |
|
235 | { | |
|
236 | if(freq==INTOSC) | |
|
237 | { | |
|
238 | RCC->CFGR &= ~(0xF<<4); | |
|
239 | return freq; | |
|
240 | } | |
|
241 | for(i=1;i<8;i++) | |
|
242 | { | |
|
243 | if((freq<<i)==INTOSC) | |
|
244 | { | |
|
245 | RCC->CFGR &= ~(0xF<<4); | |
|
246 | RCC->CFGR |= ((0x8|i)<<4); | |
|
247 | return freq; | |
|
248 | } | |
|
249 | } | |
|
250 | } | |
|
251 | else | |
|
252 | return setPll(freq); | |
|
253 | } | |
|
254 | else //HSE used as sys clk | |
|
255 | { | |
|
256 | if((OSC0%freq)==0) //now check if we can directly divide HSI | |
|
257 | { | |
|
258 | if(freq==OSC0) | |
|
259 | { | |
|
260 | RCC->CFGR &= ~(0xF<<4); | |
|
261 | return freq; | |
|
262 | } | |
|
263 | for(i=1;i<8;i++) | |
|
264 | { | |
|
265 | if((freq<<i)==OSC0) | |
|
266 | { | |
|
267 | RCC->CFGR &= ~(0xF<<4); | |
|
268 | RCC->CFGR |= ((0x8|i)<<4); | |
|
269 | return freq; | |
|
270 | } | |
|
271 | } | |
|
272 | } | |
|
273 | else | |
|
274 | return setPll(freq); | |
|
275 | } | |
|
276 | } | |
|
277 | return 0; | |
|
278 | } | |
|
279 | ||
|
280 | #include <stdio.h> | |
|
281 | extern int main(); | |
|
282 | ||
|
283 | inline void enable_FPU() | |
|
284 | { | |
|
285 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ | |
|
286 | __asm__("dsb"); | |
|
287 | __asm__("isb"); | |
|
288 | } | |
|
289 | 11 | |
|
290 | 12 | void cpu_init() |
|
291 | 13 | { |
@@ -165,7 +165,7 int uartsetpins(uart_t* uart,uint32_t TX | |||
|
165 | 165 | break; |
|
166 | 166 | } |
|
167 | 167 | GPIO_PinAFConfig(GPIOGETPORT(TX), (uint8_t)(TX & 0xF), gpioAFuartx); |
|
168 |
GPIO_PinAFConfig(GPIOGETPORT( |
|
|
168 | GPIO_PinAFConfig(GPIOGETPORT(RX), (uint8_t)(RX & 0xF), gpioAFuartx); | |
|
169 | 169 | if((gpioAFuartx!=GPIO_AF_UART5) && (gpioAFuartx!=GPIO_AF_UART4)) |
|
170 | 170 | { |
|
171 | 171 | if(CTSpin!=-1) |
@@ -4,7 +4,8 SUBDIRS = CORE/core.pro \ | |||
|
4 | 4 | CPU/cpu.pro \ |
|
5 | 5 | GPIO/gpio.pro \ |
|
6 | 6 | UART/uart.pro \ |
|
7 | SPI/spi.pro | |
|
7 | SPI/spi.pro \ | |
|
8 | I2C/i2c.pro | |
|
8 | 9 | |
|
9 | 10 | |
|
10 | 11 |
@@ -8,7 +8,6 INCLUDEPATH += $$LIBUC_LIBS_DIR/includes | |||
|
8 | 8 | |
|
9 | 9 | LIBUC_BIN_LIBS_DIR = $$LIBUC_LIBS_DIR/bin/$$ARCH |
|
10 | 10 | |
|
11 | ||
|
12 | 11 | LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ |
|
13 | 12 | -lsdcard |
|
14 | 13 | |
@@ -22,6 +21,9 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ | |||
|
22 | 21 | -luart |
|
23 | 22 | |
|
24 | 23 | LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ |
|
24 | -li2c | |
|
25 | ||
|
26 | LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ | |
|
25 | 27 | -lgpio |
|
26 | 28 | |
|
27 | 29 | LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ |
@@ -30,6 +32,9 LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ | |||
|
30 | 32 | LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ |
|
31 | 33 | -lcpu |
|
32 | 34 | |
|
35 | LIBS += -L$$LIBUC_LIBS_DIR/bin/$$ARCH \ | |
|
36 | -lcore | |
|
37 | ||
|
33 | 38 | |
|
34 | 39 | |
|
35 | 40 |
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