HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · designs/Validation_MS_auto/data_read_with_timer.vhd

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.

pellion - - Load All Authors

File last commit:

r544:7527baf4377d JC


                r655:2dbcdaf8bb73

tip default

Download file

             data_read_with_timer.vhd
        
                    74 lines
            
             | 1.9 KiB
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / designs / Validation_MS_auto / data_read_with_timer.vhd
          
                    History
                
                 |
                  Annotation
                 | Raw
                 |Copy content
                 |Copy permalink

      LIBRARY ieee;

      USE ieee.std_logic_1164.ALL;

      USE IEEE.MATH_REAL.ALL;

      USE ieee.numeric_std.ALL;

      LIBRARY std;

      use std.textio.all;

      ENTITY data_read_with_timer IS

        GENERIC (

          input_file_name  : STRING := "input_data_2.txt";

          NB_CHAR_PER_DATA : INTEGER := 4;

          NB_CYCLE_TIMER   : INTEGER := 1024

          );

        PORT (

          clk           : IN STD_LOGIC;

          rstn          : IN STD_LOGIC;

          end_of_file   : OUT STD_LOGIC;

          data_out_val  : OUT STD_LOGIC;

          data_out      : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0)

          );

      END;

      ARCHITECTURE beh OF data_read_with_timer IS

        COMPONENT data_read

          GENERIC (

            input_file_name  : STRING;

            NB_CHAR_PER_DATA : INTEGER);

          PORT (

            clk           : IN  STD_LOGIC;

            read_new_data : IN  STD_LOGIC;

            end_of_file   : OUT STD_LOGIC;

            data_out_val  : OUT STD_LOGIC;

            data_out      : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0));

        END COMPONENT;

        SIGNAL nb_cycle_counter : INTEGER;

        SIGNAL read_new_data : STD_LOGIC;

      BEGIN  -- beh

        PROCESS (clk, rstn)

        BEGIN  -- PROCESS

          IF rstn = '0' THEN                  -- asynchronous reset (active low)

            nb_cycle_counter <= 0;

            read_new_data    <= '0';

          ELSIF clk'event AND clk = '1' THEN  -- rising clock edge

            IF nb_cycle_counter < NB_CYCLE_TIMER-1 THEN

              nb_cycle_counter <= nb_cycle_counter + 1;

              read_new_data    <= '0';

            ELSE

              nb_cycle_counter <= 0;

              read_new_data <= '1';

            END IF;      

          END IF;

        END PROCESS;

        data_read_1: data_read

          GENERIC MAP (

            input_file_name  => input_file_name,

            NB_CHAR_PER_DATA => NB_CHAR_PER_DATA)

          PORT MAP (

            clk           => clk,

            read_new_data => read_new_data,

            end_of_file   => end_of_file,

            data_out_val  => data_out_val,

            data_out      => data_out);

      END beh;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages


				LIBRARY ieee;
				USE ieee.std_logic_1164.ALL;
				USE IEEE.MATH_REAL.ALL;
				USE ieee.numeric_std.ALL;

				LIBRARY std;
				use std.textio.all;

				ENTITY data_read_with_timer IS
				GENERIC (
				input_file_name : STRING := "input_data_2.txt";
				NB_CHAR_PER_DATA : INTEGER := 4;
				NB_CYCLE_TIMER : INTEGER := 1024
				);
				PORT (
				clk : IN STD_LOGIC;
				rstn : IN STD_LOGIC;

				end_of_file : OUT STD_LOGIC;

				data_out_val : OUT STD_LOGIC;
				data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0)
				);
				END;

				ARCHITECTURE beh OF data_read_with_timer IS

				COMPONENT data_read
				GENERIC (
				input_file_name : STRING;
				NB_CHAR_PER_DATA : INTEGER);
				PORT (
				clk : IN STD_LOGIC;
				read_new_data : IN STD_LOGIC;
				end_of_file : OUT STD_LOGIC;
				data_out_val : OUT STD_LOGIC;
				data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0));
				END COMPONENT;

				SIGNAL nb_cycle_counter : INTEGER;
				SIGNAL read_new_data : STD_LOGIC;

				BEGIN -- beh

				PROCESS (clk, rstn)
				BEGIN -- PROCESS
				IF rstn = '0' THEN -- asynchronous reset (active low)
				nb_cycle_counter <= 0;
				read_new_data <= '0';
				ELSIF clk'event AND clk = '1' THEN -- rising clock edge
				IF nb_cycle_counter < NB_CYCLE_TIMER-1 THEN
				nb_cycle_counter <= nb_cycle_counter + 1;
				read_new_data <= '0';
				ELSE
				nb_cycle_counter <= 0;
				read_new_data <= '1';
				END IF;
				END IF;
				END PROCESS;


				data_read_1: data_read
				GENERIC MAP (
				input_file_name => input_file_name,
				NB_CHAR_PER_DATA => NB_CHAR_PER_DATA)
				PORT MAP (
				clk => clk,
				read_new_data => read_new_data,
				end_of_file => end_of_file,
				data_out_val => data_out_val,
				data_out => data_out);

				END beh;