##// END OF EJS Templates
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.

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r629:24d5a378ec74 simu_with_Leon3
r655:2dbcdaf8bb73 tip default
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Makefile
55 lines | 1.3 KiB | text/x-makefile | MakefileLexer
VHDLIB=../..
SCRIPTSDIR=$(VHDLIB)/scripts/
GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
TOP=LFR_EQM
BOARD=LFR-EQM
include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
EFFORT=high
XSTOPT=
VHDLSYNFILES=LFR-EQM.vhd
VHDLSIMFILES=testbench.vhd
PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
CLEAN=soft-clean
TECHLIBS = axcelerator
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX
DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
./amba_lcd_16x2_ctrlr \
./general_purpose/lpp_AMR \
./general_purpose/lpp_balise \
./general_purpose/lpp_delay \
./lpp_bootloader \
./dsp/lpp_fft \
./lpp_uart \
./lpp_usb \
./lpp_sim/CY7C1061DV33 \
FILESKIP = i2cmst.vhd \
APB_MULTI_DIODE.vhd \
APB_MULTI_DIODE.vhd \
Top_MatrixSpec.vhd \
APB_FFT.vhd\
CoreFFT_simu.vhd \
lpp_lfr_apbreg_simu.vhd \
sgmii.vhd
include $(GRLIB)/bin/Makefile
include $(GRLIB)/software/leon3/Makefile
################## project specific targets ##########################