HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · designs/EGSE_ICI/DC_GATE_GEN.vhd

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.

Alexis Jeandet - - Load All Authors

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             DC_GATE_GEN.vhd
        
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      -- DC_GATE_GEN.vhd

      library IEEE;

      use IEEE.std_logic_1164.all;

      use IEEE.numeric_std.all;

      entity DC_GATE_GEN is

      generic(WordCnt   :   integer := 144);

      port

      (

          clk     :   in  std_logic;

          Wcount  :   in  integer range 0 to WordCnt-1;

          Gate    :   out std_logic

      );

      end entity;

      architecture ar_DC_GATE_GEN of DC_GATE_GEN is

      begin

      process(clk)

          begin

              if clk'event and clk ='0' then

                      case Wcount is

                          when 48 =>

                              gate <= '1';

                          when 49 =>

                              gate <= '1';

                          when 50 =>

                              gate <= '1';

                          when 51 =>

                              gate <= '1';

                          when 52 =>

                              gate <= '1';

                          when 53 =>

                              gate <= '1';

                          when others =>

                              gate <= '0';

                      end case;

              end if;

      end process;

      end architecture;

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				-- DC_GATE_GEN.vhd
				library IEEE;
				use IEEE.std_logic_1164.all;
				use IEEE.numeric_std.all;








				entity DC_GATE_GEN is
				generic(WordCnt : integer := 144);
				port
				(
				clk : in std_logic;
				Wcount : in integer range 0 to WordCnt-1;
				Gate : out std_logic
				);
				end entity;




				architecture ar_DC_GATE_GEN of DC_GATE_GEN is
				begin
				process(clk)
				begin
				if clk'event and clk ='0' then
				case Wcount is
				when 48 =>
				gate <= '1';
				when 49 =>
				gate <= '1';

				when 50 =>
				gate <= '1';
				when 51 =>
				gate <= '1';

				when 52 =>
				gate <= '1';
				when 53 =>
				gate <= '1';


				when others =>
				gate <= '0';
				end case;
				end if;
				end process;
				end architecture;