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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : Jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.general_purpose.ALL;
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ENTITY MUXN IS
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GENERIC(
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Input_SZ : INTEGER := 16;
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NbStage : INTEGER := 2);
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PORT(
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sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
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--INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
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INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
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RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
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END ENTITY;
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ARCHITECTURE ar_MUXN OF MUXN IS
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COMPONENT MUXN
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GENERIC (
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Input_SZ : INTEGER;
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NbStage : INTEGER);
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PORT (
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sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
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INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
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--INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
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RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
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END COMPONENT;
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--SIGNAL S : ARRAY (0 TO (2**(NbStage-1)-1)) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
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SIGNAL S: MUX_INPUT_TYPE(0 TO (2**(NbStage-1))-1,Input_SZ-1 DOWNTO 0);
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BEGIN
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all_input : FOR I IN 0 TO (2**(NbStage-1))-1 GENERATE
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all_input: FOR J IN Input_SZ-1 DOWNTO 0 GENERATE
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S(I,J) <= INPUT(2*I,J) WHEN sel(0) = '0' ELSE INPUT(2*I+1,J);
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END GENERATE all_input;
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END GENERATE all_input;
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NB_STAGE_1: IF NbStage = 1 GENERATE
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all_input: FOR J IN Input_SZ-1 DOWNTO 0 GENERATE
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RES(J) <= S(0,J);
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END GENERATE all_input;
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END GENERATE NB_STAGE_1;
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NB_STAGE_2 : IF NbStage = 2 GENERATE
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all_input: FOR I IN Input_SZ-1 DOWNTO 0 GENERATE
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RES(I) <= S(0,I) WHEN sel(1) = '0' ELSE S(1,I);
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END GENERATE all_input;
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END GENERATE NB_STAGE_2;
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NB_STAGE_PLUS : IF NbStage > 2 GENERATE
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MUXN_1 : MUXN
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GENERIC MAP (
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Input_SZ => Input_SZ,
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NbStage => NbStage-1)
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PORT MAP (
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sel => sel(NbStage-1 DOWNTO 1),
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INPUT => S,
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RES => RES);
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END GENERATE NB_STAGE_PLUS;
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END ar_MUXN;
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