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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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ENTITY HeaderBuilder IS
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GENERIC(
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Data_sz : INTEGER := 32);
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PORT(
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clkm : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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Statu : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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Matrix_Type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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Matrix_Write : IN STD_LOGIC;
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Valid : OUT STD_LOGIC;
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dataIN : IN STD_LOGIC_VECTOR((2*Data_sz)-1 DOWNTO 0);
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emptyIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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RenOUT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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dataOUT : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0);
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emptyOUT : OUT STD_LOGIC;
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RenIN : IN STD_LOGIC;
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header : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0);
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header_val : OUT STD_LOGIC;
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header_ack : IN STD_LOGIC
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);
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END ENTITY;
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ARCHITECTURE ar_HeaderBuilder OF HeaderBuilder IS
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SIGNAL Matrix_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL Write_reg : STD_LOGIC;
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SIGNAL Data_cpt : INTEGER;
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SIGNAL MAX : INTEGER;
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TYPE etat IS (idle0, idle1, pong0, pong1);
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SIGNAL ect : etat;
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BEGIN
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PROCESS (clkm, rstn)
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BEGIN
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IF(rstn = '0')then
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ect <= idle0;
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Valid <= '0';
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header_val <= '0';
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header(5 DOWNTO 0) <= (OTHERS => '0');
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Write_reg <= '0';
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Data_cpt <= 0;
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MAX <= 128;
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ELSIF(clkm' event AND clkm = '1')then
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Write_reg <= Matrix_Write;
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IF(Statu = "0001" OR Statu="0011" OR Statu="0110" OR Statu="1010" OR Statu="1111")THEN
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MAX <= 128;
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ELSE
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MAX <= 256;
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END IF;
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IF(Write_reg = '0' AND Matrix_Write = '1')THEN
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Data_cpt <= Data_cpt + 1;
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Valid <= '0';
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ELSIF(Data_cpt = MAX)THEN
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Data_cpt <= 0;
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Valid <= '1';
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header_val <= '1';
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ELSE
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Valid <= '0';
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END IF;
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CASE ect IS
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WHEN idle0 =>
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IF(header_ack = '1')THEN
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header_val <= '0';
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ect <= pong0;
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END IF;
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WHEN pong0 =>
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header(1 DOWNTO 0) <= Matrix_Type;
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header(5 DOWNTO 2) <= Matrix_Param;
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IF(emptyIN(0) = '1')THEN
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ect <= idle1;
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END IF;
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WHEN idle1 =>
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IF(header_ack = '1')THEN
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header_val <= '0';
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ect <= pong1;
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END IF;
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WHEN pong1 =>
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header(1 DOWNTO 0) <= Matrix_Type;
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header(5 DOWNTO 2) <= Matrix_Param;
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IF(emptyIN(1) = '1')THEN
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ect <= idle0;
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END IF;
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END CASE;
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END IF;
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END PROCESS;
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Matrix_Param <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(Statu))-1, 4));
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header(31 DOWNTO 6) <= (OTHERS => '0');
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WITH ect SELECT
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dataOUT <= dataIN(Data_sz-1 DOWNTO 0) WHEN pong0,
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dataIN(Data_sz-1 DOWNTO 0) WHEN idle0,
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dataIN((2*Data_sz)-1 DOWNTO Data_sz) WHEN pong1,
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dataIN((2*Data_sz)-1 DOWNTO Data_sz) WHEN idle1,
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(OTHERS => '0') WHEN OTHERS;
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WITH ect SELECT
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emptyOUT <= emptyIN(0) WHEN pong0,
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emptyIN(0) WHEN idle0,
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emptyIN(1) WHEN pong1,
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emptyIN(1) WHEN idle1,
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'1' WHEN OTHERS;
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WITH ect SELECT
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RenOUT <= '1' & RenIN WHEN pong0,
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'1' & RenIN WHEN idle0,
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RenIN & '1' WHEN pong1,
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RenIN & '1' WHEN idle1,
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"11" WHEN OTHERS;
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END ARCHITECTURE;
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