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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.general_purpose.ALL;
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--TODO
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--terminer le testbensh puis changer le resize dans les instanciations
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--par un resize sur un vecteur en combi
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ENTITY MAC IS
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GENERIC(
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Input_SZ_A : INTEGER := 8;
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Input_SZ_B : INTEGER := 8;
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COMP_EN : INTEGER := 0 -- 1 => No Comp
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);
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PORT(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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clr_MAC : IN STD_LOGIC;
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MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
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);
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END MAC;
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ARCHITECTURE ar_MAC OF MAC IS
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SIGNAL clr_MAC_s : STD_LOGIC;
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SIGNAL MAC_MUL_ADD_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL add, mult : STD_LOGIC;
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SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
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SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
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SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
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SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
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SIGNAL MACMUXsel : STD_LOGIC;
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SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
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SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
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SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
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SIGNAL MACMUX2sel : STD_LOGIC;
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SIGNAL add_D : STD_LOGIC;
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SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
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SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
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SIGNAL MACMUXsel_D : STD_LOGIC;
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SIGNAL MACMUX2sel_D : STD_LOGIC;
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SIGNAL MACMUX2sel_D_D : STD_LOGIC;
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SIGNAL clr_MAC_D : STD_LOGIC;
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-- SIGNAL clr_MAC_D_D : STD_LOGIC;
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-- SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
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-- SIGNAL load_mult_result : STD_LOGIC;
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-- SIGNAL load_mult_result_D : STD_LOGIC;
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BEGIN
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--==============================================================
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--=============M A C C O N T R O L E R=========================
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--==============================================================
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MAC_CONTROLER1 : MAC_CONTROLER
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PORT MAP(
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ctrl => MAC_MUL_ADD_s,
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MULT => mult,
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ADD => add,
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--LOAD_ADDER => load_mult_result,
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MACMUX_sel => MACMUXsel,
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MACMUX2_sel => MACMUX2sel
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);
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--==============================================================
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--==============================================================
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--=============M U L T I P L I E R==============================
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--==============================================================
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Multiplieri_nst : Multiplier
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GENERIC MAP(
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Input_SZ_A => Input_SZ_A,
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Input_SZ_B => Input_SZ_B
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)
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PORT MAP(
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clk => clk,
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reset => reset,
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mult => mult,
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OP1 => OP1_2C,
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OP2 => OP2_2C,
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RES => MULTout
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);
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--==============================================================
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--PROCESS (clk, reset)
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--BEGIN -- PROCESS
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-- IF reset = '0' THEN -- asynchronous reset (active low)
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-- load_mult_result_D <= '0';
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-- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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-- load_mult_result_D <= load_mult_result;
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-- END IF;
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--END PROCESS;
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--==============================================================
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--======================A D D E R ==============================
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--==============================================================
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adder_inst : Adder
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GENERIC MAP(
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Input_SZ_A => Input_SZ_A+Input_SZ_B,
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Input_SZ_B => Input_SZ_A+Input_SZ_B
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)
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PORT MAP(
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clk => clk,
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reset => reset,
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clr => clr_MAC_D,
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load => MACMUX2sel_D, --load_mult_result_D,
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add => add_D,
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OP1 => ADDERinA,
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OP2 => ADDERinB,
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RES => ADDERout
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);
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--==============================================================
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--===================TWO COMPLEMENTERS==========================
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--==============================================================
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gen_comp : IF COMP_EN = 0 GENERATE
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TWO_COMPLEMENTER1 : TwoComplementer
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GENERIC MAP(
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Input_SZ => Input_SZ_A
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)
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PORT MAP(
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clk => clk,
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reset => reset,
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clr => '0', --clr_MAC,
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TwoComp => Comp_2C(0),
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OP => OP1,
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RES => OP1_2C
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);
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TWO_COMPLEMENTER2 : TwoComplementer
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GENERIC MAP(
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Input_SZ => Input_SZ_B
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)
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PORT MAP(
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clk => clk,
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reset => reset,
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clr => '0', --clr_MAC,
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TwoComp => Comp_2C(1),
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OP => OP2,
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RES => OP2_2C
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);
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clr_MACREG_comp : MAC_REG
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GENERIC MAP(size => 1)
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PORT MAP(
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reset => reset,
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clk => clk,
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D(0) => clr_MAC,
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Q(0) => clr_MAC_s
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);
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MAC_MUL_ADD_REG : MAC_REG
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GENERIC MAP(size => 2)
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PORT MAP(
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reset => reset,
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clk => clk,
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D => MAC_MUL_ADD,
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Q => MAC_MUL_ADD_s
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);
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END GENERATE gen_comp;
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no_gen_comp : IF COMP_EN = 1 GENERATE
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OP2_2C <= OP2;
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OP1_2C <= OP1;
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clr_MAC_s <= clr_MAC;
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MAC_MUL_ADD_s <= MAC_MUL_ADD;
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END GENERATE no_gen_comp;
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--==============================================================
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clr_MACREG1 : MAC_REG
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GENERIC MAP(size => 1)
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PORT MAP(
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reset => reset,
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clk => clk,
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D(0) => clr_MAC_s,
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Q(0) => clr_MAC_D
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);
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addREG : MAC_REG
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GENERIC MAP(size => 1)
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PORT MAP(
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reset => reset,
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clk => clk,
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D(0) => add,
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Q(0) => add_D
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);
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OP1REG : MAC_REG
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GENERIC MAP(size => Input_SZ_A)
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PORT MAP(
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reset => reset,
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clk => clk,
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D => OP1_2C,
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Q => OP1_2C_D
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);
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OP2REG : MAC_REG
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GENERIC MAP(size => Input_SZ_B)
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PORT MAP(
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reset => reset,
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clk => clk,
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D => OP2_2C,
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Q => OP2_2C_D
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);
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MULToutREG : MAC_REG
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GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
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PORT MAP(
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reset => reset,
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clk => clk,
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D => MULTout,
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Q => MULTout_D
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);
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MACMUXselREG : MAC_REG
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GENERIC MAP(size => 1)
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PORT MAP(
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reset => reset,
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clk => clk,
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D(0) => MACMUXsel,
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Q(0) => MACMUXsel_D
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);
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MACMUX2selREG : MAC_REG
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GENERIC MAP(size => 1)
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PORT MAP(
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reset => reset,
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clk => clk,
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D(0) => MACMUX2sel,
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Q(0) => MACMUX2sel_D
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);
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MACMUX2selREG2 : MAC_REG
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GENERIC MAP(size => 1)
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PORT MAP(
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reset => reset,
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clk => clk,
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D(0) => MACMUX2sel_D,
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Q(0) => MACMUX2sel_D_D
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);
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--==============================================================
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--======================M A C M U X ===========================
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--==============================================================
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MACMUX_inst : MAC_MUX
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GENERIC MAP(
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Input_SZ_A => Input_SZ_A+Input_SZ_B,
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Input_SZ_B => Input_SZ_A+Input_SZ_B
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)
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PORT MAP(
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sel => MACMUXsel_D,
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INA1 => ADDERout,
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INA2 => OP2_2C_D_Resz,
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INB1 => MULTout,
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INB2 => OP1_2C_D_Resz,
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OUTA => ADDERinA,
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OUTB => ADDERinB
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);
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OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B));
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OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B));
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--==============================================================
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--==============================================================
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--======================M A C M U X2 ==========================
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--==============================================================
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MAC_MUX2_inst : MAC_MUX2
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GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B)
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PORT MAP(
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sel => MACMUX2sel_D_D,
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RES2 => MULTout_D,
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RES1 => ADDERout,
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RES => RES
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);
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--==============================================================
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END ar_MAC;
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