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-----------------------------------------------------------------------------
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-- LEON3 Demonstration design test bench
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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------------------------------------------------------------------------------
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-- modified by Thomas Ameseder, Gleichmann Electronics 2004, 2005 to
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-- support the use of an external AHB slave and different HPE board versions
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------------------------------------------------------------------------------
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-- further adapted from Hpe_compact to Hpe_mini (Feb. 2005)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.sim.all;
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library techmap;
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use techmap.gencomp.all;
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library micron;
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use micron.components.all;
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use work.config.all; -- configuration
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use work.debug.all;
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use std.textio.all;
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library grlib;
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use grlib.stdlib.all;
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use grlib.stdio.all;
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use grlib.devices.all;
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entity testbench is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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clkperiod : integer := 20; -- system clock period
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romwidth : integer := 16; -- rom data width (8/32)
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romdepth : integer := 16; -- rom address depth
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sramwidth : integer := 32; -- ram data width (8/16/32)
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sramdepth : integer := 18; -- ram address depth
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srambanks : integer := 2 -- number of ram banks
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);
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end;
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architecture behav of testbench is
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constant promfile : string := "prom.srec"; -- rom contents
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constant sdramfile : string := "sdram.srec"; -- sdram contents
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signal clk : std_logic := '0';
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signal Rst : std_logic := '0'; -- Reset
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constant ct : integer := clkperiod/2;
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signal address : std_logic_vector(23 downto 0);
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signal data : std_logic_vector(31 downto 0);
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signal romsn : std_logic_vector(1 downto 0);
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signal oen : std_ulogic;
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signal writen : std_ulogic;
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signal iosn : std_ulogic;
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-- ddr memory
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signal ddr_clk : std_logic;
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signal ddr_clkb : std_logic;
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signal ddr_clk_fb : std_logic;
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signal ddr_cke : std_logic;
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signal ddr_csb : std_logic;
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signal ddr_web : std_ulogic; -- ddr write enable
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signal ddr_rasb : std_ulogic; -- ddr ras
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signal ddr_casb : std_ulogic; -- ddr cas
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signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
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signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
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signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
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signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
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signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
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signal brdyn : std_ulogic;
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signal bexcn : std_ulogic;
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signal wdog : std_ulogic;
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signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
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signal dsurst : std_ulogic;
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signal test : std_ulogic;
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signal rtsn, ctsn : std_ulogic;
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signal error : std_logic;
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signal pio : std_logic_vector(15 downto 0);
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signal GND : std_ulogic := '0';
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signal VCC : std_ulogic := '1';
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signal NC : std_ulogic := 'Z';
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signal clk2 : std_ulogic := '1';
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signal plllock : std_ulogic;
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-- pulled up high, therefore std_logic
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signal txd, rxd1 : std_logic;
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signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
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signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
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signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
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constant lresp : boolean := false;
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signal resoutn : std_logic;
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signal dsubren : std_ulogic;
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signal dsuactn : std_ulogic;
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begin
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dsubren <= not dsubre;
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-- clock and reset
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clk <= not clk after ct * 1 ns;
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rst <= '1', '0' after 100 ns;
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dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
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address(0) <= '0';
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ddr_dqs <= (others => 'L');
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d3 : entity work.leon3mp
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port map (
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reset => rst,
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clk_50mhz => clk,
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errorn => error,
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address => address(23 downto 0),
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data => data(31 downto 16),
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testdata => data(15 downto 0),
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ddr_clk0 => ddr_clk,
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ddr_clk0b => ddr_clkb,
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ddr_clk_fb => ddr_clk_fb,
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ddr_cke0 => ddr_cke,
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ddr_cs0b => ddr_csb,
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ddr_web => ddr_web,
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ddr_rasb => ddr_rasb,
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ddr_casb => ddr_casb,
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ddr_dm => ddr_dm,
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ddr_dqs => ddr_dqs,
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ddr_ad => ddr_ad,
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ddr_ba => ddr_ba,
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ddr_dq => ddr_dq,
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dsuen => dsuen,
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dsubre => dsubre,
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-- dsuact => dsuactn,
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dsutx => dsutx,
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dsurx => dsurx,
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oen => oen,
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writen => writen,
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iosn => iosn,
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romsn => romsn(0),
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utxd1 => txd,
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urxd1 => txd,
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emdio => emdio,
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etx_clk => etx_clk,
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erx_clk => erx_clk,
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erxd => erxd,
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erx_dv => erx_dv,
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erx_er => erx_er,
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erx_col => erx_col,
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erx_crs => erx_crs,
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etxd => etxd,
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etx_en => etx_en,
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etx_er => etx_er,
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emdc => emdc
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);
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ddr_clk_fb <= ddr_clk;
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u1 : mt46v16m16
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generic map (index => -1, fname => sdramfile)
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port map(
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Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
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Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
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Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
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Dm => ddr_dm(1 downto 0));
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prom0 : for i in 0 to (romwidth/8)-1 generate
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sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
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port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
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writen, oen);
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end generate;
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-- phy0 : if CFG_GRETH > 0 generate
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-- p0 : phy
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-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
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-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
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-- end generate;
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error <= 'H'; -- ERROR pull-up
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iuerr : process
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begin
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wait for 5 us;
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assert (to_X01(error) = '1')
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report "*** IU in error mode, simulation halted ***"
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severity failure;
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end process;
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test0 : grtestmod
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port map ( rst, clk, error, address(21 downto 2), data,
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iosn, oen, writen, brdyn);
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data <= buskeep(data) after 5 ns;
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dsucom : process
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procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
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variable w32 : std_logic_vector(31 downto 0);
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variable c8 : std_logic_vector(7 downto 0);
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constant txp : time := 160 * 1 ns;
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begin
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dsutx <= '1';
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dsurst <= '1';
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wait;
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wait for 5000 ns;
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txc(dsutx, 16#55#, txp); -- sync uart
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
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--
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
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--
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
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--
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
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--
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-- txc(dsutx, 16#80#, txp);
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
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-- rxi(dsurx, w32, txp, lresp);
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txc(dsutx, 16#a0#, txp);
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txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
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rxi(dsurx, w32, txp, lresp);
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end;
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begin
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dsucfg(dsutx, dsurx);
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wait;
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end process;
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end;
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