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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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use lpp.lpp_matrix.all;
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use lpp.general_purpose.all;
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--! Un MAC : Multiplier Accumulator Chip
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entity MAC_v2 is
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generic(
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Input_SZ_A : integer := 8;
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Input_SZ_B : integer := 8);
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port(
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clk : in std_logic; --! Horloge du composant
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reset : in std_logic; --! Reset general du composant
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clr_MAC : in std_logic; --! Un reset sp�cifique au programme
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MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0); --! Permet de s�lectionner la/les fonctionnalit� d�sir�
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OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); --! Premier Op�rande
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OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); --! Second Op�rande
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RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) --! R�sultat du MAC
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);
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end MAC_v2;
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architecture ar_MAC_v2 of MAC_v2 is
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signal add,mult : std_logic;
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signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
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signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
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signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
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signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
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signal MACMUXsel : std_logic;
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signal OP1_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
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signal OP2_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
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signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0);
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signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0);
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signal MACMUX2sel : std_logic;
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signal add_D : std_logic;
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signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0);
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signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0);
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signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
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signal MACMUXsel_D : std_logic;
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signal MACMUX2sel_D : std_logic;
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signal MACMUX2sel_D_D : std_logic;
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signal clr_MAC_D : std_logic;
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signal clr_MAC_D_D : std_logic;
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signal MAC_MUL_ADD_2C_D : std_logic_vector(3 downto 0);
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begin
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--==============================================================
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--=============M A C C O N T R O L E R=========================
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--==============================================================
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MAC_CONTROLER1 : MAC_CONTROLER
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port map(
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ctrl => MAC_MUL_ADD_2C_D(1 downto 0),
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MULT => mult,
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ADD => add,
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MACMUX_sel => MACMUXsel,
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MACMUX2_sel => MACMUX2sel
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);
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--==============================================================
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--==============================================================
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--=============M U L T I P L I E R==============================
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--==============================================================
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Multiplieri_nst : Multiplier
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generic map(
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Input_SZ_A => Input_SZ_A,
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Input_SZ_B => Input_SZ_B
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)
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port map(
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clk => clk,
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reset => reset,
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mult => mult,
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OP1 => OP1_2C,
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OP2 => OP2_2C,
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RES => MULTout
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);
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--==============================================================
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--==============================================================
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--======================A D D E R ==============================
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--==============================================================
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adder_inst : Adder
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generic map(
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Input_SZ_A => Input_SZ_A+Input_SZ_B,
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Input_SZ_B => Input_SZ_A+Input_SZ_B
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)
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port map(
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clk => clk,
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reset => reset,
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clr => clr_MAC_D_D,
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add => add_D,
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OP1 => ADDERinA,
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OP2 => ADDERinB,
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RES => ADDERout
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);
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--==============================================================
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--==============================================================
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--===================TWO COMPLEMENTERS==========================
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--==============================================================
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TWO_COMPLEMENTER1 : TwoComplementer
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generic map(
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Input_SZ => Input_SZ_A
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)
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port map(
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clk => clk,
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reset => reset,
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clr => clr_MAC,
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TwoComp => MAC_MUL_ADD_2C(2),
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OP => OP1,
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RES => OP1_2C
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);
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TWO_COMPLEMENTER2 : TwoComplementer
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generic map(
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Input_SZ => Input_SZ_B
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)
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port map(
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clk => clk,
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reset => reset,
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clr => clr_MAC,
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TwoComp => MAC_MUL_ADD_2C(3),
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OP => OP2,
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RES => OP2_2C
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);
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--==============================================================
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CTRL : MAC_REG
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generic map(size => 2)
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port map(
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reset => reset,
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clk => clk,
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D => MAC_MUL_ADD_2C(1 downto 0),
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Q => MAC_MUL_ADD_2C_D(1 downto 0)
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);
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clr_MACREG1 : MAC_REG
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generic map(size => 1)
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port map(
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reset => reset,
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clk => clk,
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D(0) => clr_MAC,
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Q(0) => clr_MAC_D
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);
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clr_MACREG2 : MAC_REG
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generic map(size => 1)
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port map(
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reset => reset,
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clk => clk,
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D(0) => clr_MAC_D,
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Q(0) => clr_MAC_D_D
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);
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addREG : MAC_REG
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generic map(size => 1)
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port map(
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reset => reset,
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clk => clk,
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D(0) => add,
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Q(0) => add_D
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);
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OP1REG : MAC_REG
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generic map(size => Input_SZ_A)
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port map(
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reset => reset,
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clk => clk,
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D => OP1_2C,
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Q => OP1_2C_D
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);
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OP2REG : MAC_REG
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generic map(size => Input_SZ_B)
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port map(
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reset => reset,
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clk => clk,
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D => OP2_2C,
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Q => OP2_2C_D
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);
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MULToutREG : MAC_REG
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generic map(size => Input_SZ_A+Input_SZ_B)
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port map(
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reset => reset,
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clk => clk,
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D => MULTout,
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Q => MULTout_D
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);
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MACMUXselREG : MAC_REG
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generic map(size => 1)
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port map(
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reset => reset,
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clk => clk,
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D(0) => MACMUXsel,
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Q(0) => MACMUXsel_D
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);
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MACMUX2selREG : MAC_REG
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generic map(size => 1)
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port map(
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reset => reset,
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clk => clk,
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D(0) => MACMUX2sel,
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Q(0) => MACMUX2sel_D
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);
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MACMUX2selREG2 : MAC_REG
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generic map(size => 1)
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port map(
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reset => reset,
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clk => clk,
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D(0) => MACMUX2sel_D,
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Q(0) => MACMUX2sel_D_D
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);
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--==============================================================
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--======================M A C M U X ===========================
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--==============================================================
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MACMUX_inst : MAC_MUX
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generic map(
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Input_SZ_A => Input_SZ_A+Input_SZ_B,
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Input_SZ_B => Input_SZ_A+Input_SZ_B
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)
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port map(
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sel => MACMUXsel_D,
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INA1 => ADDERout,
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INA2 => OP2_Resz,
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INB1 => MULTout,
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INB2 => OP1_Resz,
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OUTA => ADDERinA,
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OUTB => ADDERinB
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);
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OP1_Resz <= std_logic_vector(resize(signed(OP1_2C_D),Input_SZ_A+Input_SZ_B));
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OP2_Resz <= std_logic_vector(resize(signed(OP2_2C_D),Input_SZ_A+Input_SZ_B));
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--==============================================================
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--==============================================================
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--======================M A C M U X2 ==========================
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--==============================================================
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MAC_MUX2_inst : MAC_MUX2
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generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
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port map(
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sel => MACMUX2sel_D_D,
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RES2 => MULTout_D,
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RES1 => ADDERout,
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RES => RES
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);
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--==============================================================
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end ar_MAC_v2;
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