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r245:0fbfdf431a95 alexis
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top_synplify_win32.npl
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JDF G
PROJECT top
DESIGN top
DEVFAM PROASIC3
DEVICE PROASIC3
DEVSPEED Std
DEVPKG ""
DEVTOPLEVELMODULETYPE EDIF
DEVSIMULATOR Modelsim
DEVGENERATEDSIMULATIONMODEL VHDL
SOURCE synplify\top.edf
DEPASSOC top ..\..\boards\Projet-Blanc-M7A3P1K\top.ucf
[Normal]
xilxMapAllowLogicOpt=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
xilxMapCoverMode=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Speed
xilxNgdbld_AUL=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
xilxPAReffortLevel=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Medium
xilxNgdbldMacro=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1105378344, ..\..\netlists\xilinx\PROASIC3