HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-M7A3P1k/top_synplify.prj

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				source compile.synp
				add_file -vhdl -lib work config.vhd
				add_file -vhdl -lib work ahbrom.vhd
				add_file -vhdl -lib work leon3mp.vhd
				add_file -constraint ../../boards/Projet-Blanc-M7A3P1K/synplify.sdc

				#implementation: "synplify"
				impl -add synplify

				#device options
				set_option -technology PROASIC3
				set_option -part PROASIC3
				set_option -speed_grade Std

				#compilation/mapping options
				set_option -use_fsm_explorer 0
				set_option -write_vhdl 1
				#set_option -disable_io_insertion 0

				#map options
				set_option -frequency 50

				set_option -top_module top

				#set result format/file last
				project -result_file "synplify/top.edf"

				#implementation attributes
				set_option -package ""
				set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0
				impl -active "synplify"

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