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top_libero.prj
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KEY LIBERO "9.1"
KEY CAPTURE "9.1.0.18"
KEY DEFAULT_IMPORT_LOC "D:\GRLIB_BusAMBA\VHD_Lib\lib\lpp\lpp_matrix"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "23345426-15b3-4009-b8fc-d9c115e229e7"
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family ""
KEY VendorTechnology_Die ""
KEY VendorTechnology_Package ""
KEY ProjectLocation "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
LIST REVISIONS
VALUE="Impl1",NUM=1
VALUE="Impl2",NUM=2
CURREV=2
ENDLIST
LIST LIBRARIES
grlib
synplify
techmap
spw
eth
opencores
gaisler
esa
fmf
spansion
gsi
lpp
cypress
ENDLIST
LIST LIBRARY_grlib
ALIAS=grlib
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_synplify
ALIAS=synplify
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_techmap
ALIAS=techmap
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_spw
ALIAS=spw
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_eth
ALIAS=eth
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_opencores
ALIAS=opencores
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_gaisler
ALIAS=gaisler
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_esa
ALIAS=esa
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_fmf
ALIAS=fmf
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_spansion
ALIAS=spansion
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_gsi
ALIAS=gsi
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_lpp
ALIAS=lpp
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_cypress
ALIAS=cypress
COMPILE_OPTION=COMPILE
ENDLIST
LIST FileManager
VALUE "<project>\..\..\boards\Projet-Blanc-M7A3P1K\Projet-Blanc-M7A3P1K.pdc,pdc"
STATE="utd"
TIME="1318421517"
SIZE="5289"
ENDFILE
VALUE "<project>\..\..\lib\cypress\ssram\components.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6172"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\lib\cypress\ssram\cy7c1354b.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="16395"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\lib\cypress\ssram\cy7c1380d.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="26462"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\lib\cypress\ssram\package_utility.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2040"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\lib\esa\memoryctrl\mctrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="36771"
LIBRARY="esa"
ENDFILE
VALUE "<project>\..\..\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2210"
LIBRARY="esa"
ENDFILE
VALUE "<project>\..\..\lib\eth\comp\ethcomp.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="19122"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\lib\eth\core\eth_ahb_mst.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5935"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\lib\eth\core\eth_edcl_ahb_mst.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4620"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\lib\eth\core\eth_rstgen.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="1946"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\lib\eth\core\grethc.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="81374"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\lib\eth\core\greth_pkg.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="20023"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\lib\eth\core\greth_rx.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="10782"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\lib\eth\core\greth_tx.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="16451"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="13226"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\lib\eth\wrapper\greth_gen.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="13399"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\lib\fmf\fifo\idt7202.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="31912"
LIBRARY="fmf"
ENDFILE
VALUE "<project>\..\..\lib\fmf\flash\flash.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5307"
LIBRARY="fmf"
ENDFILE
VALUE "<project>\..\..\lib\fmf\flash\m25p80.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="51454"
LIBRARY="fmf"
ENDFILE
VALUE "<project>\..\..\lib\fmf\flash\s25fl064a.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="52107"
LIBRARY="fmf"
ENDFILE
VALUE "<project>\..\..\lib\fmf\utilities\conversions.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="39795"
LIBRARY="fmf"
ENDFILE
VALUE "<project>\..\..\lib\fmf\utilities\gen_utils.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5981"
LIBRARY="fmf"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\ambatest\ahbtbm.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="14280"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\ambatest\ahbtbp.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="37009"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\arith\arith.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4559"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\arith\div32.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5872"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\arith\mul32.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="12859"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\can\can.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6902"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\can\canmux.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="895"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\can\can_mc.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6335"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\can\can_mod.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="7699"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\can\can_oc.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5716"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\can\can_rd.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6731"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\gr1553b\gr1553b_pkg.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="13546"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\greth\ethernet_mac.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5107"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\greth\greth.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="12963"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\greth\grethm.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6121"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\greth\greth_gbit.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="12640"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\greth\greth_gbit_mb.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="13185"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\greth\greth_mb.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="13546"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\jtag\ahbjtag.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4394"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\jtag\ahbjtag_bsd.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3286"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\jtag\bscanregs.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2733"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\jtag\bscanregsbd.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3075"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\jtag\jtag.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6219"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\jtag\jtagcom.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6660"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\jtag\jtagtst.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="20077"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\jtag\libjtagcom.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2285"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3ft\leon3ft.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="7619"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\cachemem.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="19137"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\cpu_disasx.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2436"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\dsu3.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2716"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\dsu3x.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="25204"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\grfpushwx.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="10041"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\grfpwx.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4178"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\grfpwxsh.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="9591"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\grlfpwx.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4131"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\irqmp.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="10826"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\iu3.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="118264"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\leon3.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="33785"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\leon3cg.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="7865"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\leon3s.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="11594"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\leon3sh.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="7341"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\libcache.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="24648"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\libiu.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="8432"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\libmmu.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="11081"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\libproc3.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6115"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mfpwx.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="7283"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmu.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="18924"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmuconfig.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="22410"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmuiface.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="8057"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmulru.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5315"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmulrue.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3101"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmutlb.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="21062"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmutlbcam.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="9262"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmutw.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="10663"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmu_acache.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="12980"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmu_cache.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5604"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmu_dcache.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="61295"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\mmu_icache.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="25857"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\proc3.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6689"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\leon3\tbufmem.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2191"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\memctrl\memctrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="44002"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\memctrl\sdctrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="28826"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\memctrl\sdctrl64.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="28989"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\memctrl\sdmctrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="25462"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\memctrl\spimctrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="39987"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\memctrl\srctrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="15458"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\ahbdpram.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5288"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\ahbmst.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5404"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\ahbmst2.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="9610"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\ahbram.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="8493"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\ahbstat.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4587"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\ahbtrace.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2278"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\ahbtrace_mb.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2642"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\ahbtrace_mmb.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="15456"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\ahb_mst_iface.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5006"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\apbps2.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="13867"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\apbvga.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="12222"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\charrom.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="119223"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\charrom_package.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="1699"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\gptimer.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="10167"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\gracectrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="11527"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\grgpio.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="10703"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\grgpreg.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4657"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\grsysmon.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="16849"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\i2cmst_gen.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3305"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\i2cslv.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="20210"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\logan.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="16907"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\misc.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="40856"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\rstgen.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2574"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\spictrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="9667"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\spictrlx.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="65392"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\svgactrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="27836"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\wild.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5876"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\misc\wild2ahb.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="22895"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\net\net.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="12092"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\ahbrep.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4545"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\ata_device.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="15735"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\delay_wire.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2122"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\grusbdcsim.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6416"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\grusb_dclsim.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="18489"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\i2c_slave_model.v,hdl"
STATE="utd"
TIME="1309254878"
SIZE="11656"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\phy.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="24156"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\pwm_check.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="31865"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\sim.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="27132"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\spi_flash.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="19277"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\sram.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5429"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\sram16.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2306"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\sim\usbsim.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="57896"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\spacewire\grspw.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="15662"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\spacewire\grspw2.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="14573"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\spacewire\grspwm.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4227"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\spacewire\spacewire.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="22806"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\uart\ahbuart.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2944"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\uart\apbuart.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="18486"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\uart\dcom.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4954"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\uart\dcom_uart.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="9958"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\uart\libdcom.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5314"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\gaisler\uart\uart.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2677"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\lib\grlib\amba\ahbctrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="38737"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\amba\amba.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="42727"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\amba\amba_tp.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="72394"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\amba\apbctrl.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="11410"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\amba\defmst.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="1920"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\amba\devices.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="37789"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\amba\dma2ahb.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="25629"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\amba\dma2ahb_pkg.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6000"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="67479"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\modgen\leaves.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="682913"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\modgen\multlib.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="1614"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\sparc\cpu_disas.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4306"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\sparc\sparc.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="10265"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\sparc\sparc_disas.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="27668"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\stdlib\config.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2277"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\stdlib\stdio.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="8538"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\stdlib\stdlib.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="17577"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\stdlib\testlib.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="31699"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\stdlib\version.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="270"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\grlib\util\util.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="1766"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\lib\gsi\ssram\core_burst.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="21071"
LIBRARY="gsi"
ENDFILE
VALUE "<project>\..\..\lib\gsi\ssram\functions.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="97832"
LIBRARY="gsi"
ENDFILE
VALUE "<project>\..\..\lib\gsi\ssram\g880e18bt.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="7026"
LIBRARY="gsi"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\amba_lcd_16x2_ctrlr.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="4857"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\apb_lcd_ctrlr.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="4684"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\FRAME_CLK.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2063"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_CFG.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2262"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_DRVR.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="4068"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_ENGINE.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="5400"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_2x16_DRIVER.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="4608"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_CLK_GENERATOR.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2035"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\Top_LCD.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="3093"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\APB_IIR_CEL.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="8034"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FILTER.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="3402"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="6961"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FilterCTRLR.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="8493"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FILTER_RAM_CTRLR.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="5164"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="10609"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\IIR_CEL_FILTER.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2658"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="7792"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2232"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2276"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\RAM_CTRLR2.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="5030"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\Top_Filtre_IIR.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1005"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="141869"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="4032"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\APB_FFT.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="5929"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\APB_FFT_half.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="5590"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="12457"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="4721"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="25871"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="32249"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="5049"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\Flag_Extremum.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2574"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="4326"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="7485"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="3997"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="12080"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\Adder.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2272"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1930"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\ALU.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2278"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1958"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="5897"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\APB_AMR.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="3577"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\bclk_reg.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="685"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\Clock_multi.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1218"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\Dephaseur.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1492"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\Gene_Rz.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1011"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\lpp_AMR.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2523"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_balise\APB_Balise.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="4392"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_balise\lpp_balise.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1887"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="5159"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_delay\lpp_delay.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2254"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_delay\TimerDelay.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1726"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MAC.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="7280"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1961"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1985"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1710"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1775"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2230"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MUX2.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1692"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\REG.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="1812"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\general_purpose\Shifter.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2198"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="4077"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\AD7688_spi_if.vhd,hdl"
STATE="utd"
TIME="1343140024"
SIZE="2577"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="2995"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="4220"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\lpp_apb_ad_conv.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="4391"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_ad_Conv\WriteGen_ADC.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="2748"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="1335"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_amba\APB_MULTI_DIODE.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3238"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_amba\APB_SIMPLE_DIODE.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3455"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="2548"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\APB_CNA.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="4480"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\CNA_TabloC.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3111"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\Convertisseur_config.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="1626"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\Gene_SYNC.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="2613"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="2872"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\Serialize.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3956"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_cna\Systeme_Clock.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="2338"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="8207"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\ALU_v2.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="2878"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\APB_Matrix.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="4198"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3738"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3663"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="7938"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\MAC_v2.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="9200"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="2885"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="2955"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\Starter.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3521"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\TopMatrix_PDR.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="7268"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\Top_MatrixSpec.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="2328"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_matrix\TwoComplementer.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="2848"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_memory\APB_FIFO.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="10851"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_memory\lppFIFOx5.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3341"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_memory\lpp_FIFO.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="4761"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="5693"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="5741"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_uart\APB_UART.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="5098"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_uart\BaudGen.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3871"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_uart\lpp_uart.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3903"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_uart\Shift_REG.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3363"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_uart\UART.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="4070"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_usb\APB_USB.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="4054"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_usb\lpp_usb.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="3039"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\lpp\.\lpp_usb\RWbuf.vhd,hdl"
STATE="utd"
TIME="1343140025"
SIZE="5486"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\opencores\can\cancomp.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="3227"
LIBRARY="opencores"
ENDFILE
VALUE "<project>\..\..\lib\opencores\can\can_top.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="348580"
LIBRARY="opencores"
ENDFILE
VALUE "<project>\..\..\lib\opencores\occomp\occomp.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="9637"
LIBRARY="opencores"
ENDFILE
VALUE "<project>\..\..\lib\spw\comp\spwcomp.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="25287"
LIBRARY="spw"
ENDFILE
VALUE "<project>\..\..\lib\spw\wrapper\grspw2_gen.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="11472"
LIBRARY="spw"
ENDFILE
VALUE "<project>\..\..\lib\spw\wrapper\grspw_gen.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="11662"
LIBRARY="spw"
ENDFILE
VALUE "<project>\..\..\lib\synplify\sim\synattr.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="22767"
LIBRARY="synplify"
ENDFILE
VALUE "<project>\..\..\lib\synplify\sim\synplify.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="9340"
LIBRARY="synplify"
ENDFILE
VALUE "<project>\..\..\lib\techmap\gencomp\gencomp.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="48917"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\gencomp\netcomp.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="55671"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\inferred\ddr_inferred.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="2020"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\inferred\ddr_phy_inferred.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="34489"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\inferred\memory_inferred.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="9887"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\inferred\mul_inferred.vhd,hdl"
STATE="utd"
TIME="1309254996"
SIZE="4244"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\allclkgen.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="17054"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\allddr.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="41428"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\allmem.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="37015"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\allmul.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3153"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\allpads.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="25971"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\alltap.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="10148"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\clkand.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3334"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\clkgen.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="8992"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\clkmux.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3057"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\clkpad.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3974"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\clkpad_ds.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2859"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\cpu_disas_net.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4505"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\ddrphy.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="19101"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\ddr_ireg.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2748"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\ddr_oreg.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2873"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\grfpw_net.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="32800"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\grgates.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="1922"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\grlfpw_net.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="37743"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\grspwc2_net.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="36988"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\grspwc_net.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="35951"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\grusbhc_net.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="72748"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\inpad.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4645"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\inpad_ddr.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3492"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\inpad_ds.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3553"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\iodpad.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4645"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\iopad.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6438"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\iopad_ddr.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4909"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\iopad_ds.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4612"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\leon4_net.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="23007"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\lvds_combo.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3605"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\mul_61x61.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3733"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\nandtree.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2422"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\odpad.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5069"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\outpad.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5092"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\outpad_ddr.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3763"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\outpad_ds.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3473"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\regfile_3p.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3080"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\ringosc.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="1989"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\scanreg.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3635"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\skew_outpad.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2031"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\spictrl_net.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5893"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\ssrctrl_net.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="12025"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\syncfifo.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="2986"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\syncram.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="9040"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\syncram128.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="3504"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\syncram128bw.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5305"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\syncram156bw.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5421"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\syncram64.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4927"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\syncram_2p.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="12773"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\syncram_dp.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="7244"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\system_monitor.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="10506"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\tap.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6548"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\techbuf.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4457"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\techmult.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="7034"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\maps\toutpad.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="6172"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\proasic3\buffer_apa3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2154"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6738"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\proasic3\memory_apa3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="17067"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\techmap\proasic3\tap_proasic3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3674"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\lib\work\debug\cpu_disas.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="4217"
ENDFILE
VALUE "<project>\..\..\lib\work\debug\debug.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="1811"
ENDFILE
VALUE "<project>\..\..\lib\work\debug\grtestmod.vhd,hdl"
STATE="utd"
TIME="1309254994"
SIZE="5804"
ENDFILE
VALUE "<project>\ahbrom.vhd,hdl"
STATE="utd"
TIME="1314194813"
SIZE="9014"
ENDFILE
VALUE "<project>\config.vhd,hdl"
STATE="utd"
TIME="1343131155"
SIZE="6290"
ENDFILE
VALUE "<project>\leon3mp.vhd,hdl"
STATE="utd"
TIME="1343140322"
SIZE="14441"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="Synplify AE"
FUNCTION="Synthesis"
TOOL="Synplify"
LOCATION="C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\bin\synplify_pro.exe"
PARAM=""
BATCH=0
EndProfile
NAME="ModelSim AE"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Actel\Libero_v9.1\Model\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
EndProfile
NAME="WFL"
FUNCTION="Stimulus"
TOOL="WFL"
LOCATION="syncad.exe"
PARAM="-pwflite"
BATCH=0
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Actel\Libero_v9.1\Designer\bin\FlashPro.exe"
PARAM=""
BATCH=0
EndProfile
ENDLIST
LIST ProjectState5.1
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
ENDLIST