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----------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2004 GAISLER RESEARCH
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- See the file COPYING for the full details of the license.
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--
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-----------------------------------------------------------------------------
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-- Package: components
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-- File: components.vhd
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-- Author: Jiri Gaisler, Gaisler Research
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-- Description: Component declaration of Cypress sync-sram
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------------------------------------------------------------------------------
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-- pragma translate_off
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library ieee;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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package components is
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component cy7c1354
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generic (
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fname : string := "sram.srec"; -- File to read from
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-- Constant parameters
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addr_bits : INTEGER := 18;
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data_bits : INTEGER := 36;
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-- Timing parameters for -5 (225 Mhz)
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tCYC : TIME := 4.4 ns;
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tCH : TIME := 1.8 ns;
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tCL : TIME := 1.8 ns;
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tCO : TIME := 2.8 ns;
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tAS : TIME := 1.4 ns;
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tCENS : TIME := 1.4 ns;
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tWES : TIME := 1.4 ns;
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tDS : TIME := 1.4 ns;
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tAH : TIME := 0.4 ns;
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tCENH : TIME := 0.4 ns;
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tWEH : TIME := 0.4 ns;
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tDH : TIME := 0.4 ns
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-- Timing parameters for -5 (200 Mhz)
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--tCYC : TIME := 5.0 ns;
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--tCH : TIME := 2.0 ns;
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--tCL : TIME := 2.0 ns;
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--tCO : TIME := 3.2 ns;
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--tAS : TIME := 1.5 ns;
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--tCENS : TIME := 1.5 ns;
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--tWES : TIME := 1.5 ns;
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--tDS : TIME := 1.5 ns;
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--tAH : TIME := 0.5 ns;
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--tCENH : TIME := 0.5 ns;
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--tWEH : TIME := 0.5 ns;
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--tDH : TIME := 0.5 ns
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-- Timing parameters for -5 (166 Mhz)
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--tCYC : TIME := 6.0 ns;
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--tCH : TIME := 2.4 ns;
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--tCL : TIME := 2.4 ns;
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--tCO : TIME := 3.5 ns;
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--tAS : TIME := 1.5 ns;
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--tCENS : TIME := 1.5 ns;
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--tWES : TIME := 1.5 ns;
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--tDS : TIME := 1.5 ns;
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--tAH : TIME := 0.5 ns;
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--tCENH : TIME := 0.5 ns;
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--tWEH : TIME := 0.5 ns;
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--tDH : TIME := 0.5 ns
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);
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-- Port Declarations
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PORT (
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Dq : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); -- Data I/O
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Addr : IN STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0); -- Address
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Mode : IN STD_LOGIC := '1'; -- Burst Mode
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Clk : IN STD_LOGIC; -- Clk
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CEN_n : IN STD_LOGIC; -- CEN#
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AdvLd_n : IN STD_LOGIC; -- Adv/Ld#
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Bwa_n : IN STD_LOGIC; -- Bwa#
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Bwb_n : IN STD_LOGIC; -- BWb#
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Bwc_n : IN STD_LOGIC; -- Bwc#
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Bwd_n : IN STD_LOGIC; -- BWd#
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Rw_n : IN STD_LOGIC; -- RW#
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Oe_n : IN STD_LOGIC; -- OE#
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Ce1_n : IN STD_LOGIC; -- CE1#
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Ce2 : IN STD_LOGIC; -- CE2
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Ce3_n : IN STD_LOGIC; -- CE3#
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Zz : IN STD_LOGIC -- Snooze Mode
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);
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end component;
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component CY7C1380D
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GENERIC (
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fname : string := "sram.srec"; -- File to read from
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-- Constant Parameters
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addr_bits : INTEGER := 19; -- This is external address
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data_bits : INTEGER := 36;
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--Clock timings for 250Mhz
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Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
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Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
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Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
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Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
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Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
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Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
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Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
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Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
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Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
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Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
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Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
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Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
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Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
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Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
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Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
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Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
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Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
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Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
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Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
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Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
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Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
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);
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PORT (iZZ : IN STD_LOGIC;
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iMode : IN STD_LOGIC;
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iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
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inGW : IN STD_LOGIC;
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inBWE : IN STD_LOGIC;
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inBWd : IN STD_LOGIC;
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inBWc : IN STD_LOGIC;
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inBWb : IN STD_LOGIC;
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inBWa : IN STD_LOGIC;
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inCE1 : IN STD_LOGIC;
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iCE2 : IN STD_LOGIC;
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inCE3 : IN STD_LOGIC;
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inADSP : IN STD_LOGIC;
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inADSC : IN STD_LOGIC;
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inADV : IN STD_LOGIC;
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inOE : IN STD_LOGIC;
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ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
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iCLK : IN STD_LOGIC);
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end component;
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end;
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-- pragma translate_on
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