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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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----------------------------------------------------------------------------
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-- Package: allpads
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-- File: allpads.vhd
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-- Author: Jiri Gaisler et al. - Aeroflex Gaisler
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-- Description: All tech pads
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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package allpads is
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component apa3_clkpad
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generic (level : integer := 0; voltage : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3_clkpad_ds
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generic (level : integer := lvds);
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port (padp, padn : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3_inpad
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generic (level : integer := 0; voltage : integer := 0;
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filter : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3_inpad_ds
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generic (level : integer := lvds);
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port (padp, padn : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3_iopad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0;
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filter : integer := 0);
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port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3_iopad_ds
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generic (level : integer := lvds);
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port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3_odpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i, en : in std_ulogic);
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end component;
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component apa3_outpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i : in std_ulogic);
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end component;
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component apa3_outpad_ds
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generic (level : integer := lvds);
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port (padp, padn : out std_ulogic; i : in std_ulogic);
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end component;
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component apa3_toutpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i, en : in std_ulogic);
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end component;
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component apa3_toutpad_ds
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generic (level : integer := lvds);
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port (padp, padn : out std_ulogic; i, en : in std_ulogic);
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end component;
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component apa3e_clkpad
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generic (level : integer := 0; voltage : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3e_clkpad_ds
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generic (level : integer := lvds);
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port (padp, padn : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3e_inpad
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generic (level : integer := 0; voltage : integer := 0;
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filter : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3e_inpad_ds
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generic (level : integer := lvds);
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port (padp, padn : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3e_iopad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0;
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filter : integer := 0);
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port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3e_iopad_ds
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generic (level : integer := lvds);
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port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3e_odpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i, en : in std_ulogic);
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end component;
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component apa3e_outpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i : in std_ulogic);
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end component;
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component apa3e_outpad_ds
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generic (level : integer := lvds);
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port (padp, padn : out std_ulogic; i : in std_ulogic);
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end component;
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component apa3e_toutpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i, en : in std_ulogic);
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end component;
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component apa3e_toutpad_ds
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generic (level : integer := lvds);
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port (padp, padn : out std_ulogic; i, en : in std_ulogic);
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end component;
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component apa3l_clkpad
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generic (level : integer := 0; voltage : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3l_clkpad_ds
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generic (level : integer := lvds);
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port (padp, padn : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3l_inpad
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generic (level : integer := 0; voltage : integer := 0;
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filter : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3l_inpad_ds
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generic (level : integer := lvds);
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port (padp, padn : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3l_iopad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0;
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filter : integer := 0);
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port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3l_iopad_ds
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generic (level : integer := lvds);
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port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
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end component;
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component apa3l_odpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i, en : in std_ulogic);
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end component;
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component apa3l_outpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i : in std_ulogic);
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end component;
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component apa3l_outpad_ds
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generic (level : integer := lvds);
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port (padp, padn : out std_ulogic; i : in std_ulogic);
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end component;
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component apa3l_toutpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i, en : in std_ulogic);
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end component;
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component apa3l_toutpad_ds
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generic (level : integer := lvds);
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port (padp, padn : out std_ulogic; i, en : in std_ulogic);
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end component;
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component fusion_clkpad
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generic (level : integer := 0; voltage : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end component;
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component fusion_clkpad_ds
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generic (level : integer := lvds);
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port (padp, padn : in std_ulogic; o : out std_ulogic);
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end component;
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component fusion_inpad
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generic (level : integer := 0; voltage : integer := 0;
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filter : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end component;
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component fusion_inpad_ds
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generic (level : integer := lvds);
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port (padp, padn : in std_ulogic; o : out std_ulogic);
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end component;
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component fusion_iopad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0;
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filter : integer := 0);
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port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
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end component;
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component fusion_iopad_ds
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generic (level : integer := lvds);
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port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
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end component;
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component fusion_odpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i, en : in std_ulogic);
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end component;
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component fusion_outpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i : in std_ulogic);
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end component;
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component fusion_outpad_ds
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generic (level : integer := lvds);
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port (padp, padn : out std_ulogic; i : in std_ulogic);
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end component;
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component fusion_toutpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i, en : in std_ulogic);
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end component;
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component fusion_toutpad_ds
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generic (level : integer := lvds);
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port (padp, padn : out std_ulogic; i, en : in std_ulogic);
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end component;
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component axcel_inpad
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generic (level : integer := 0; voltage : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end component;
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component axcel_iopad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
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end component;
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component axcel_outpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i : in std_ulogic);
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end component;
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component axcel_odpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i : in std_ulogic);
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end component;
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component axcel_toutpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i, en : in std_ulogic);
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end component;
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component axcel_clkpad
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generic (level : integer := 0; voltage : integer := 0; arch : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end component;
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component axcel_inpad_ds
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generic (level : integer := lvds; voltage : integer := x33v);
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port (padp, padn : in std_ulogic; o : out std_ulogic);
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end component;
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component axcel_outpad_ds
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generic (level : integer := lvds; voltage : integer := x33v);
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port (padp, padn : out std_ulogic; i : in std_ulogic);
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end component;
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component atc18_inpad
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generic (level : integer := 0; voltage : integer := 0);
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port (pad : in std_logic; o : out std_logic);
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end component;
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component atc18_iopad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
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end component;
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component atc18_outpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_logic; i : in std_logic);
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end component;
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component atc18_odpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_logic; i : in std_logic);
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end component;
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component atc18_toutpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_logic; i, en : in std_logic);
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end component;
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component atc18_clkpad
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generic (level : integer := 0; voltage : integer := 0);
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port (pad : in std_logic; o : out std_logic);
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end component;
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component ihp25_inpad
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generic(level : integer := 0; voltage : integer := 0);
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port (pad : in std_logic; o : out std_logic);
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end component;
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component ihp25rh_inpad
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generic(level : integer := 0; voltage : integer := 0);
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port (pad : in std_logic; o : out std_logic);
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end component;
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component ihp25_iopad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
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end component;
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component ihp25rh_iopad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
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end component;
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component ihp25_outpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_logic; i : in std_logic);
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end component;
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component ihp25rh_outpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_logic; i : in std_logic);
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end component;
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component ihp25_toutpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i, en : in std_logic);
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end component;
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component ihp25rh_toutpad
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generic (level : integer := 0; slew : integer := 0;
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voltage : integer := 0; strength : integer := 0);
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port (pad : out std_ulogic; i, en : in std_logic);
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end component;
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component ihp25_clkpad
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generic (level : integer := 0; voltage : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end component;
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component ihp25rh_clkpad
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generic (level : integer := 0; voltage : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component rhumc_inpad
|
|
|
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
|
|
|
port (pad : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component rhumc_iopad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component rhumc_outpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_logic; i : in std_logic);
|
|
|
end component;
|
|
|
|
|
|
component rhumc_toutpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_logic; i, en : in std_logic);
|
|
|
end component;
|
|
|
|
|
|
component umc_inpad
|
|
|
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
|
|
|
port (pad : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component umc_iopad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component umc_outpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_logic; i : in std_logic);
|
|
|
end component;
|
|
|
|
|
|
component umc_toutpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_logic; i, en : in std_logic);
|
|
|
end component;
|
|
|
|
|
|
component unisim_inpad
|
|
|
generic (level : integer := 0; voltage : integer := x33v);
|
|
|
port (pad : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component unisim_iopad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12);
|
|
|
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component unisim_outpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12);
|
|
|
port (pad : out std_ulogic; i : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component unisim_odpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12);
|
|
|
port (pad : out std_ulogic; i : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component unisim_toutpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12);
|
|
|
port (pad : out std_ulogic; i, en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component unisim_skew_outpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
|
|
|
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
|
|
|
o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component unisim_clkpad
|
|
|
generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0);
|
|
|
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component unisim_inpad_ds
|
|
|
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
|
|
|
port (padp, padn : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component unisim_iopad_ds
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; term : integer := 0);
|
|
|
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component unisim_outpad_ds
|
|
|
generic (level : integer := lvds; voltage : integer := x33v);
|
|
|
port (padp, padn : out std_ulogic; i : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component unisim_clkpad_ds is
|
|
|
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
|
|
|
port (padp, padn : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component virtex4_inpad_ds
|
|
|
generic (level : integer := lvds; voltage : integer := x33v);
|
|
|
port (padp, padn : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component virtex4_clkpad_ds is
|
|
|
generic (level : integer := lvds; voltage : integer := x33v);
|
|
|
port (padp, padn : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component rh_lib18t_inpad
|
|
|
generic ( voltage : integer := 0; filter : integer := 0);
|
|
|
port (pad : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component rh_lib18t_iopad
|
|
|
generic ( strength : integer := 4);
|
|
|
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component rh_lib18t_inpad_ds is
|
|
|
port (padp, padn : in std_ulogic; o : out std_ulogic; en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component rh_lib18t_outpad_ds is
|
|
|
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ut025crh_inpad
|
|
|
generic ( level : integer := 0; voltage : integer := 0; filter : integer := 0);
|
|
|
port (pad : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component ut025crh_iopad is
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ut025crh_outpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_ulogic; i : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ut025crh_toutpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_ulogic; i, en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ut025crh_lvds_combo
|
|
|
generic (voltage : integer := 0; width : integer := 1);
|
|
|
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
|
|
|
odval, osval, en : in std_logic_vector(0 to width-1);
|
|
|
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
|
|
|
idval, isval : out std_logic_vector(0 to width-1));
|
|
|
end component;
|
|
|
|
|
|
component ut130hbd_inpad
|
|
|
generic ( level : integer := 0; voltage : integer := 0; filter : integer := 0);
|
|
|
port (pad : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component ut130hbd_iopad is
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ut130hbd_outpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_ulogic; i : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ut130hbd_toutpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_ulogic; i, en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ut130hbd_lvds_combo
|
|
|
generic (voltage : integer := 0; width : integer := 1);
|
|
|
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
|
|
|
odval, osval, en : in std_logic_vector(0 to width-1);
|
|
|
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
|
|
|
idval, isval : out std_logic_vector(0 to width-1));
|
|
|
end component;
|
|
|
|
|
|
component ut90nhbd_inpad is
|
|
|
generic (
|
|
|
level : integer := 0;
|
|
|
voltage : integer := 0;
|
|
|
filter : integer := 0);
|
|
|
port (
|
|
|
pad : in std_ulogic;
|
|
|
o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ut90nhbd_iopad is
|
|
|
generic(
|
|
|
level : integer := 0;
|
|
|
slew : integer := 0;
|
|
|
voltage : integer := 0;
|
|
|
strength : integer := 0);
|
|
|
port(
|
|
|
pad : inout std_ulogic;
|
|
|
i : in std_ulogic;
|
|
|
en : in std_ulogic;
|
|
|
o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ut90nhbd_outpad is
|
|
|
generic (
|
|
|
level : integer := 0;
|
|
|
slew : integer := 0;
|
|
|
voltage : integer := 0;
|
|
|
strength : integer := 0);
|
|
|
port(
|
|
|
pad : out std_ulogic;
|
|
|
i : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ut90nhbd_toutpad is
|
|
|
generic (
|
|
|
level : integer := 0;
|
|
|
slew : integer := 0;
|
|
|
voltage : integer := 0;
|
|
|
strength : integer := 0);
|
|
|
port (
|
|
|
pad : out std_ulogic;
|
|
|
i : in std_ulogic;
|
|
|
en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component rhumc_lvds_combo
|
|
|
generic (voltage : integer := 0; width : integer := 1);
|
|
|
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
|
|
|
odval, osval, en : in std_logic_vector(0 to width-1);
|
|
|
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
|
|
|
idval, isval : out std_logic_vector(0 to width-1);
|
|
|
lvdsref : in std_logic);
|
|
|
end component;
|
|
|
|
|
|
component umc_lvds_combo
|
|
|
generic (voltage : integer := 0; width : integer := 1);
|
|
|
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
|
|
|
odval, osval, en : in std_logic_vector(0 to width-1);
|
|
|
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
|
|
|
idval, isval : out std_logic_vector(0 to width-1);
|
|
|
lvdsref : in std_logic);
|
|
|
end component;
|
|
|
|
|
|
component peregrine_inpad is
|
|
|
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0;
|
|
|
strength : integer := 0);
|
|
|
port (pad : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component peregrine_iopad is
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component peregrine_toutpad is
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_ulogic; i, en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component nextreme_inpad
|
|
|
generic (level : integer := 0; voltage : integer := 0);
|
|
|
port (pad : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component nextreme_iopad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component nextreme_toutpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_logic; i, en : in std_logic);
|
|
|
end component;
|
|
|
|
|
|
component atc18rha_inpad
|
|
|
generic (level : integer := 0; voltage : integer := 0);
|
|
|
port (pad : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component atc18rha_iopad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component atc18rha_outpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_logic; i : in std_logic);
|
|
|
end component;
|
|
|
|
|
|
component atc18rha_odpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_logic; i : in std_logic);
|
|
|
end component;
|
|
|
|
|
|
component atc18rha_toutpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 0);
|
|
|
port (pad : out std_logic; i, en : in std_logic);
|
|
|
end component;
|
|
|
|
|
|
component atc18rha_clkpad
|
|
|
generic (level : integer := 0; voltage : integer := 0);
|
|
|
port (pad : in std_logic; o : out std_logic);
|
|
|
end component;
|
|
|
|
|
|
component n2x_inpad
|
|
|
generic (level : integer := 0; voltage : integer := x33v);
|
|
|
port (pad : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component n2x_iopad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12);
|
|
|
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component n2x_outpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 12);
|
|
|
port (pad : out std_ulogic; i : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component n2x_toutpad
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 12);
|
|
|
port (pad : out std_ulogic; i, en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component n2x_inpad_ds
|
|
|
generic (level : integer := lvds; voltage : integer := x33v);
|
|
|
port (padp, padn : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component n2x_iopad_ds
|
|
|
generic (level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12);
|
|
|
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component n2x_outpad_ds
|
|
|
generic (level : integer := lvds; voltage : integer := x33v);
|
|
|
port (padp, padn : out std_ulogic; i : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
end;
|
|
|
|
