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leon3mp_libero.prj.convert.8.6.bak
2622 lines | 89.5 KiB | text/plain | TextLexer
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KEY LIBERO "8.6"
KEY CAPTURE "8.6.2.10"
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family "Virtex2"
KEY VendorTechnology_Die ""
KEY VendorTechnology_Package ""
KEY ProjectLocation "."
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "leon3mp"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
grlib
secureip
eclipsee
synplify
techmap
spw
eth
opencores
core1553bbc
core1553brt
core1553brm
corePCIF
gaisler
esa
gleichmann
fmf
spansion
gsi
lpp
cypress
hynix
micron
openchip
work
ENDLIST
LIST LIBRARIES_grlib
ALIAS=grlib
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_secureip
ALIAS=secureip
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_eclipsee
ALIAS=eclipsee
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_synplify
ALIAS=synplify
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_techmap
ALIAS=techmap
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_spw
ALIAS=spw
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_eth
ALIAS=eth
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_opencores
ALIAS=opencores
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_core1553bbc
ALIAS=core1553bbc
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_core1553brt
ALIAS=core1553brt
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_core1553brm
ALIAS=core1553brm
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_corePCIF
ALIAS=corePCIF
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_gaisler
ALIAS=gaisler
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_esa
ALIAS=esa
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_gleichmann
ALIAS=gleichmann
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_fmf
ALIAS=fmf
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_spansion
ALIAS=spansion
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_gsi
ALIAS=gsi
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_lpp
ALIAS=lpp
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_cypress
ALIAS=cypress
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_hynix
ALIAS=hynix
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_micron
ALIAS=micron
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_openchip
ALIAS=openchip
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_work
ALIAS=work
COMPILE_OPTION=COMPILE
ENDLIST
LIST FileManager
VALUE "<project>/../../lib/grlib/stdlib/version.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/stdlib/config.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/stdlib/stdlib.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/stdlib/stdio.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/stdlib/testlib.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/util/util.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/sparc/sparc.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/sparc/sparc_disas.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/sparc/cpu_disas.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/modgen/multlib.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/modgen/leaves.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/amba.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/devices.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/defmst.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/apbctrl.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/ahbctrl.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/dma2ahb_pkg.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/dma2ahb.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/dma2ahb_tp.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/amba_tp.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/tech/eclipsee/simprims/eclipse.vhd,hdl"
STATE="utd"
LIBRARY="eclipsee"
ENDFILE
VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"
STATE="utd"
LIBRARY="synplify"
ENDFILE
VALUE "<project>/../../lib/synplify/sim/synattr.vhd,hdl"
STATE="utd"
LIBRARY="synplify"
ENDFILE
VALUE "<project>/../../lib/techmap/gencomp/gencomp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/gencomp/netcomp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/inferred/memory_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/inferred/ddr_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/inferred/mul_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/inferred/ddr_phy_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/eclipsee/memory_eclipse.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/allclkgen.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/allddr.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/allmem.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/allmul.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/allpads.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/alltap.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/clkgen.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/clkmux.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/clkand.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/ddr_ireg.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/ddr_oreg.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/ddrphy.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncram.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncram64.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncram_2p.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncram_dp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncfifo.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/regfile_3p.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/tap.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/techbuf.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/nandtree.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/clkpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/clkpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/inpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/inpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/iodpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/iopad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/iopad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/lvds_combo.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/odpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/outpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/outpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/toutpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/skew_outpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/grspwc_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/grspwc2_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/grlfpw_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/grfpw_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/leon4_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/mul_61x61.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/cpu_disas_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/grusbhc_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/ringosc.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/ssrctrl_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/system_monitor.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/grgates.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/inpad_ddr.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/outpad_ddr.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/iopad_ddr.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncram128bw.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncram128.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncram156bw.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/techmult.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/spictrl_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/scanreg.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/spw/comp/spwcomp.vhd,hdl"
STATE="utd"
LIBRARY="spw"
ENDFILE
VALUE "<project>/../../lib/spw/wrapper/grspw_gen.vhd,hdl"
STATE="utd"
LIBRARY="spw"
ENDFILE
VALUE "<project>/../../lib/spw/wrapper/grspw2_gen.vhd,hdl"
STATE="utd"
LIBRARY="spw"
ENDFILE
VALUE "<project>/../../lib/eth/comp/ethcomp.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/greth_pkg.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/eth_rstgen.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/eth_edcl_ahb_mst.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/eth_ahb_mst.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/greth_tx.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/greth_rx.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/grethc.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/wrapper/greth_gen.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/wrapper/greth_gbit_gen.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/opencores/occomp/occomp.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/can/cancomp.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/can/can_top.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/i2c/i2c_master_bit_ctrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/i2c/i2c_master_byte_ctrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/i2c/i2coc.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/spi/simple_spi_top.v,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/ud_cnt.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/ro_cnt.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_dma_fifo.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_dma_actrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_dma_tctrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_pio_tctrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_pio_actrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_controller.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_pio_controller.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/ocidec2_controller.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/ata_device_oc.v,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ac97/ac97_top.v,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/actel/core1553bbc/netlist/netlists/bc1553b_withoutio_rtaxs.vhd,hdl"
STATE="utd"
LIBRARY="core1553bbc"
ENDFILE
VALUE "<project>/../../lib/actel/core1553brt/./netlist/netlists/rt1553b_withoutio_rtaxs.vhd,hdl"
STATE="utd"
LIBRARY="core1553brt"
ENDFILE
VALUE "<project>/../../lib/actel/core1553brm/./netlist/netlists/BRM_withoutio_rtaxs.vhd,hdl"
STATE="utd"
LIBRARY="core1553brm"
ENDFILE
VALUE "<project>/../../lib/gaisler/arith/arith.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/arith/mul32.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/arith/div32.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/memctrl/memctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/memctrl/sdctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/memctrl/sdctrl64.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/memctrl/sdmctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/memctrl/srctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/memctrl/spimctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/leon3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmuconfig.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmuiface.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/libmmu.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/libiu.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/libcache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/libproc3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/cachemem.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmu_icache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmu_dcache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmu_acache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmutlbcam.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmulrue.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmulru.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmutlb.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmutw.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmu.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmu_cache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/cpu_disasx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/iu3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/grfpwx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mfpwx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/grlfpwx.vhd,hdl"
STATE="utd"
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VALUE "<project>/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl"
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VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/ApbDriver.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"
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VALUE "<project>/../../lib/openchip/charlcd/charlcd.vhd,hdl"
VALUE "<project>/../../lib/openchip/charlcd/apbcharlcd.vhd,hdl"
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ENDFILELIST
ENDLIST
ENDLIST
ENDLIST