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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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use IEEE.std_logic_textio.all;
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LIBRARY STD;
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use std.textio.all;
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LIBRARY grlib;
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USE grlib.stdlib.ALL;
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LIBRARY gaisler;
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USE gaisler.libdcom.ALL;
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USE gaisler.sim.ALL;
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USE gaisler.jtagtst.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY lpp;
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USE lpp.lpp_sim_pkg.ALL;
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USE lpp.lpp_lfr_sim_pkg.ALL;
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USE lpp.lpp_lfr_apbreg_pkg.ALL;
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USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
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ENTITY testbench IS
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END;
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ARCHITECTURE behav OF testbench IS
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COMPONENT LFR_em
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PORT (
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clk100MHz : IN STD_ULOGIC;
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clk49_152MHz : IN STD_ULOGIC;
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reset : IN STD_ULOGIC;
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TAG1 : IN STD_ULOGIC;
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TAG3 : OUT STD_ULOGIC;
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TAG2 : IN STD_ULOGIC;
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TAG4 : OUT STD_ULOGIC;
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address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
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data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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nSRAM_BE0 : OUT STD_LOGIC;
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nSRAM_BE1 : OUT STD_LOGIC;
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nSRAM_BE2 : OUT STD_LOGIC;
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nSRAM_BE3 : OUT STD_LOGIC;
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nSRAM_WE : OUT STD_LOGIC;
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nSRAM_CE : OUT STD_LOGIC;
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nSRAM_OE : OUT STD_LOGIC;
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spw1_din : IN STD_LOGIC;
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spw1_sin : IN STD_LOGIC;
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spw1_dout : OUT STD_LOGIC;
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spw1_sout : OUT STD_LOGIC;
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spw2_din : IN STD_LOGIC;
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spw2_sin : IN STD_LOGIC;
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spw2_dout : OUT STD_LOGIC;
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spw2_sout : OUT STD_LOGIC;
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bias_fail_sw : OUT STD_LOGIC;
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ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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ADC_smpclk : OUT STD_LOGIC;
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ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
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HK_smpclk : OUT STD_LOGIC;
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ADC_OEB_bar_HK : OUT STD_LOGIC;
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HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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TAG8 : OUT STD_LOGIC;
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led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
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END COMPONENT;
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--COMPONENT MINI_LFR_top
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-- PORT (
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-- clk_50 : IN STD_LOGIC;
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-- clk_49 : IN STD_LOGIC;
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-- reset : IN STD_LOGIC;
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-- BP0 : IN STD_LOGIC;
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-- BP1 : IN STD_LOGIC;
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-- LED0 : OUT STD_LOGIC;
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-- LED1 : OUT STD_LOGIC;
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-- LED2 : OUT STD_LOGIC;
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-- TXD1 : IN STD_LOGIC;
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-- RXD1 : OUT STD_LOGIC;
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-- nCTS1 : OUT STD_LOGIC;
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-- nRTS1 : IN STD_LOGIC;
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-- TXD2 : IN STD_LOGIC;
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-- RXD2 : OUT STD_LOGIC;
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-- nCTS2 : OUT STD_LOGIC;
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-- nDTR2 : IN STD_LOGIC;
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-- nRTS2 : IN STD_LOGIC;
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-- nDCD2 : OUT STD_LOGIC;
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-- IO0 : INOUT STD_LOGIC;
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-- IO1 : INOUT STD_LOGIC;
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-- IO2 : INOUT STD_LOGIC;
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-- IO3 : INOUT STD_LOGIC;
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-- IO4 : INOUT STD_LOGIC;
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-- IO5 : INOUT STD_LOGIC;
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-- IO6 : INOUT STD_LOGIC;
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-- IO7 : INOUT STD_LOGIC;
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-- IO8 : INOUT STD_LOGIC;
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-- IO9 : INOUT STD_LOGIC;
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-- IO10 : INOUT STD_LOGIC;
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-- IO11 : INOUT STD_LOGIC;
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-- SPW_EN : OUT STD_LOGIC;
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-- SPW_NOM_DIN : IN STD_LOGIC;
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-- SPW_NOM_SIN : IN STD_LOGIC;
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-- SPW_NOM_DOUT : OUT STD_LOGIC;
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-- SPW_NOM_SOUT : OUT STD_LOGIC;
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-- SPW_RED_DIN : IN STD_LOGIC;
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-- SPW_RED_SIN : IN STD_LOGIC;
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-- SPW_RED_DOUT : OUT STD_LOGIC;
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-- SPW_RED_SOUT : OUT STD_LOGIC;
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-- ADC_nCS : OUT STD_LOGIC;
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-- ADC_CLK : OUT STD_LOGIC;
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-- ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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-- SRAM_nWE : OUT STD_LOGIC;
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-- SRAM_CE : OUT STD_LOGIC;
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-- SRAM_nOE : OUT STD_LOGIC;
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-- SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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-- SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
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-- SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
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--END COMPONENT;
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-----------------------------------------------------------------------------
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SIGNAL clk_50 : STD_LOGIC := '0';
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SIGNAL clk_49 : STD_LOGIC := '0';
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SIGNAL reset : STD_LOGIC;
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SIGNAL BP0 : STD_LOGIC;
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SIGNAL BP1 : STD_LOGIC;
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SIGNAL LED0 : STD_LOGIC;
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SIGNAL LED1 : STD_LOGIC;
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SIGNAL LED2 : STD_LOGIC;
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SIGNAL TXD1 : STD_LOGIC;
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SIGNAL RXD1 : STD_LOGIC;
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SIGNAL nCTS1 : STD_LOGIC;
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SIGNAL nRTS1 : STD_LOGIC;
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SIGNAL TXD2 : STD_LOGIC;
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SIGNAL RXD2 : STD_LOGIC;
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SIGNAL nCTS2 : STD_LOGIC;
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SIGNAL nDTR2 : STD_LOGIC;
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SIGNAL nRTS2 : STD_LOGIC;
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SIGNAL nDCD2 : STD_LOGIC;
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SIGNAL IO0 : STD_LOGIC;
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SIGNAL IO1 : STD_LOGIC;
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SIGNAL IO2 : STD_LOGIC;
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SIGNAL IO3 : STD_LOGIC;
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SIGNAL IO4 : STD_LOGIC;
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SIGNAL IO5 : STD_LOGIC;
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SIGNAL IO6 : STD_LOGIC;
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SIGNAL IO7 : STD_LOGIC;
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SIGNAL IO8 : STD_LOGIC;
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SIGNAL IO9 : STD_LOGIC;
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SIGNAL IO10 : STD_LOGIC;
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SIGNAL IO11 : STD_LOGIC;
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SIGNAL SPW_EN : STD_LOGIC;
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SIGNAL SPW_NOM_DIN : STD_LOGIC;
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SIGNAL SPW_NOM_SIN : STD_LOGIC;
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SIGNAL SPW_NOM_DOUT : STD_LOGIC;
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SIGNAL SPW_NOM_SOUT : STD_LOGIC;
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SIGNAL SPW_RED_DIN : STD_LOGIC;
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SIGNAL SPW_RED_SIN : STD_LOGIC;
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SIGNAL SPW_RED_DOUT : STD_LOGIC;
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SIGNAL SPW_RED_SOUT : STD_LOGIC;
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SIGNAL ADC_nCS : STD_LOGIC;
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SIGNAL ADC_CLK : STD_LOGIC;
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SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL SRAM_nWE : STD_LOGIC;
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SIGNAL SRAM_CE : STD_LOGIC;
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SIGNAL SRAM_nOE : STD_LOGIC;
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SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
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SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL ADC_smpclk : STD_LOGIC;
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SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
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SIGNAL HK_smpclk : STD_LOGIC;
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SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
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SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL all_OEB_bar : STD_LOGIC_VECTOR(8 DOWNTO 0);
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SIGNAL HK_SEL_DATA : STD_LOGIC_VECTOR(13 DOWNTO 0);
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-----------------------------------------------------------------------------
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CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
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CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
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CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
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SIGNAL message_simu : STRING(1 TO 15) := "---------------";
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SIGNAL data_message : STRING(1 TO 15) := "---------------";
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SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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BEGIN
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-----------------------------------------------------------------------------
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-- TB
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-----------------------------------------------------------------------------
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PROCESS
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CONSTANT txp : TIME := 320 ns;
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VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
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BEGIN -- PROCESS
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TXD1 <= '1';
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reset <= '0';
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WAIT FOR 500 ns;
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reset <= '1';
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WAIT FOR 10000 ns;
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message_simu <= "0 - UART init ";
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UART_INIT(TXD1,txp);
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message_simu <= "1 - UART test ";
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UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
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UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
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UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
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UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
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data_read <= data_read_v;
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data_message <= "GPIO_data_write";
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-- UNSET the LFR reset
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message_simu <= "2 - LFR UNRESET";
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UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
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--UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
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--UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
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--
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message_simu <= "3 - LFR CONFIG ";
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--UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
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LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
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X"40000000",
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X"40001000",
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X"40002000",
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X"40003000",
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X"40004000",
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X"40005000");
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LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
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LFR_MODE_SBM1,
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X"7FFFFFFF", -- START DATE
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"00000",--DATA_SHAPING ( 4 DOWNTO 0)
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X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
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X"0001280A",--DELTA_F0 (31 DOWNTO 0)
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X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
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X"0001283F",--DELTA_F1 (31 DOWNTO 0)
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X"000127FF",--DELTA_F2 (31 DOWNTO 0)
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ADDR_BASE_LFR,
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X"40006000",
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X"40007000",
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X"40008000",
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X"40009000",
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X"4000A000",
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X"4000B000",
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X"4000C000",
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X"4000D000");
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UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
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UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
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message_simu <= "4 - GO GO GO !!";
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UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
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READ_STATUS: LOOP
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WAIT FOR 2 ms;
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data_message <= "READ_NEW_STATUS";
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UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
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data_read <= data_read_v;
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UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
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UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
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data_read <= data_read_v;
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UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
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END LOOP READ_STATUS;
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WAIT;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- CLOCK
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-----------------------------------------------------------------------------
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clk_50 <= NOT clk_50 AFTER 5 ns;
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clk_49 <= NOT clk_49 AFTER 10172 ps;
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-----------------------------------------------------------------------------
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-- DON'T CARE
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-----------------------------------------------------------------------------
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BP0 <= '0';
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BP1 <= '0';
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nRTS1 <= '0' ;
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TXD2 <= '1';
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nRTS2 <= '1';
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nDTR2 <= '1';
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SPW_NOM_DIN <= '1';
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SPW_NOM_SIN <= '1';
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SPW_RED_DIN <= '1';
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SPW_RED_SIN <= '1';
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ADC_SDO <= x"AA";
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SRAM_DQ <= (OTHERS => 'Z');
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--IO0 <= 'Z';
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--IO1 <= 'Z';
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--IO2 <= 'Z';
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--IO3 <= 'Z';
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--IO4 <= 'Z';
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--IO5 <= 'Z';
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--IO6 <= 'Z';
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--IO7 <= 'Z';
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--IO8 <= 'Z';
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--IO9 <= 'Z';
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--IO10 <= 'Z';
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--IO11 <= 'Z';
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-----------------------------------------------------------------------------
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-- DUT
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-----------------------------------------------------------------------------
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LFR_em_1: LFR_em
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PORT MAP (
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clk100MHz => clk_50,
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clk49_152MHz => clk_49,
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reset => reset,
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TAG1 => TXD1,
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TAG3 => RXD1,
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TAG2 => TXD2,
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TAG4 => RXD2,
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address => SRAM_A,
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data => SRAM_DQ,
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nSRAM_BE0 => SRAM_nBE(0),
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nSRAM_BE1 => SRAM_nBE(1),
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nSRAM_BE2 => SRAM_nBE(2),
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nSRAM_BE3 => SRAM_nBE(3),
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nSRAM_WE => SRAM_nWE,
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nSRAM_CE => SRAM_CE,
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nSRAM_OE => SRAM_nOE,
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spw1_din => SPW_NOM_DIN,
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spw1_sin => SPW_NOM_SIN,
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spw1_dout => SPW_NOM_DOUT,
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spw1_sout => SPW_NOM_SOUT,
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spw2_din => SPW_RED_DIN,
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spw2_sin => SPW_RED_SIN,
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spw2_dout => SPW_RED_DOUT,
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spw2_sout => SPW_RED_SOUT,
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bias_fail_sw => OPEN,
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ADC_OEB_bar_CH => ADC_OEB_bar_CH,
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ADC_smpclk => ADC_smpclk,
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ADC_data => ADC_data,
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HK_smpclk => HK_smpclk,
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ADC_OEB_bar_HK => ADC_OEB_bar_HK,
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HK_SEL => HK_SEL,
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TAG8 => OPEN,
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led => OPEN);
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all_OEB_bar <= ADC_OEB_bar_HK & ADC_OEB_bar_CH;
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WITH HK_SEL SELECT
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HK_SEL_DATA <=
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"00"&X"00F" WHEN "00",
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"00"&X"01F" WHEN "01",
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"00"&X"02F" WHEN "10",
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"XXXXXXXXXXXXXX" WHEN OTHERS;
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WITH all_OEB_bar SELECT
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ADC_data <=
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"00"&X"000" WHEN "111111110",
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"00"&X"001" WHEN "111111101",
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"00"&X"002" WHEN "111111011",
|
|
|
"00"&X"003" WHEN "111110111",
|
|
|
"00"&X"004" WHEN "111101111",
|
|
|
"00"&X"005" WHEN "111011111",
|
|
|
"00"&X"006" WHEN "110111111",
|
|
|
"00"&X"007" WHEN "101111111",
|
|
|
HK_SEL_DATA WHEN "011111111",
|
|
|
"XXXXXXXXXXXXXX" WHEN OTHERS;
|
|
|
|
|
|
END;
|
|
|
|
