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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library grlib, techmap;
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use grlib.amba.all;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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--use gaisler.sim.all;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.general_purpose.all;
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use lpp.Rocket_PCM_Encoder.all;
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use work.Convertisseur_config.all;
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use work.config.all;
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--==================================================================
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--
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--
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-- FPGA FREQ = 48MHz
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-- ADC Oscillator frequency = 12MHz
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--
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--
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--==================================================================
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entity ici4 is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
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);
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port (
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reset : in std_ulogic;
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clk : in std_ulogic;
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sclk : in std_logic;
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Gate : in std_logic;
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MinF : in std_logic;
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MajF : in std_logic;
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Data : out std_logic;
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LF_SCK : out std_logic;
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LF_CNV : out std_logic;
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LF_SDO1 : in std_logic;
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LF_SDO2 : in std_logic;
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LF_SDO3 : in std_logic;
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DC_ADC_Sclk : out std_logic;
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DC_ADC_IN : in std_logic_vector(1 downto 0);
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DC_ADC_ClkDiv : out std_logic;
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DC_ADC_FSynch : out std_logic;
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SET_RESET0 : out std_logic;
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SET_RESET1 : out std_logic;
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LED : out std_logic
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);
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end;
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architecture rtl of ici4 is
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signal clk_buf,reset_buf : std_logic;
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Constant FramePlacerCount : integer := 2;
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signal WordCount : integer range 0 to WordCnt-1;
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signal WordClk : std_logic;
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signal AMR1X : std_logic_vector(23 downto 0);
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signal AMR1Y : std_logic_vector(23 downto 0);
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signal AMR1Z : std_logic_vector(23 downto 0);
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signal AMR2X : std_logic_vector(23 downto 0);
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signal AMR2Y : std_logic_vector(23 downto 0);
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signal AMR2Z : std_logic_vector(23 downto 0);
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signal AMR3X : std_logic_vector(23 downto 0);
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signal AMR3Y : std_logic_vector(23 downto 0);
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signal AMR3Z : std_logic_vector(23 downto 0);
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signal AMR4X : std_logic_vector(23 downto 0);
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signal AMR4Y : std_logic_vector(23 downto 0);
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signal AMR4Z : std_logic_vector(23 downto 0);
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signal TEMP1 : std_logic_vector(23 downto 0);
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signal TEMP2 : std_logic_vector(23 downto 0);
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signal TEMP3 : std_logic_vector(23 downto 0);
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signal TEMP4 : std_logic_vector(23 downto 0);
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signal LF1 : std_logic_vector(15 downto 0);
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signal LF2 : std_logic_vector(15 downto 0);
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signal LF3 : std_logic_vector(15 downto 0);
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signal data_int : std_logic;
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signal CrossDomainSync : std_logic;
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begin
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LED <= not data_int;
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data <= data_int;
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CDS0 : entity work.CrossDomainSyncGen
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Port map(
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reset => reset,
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ClockS => sclk,
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ClockF => clk,
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SyncSignal => CrossDomainSync
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);
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TM : entity work.TM_MODULE
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generic map(
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WordSize => WordSize,
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WordCnt => WordCnt,
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MinFCount => MinFCount
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)
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port map(
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reset =>reset,
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clk =>clk,
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MinF =>MinF,
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MajF =>MajF,
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sclk =>sclk,
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gate =>gate,
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data =>data_int,
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WordClk =>WordClk,
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LF1 => LF1,
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LF2 => LF2,
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LF3 => LF3,
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AMR1X => AMR1X,
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AMR1Y => AMR1Y,
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AMR1Z => AMR1Z,
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AMR2X => AMR2X,
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AMR2Y => AMR2Y,
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AMR2Z => AMR2Z,
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AMR3X => AMR3X,
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AMR3Y => AMR3Y,
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AMR3Z => AMR3Z,
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AMR4X => AMR4X,
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AMR4Y => AMR4Y,
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AMR4Z => AMR4Z,
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Temp1 => Temp1,
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Temp2 => Temp2,
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Temp3 => Temp3,
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Temp4 => Temp4
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);
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DC_ADC0:entity work.DC_ACQ_TOP
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generic map (
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WordSize => WordSize,
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WordCnt => WordCnt,
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MinFCount => MinFCount,
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EnableSR => 0,
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CstDATA => SEND_CONSTANT_DATA,
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FakeADC => 0
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)
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port map(
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reset => reset,
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clk => clk,
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SyncSig => CrossDomainSync,
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minorF => minF,
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majorF => majF,
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sclk => sclk,
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WordClk => WordClk,
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DC_ADC_Sclk => DC_ADC_Sclk,
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DC_ADC_IN => DC_ADC_IN,
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DC_ADC_ClkDiv => DC_ADC_ClkDiv,
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DC_ADC_FSynch => DC_ADC_FSynch,
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SET_RESET0 => SET_RESET0,
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SET_RESET1 => SET_RESET1,
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AMR1X => AMR1X,
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AMR1Y => AMR1Y,
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AMR1Z => AMR1Z,
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AMR2X => AMR2X,
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AMR2Y => AMR2Y,
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AMR2Z => AMR2Z,
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AMR3X => AMR3X,
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AMR3Y => AMR3Y,
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AMR3Z => AMR3Z,
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AMR4X => AMR4X,
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AMR4Y => AMR4Y,
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AMR4Z => AMR4Z,
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Temp1 => Temp1,
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Temp2 => Temp2,
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Temp3 => Temp3,
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Temp4 => Temp4
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);
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LF: entity work.LF_ACQ_TOP
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generic map(
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WordSize => WordSize,
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WordCnt => WordCnt,
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MinFCount => MinFCount,
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CstDATA => SEND_CONSTANT_DATA,
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IIRFilter => 0
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)
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port map(
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reset => reset,
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clk => clk,
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SyncSig => CrossDomainSync,
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minorF => minF,
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majorF => majF,
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sclk => sclk,
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WordClk => WordClk,
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LF_SCK => LF_SCK,
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LF_CNV => LF_CNV,
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LF_SDO1 => LF_SDO1,
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LF_SDO2 => LF_SDO2,
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LF_SDO3 => LF_SDO3,
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LF1 => LF1,
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LF2 => LF2,
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LF3 => LF3
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);
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end rtl;
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