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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:03:54 08/21/2013
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-- Design Name:
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-- Module Name: TM_MODULE - AR_TM_MODULE
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.general_purpose.all;
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use lpp.Rocket_PCM_Encoder.all;
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entity TM_MODULE is
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generic(
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WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
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);
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port(
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reset : in std_logic;
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clk : in std_logic;
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MinF : in std_logic;
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MajF : in std_logic;
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sclk : in std_logic;
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gate : in std_logic;
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data : out std_logic;
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WordClk : out std_logic;
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LF1 : in std_logic_vector(15 downto 0);
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LF2 : in std_logic_vector(15 downto 0);
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LF3 : in std_logic_vector(15 downto 0);
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AMR1X : in std_logic_vector(23 downto 0);
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AMR1Y : in std_logic_vector(23 downto 0);
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AMR1Z : in std_logic_vector(23 downto 0);
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AMR2X : in std_logic_vector(23 downto 0);
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AMR2Y : in std_logic_vector(23 downto 0);
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AMR2Z : in std_logic_vector(23 downto 0);
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AMR3X : in std_logic_vector(23 downto 0);
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AMR3Y : in std_logic_vector(23 downto 0);
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AMR3Z : in std_logic_vector(23 downto 0);
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AMR4X : in std_logic_vector(23 downto 0);
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AMR4Y : in std_logic_vector(23 downto 0);
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AMR4Z : in std_logic_vector(23 downto 0);
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Temp1 : in std_logic_vector(23 downto 0);
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Temp2 : in std_logic_vector(23 downto 0);
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Temp3 : in std_logic_vector(23 downto 0);
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Temp4 : in std_logic_vector(23 downto 0)
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);
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end TM_MODULE;
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architecture AR_TM_MODULE of TM_MODULE is
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Constant FramePlacerCount : integer := 2;
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signal MinFCnt : integer range 0 to MinFCount-1;
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signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0);
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signal WordCount : integer range 0 to WordCnt-1;
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signal data_int : std_logic;
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signal MuxOUT : std_logic_vector(WordSize-1 downto 0);
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signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0);
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signal Sel : integer range 0 to 1;
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signal MinF_Inv : std_logic;
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signal Gate_Inv : std_logic;
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signal sclk_Inv : std_logic;
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begin
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Gate_Inv <= not Gate;
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sclk_Inv <= not Sclk;
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MinF_Inv <= not MinF;
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data <= data_int;
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SD0 : Serial_Driver
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generic map(WordSize)
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port map(sclk_Inv,MuxOUT,Gate_inv,data_int);
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WC0 : Word_Cntr
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generic map(WordSize,WordCnt)
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port map(sclk_Inv,MinF,WordClk,WordCount);
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MFC0 : MinF_Cntr
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generic map(MinFCount)
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port map(
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clk => MinF_Inv,
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reset => MajF,
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Cnt_out => MinFCnt
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);
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MUX0 : Serial_Driver_Multiplexor
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generic map(FramePlacerCount,WordSize)
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port map(sclk_Inv,Sel,MuxIN,MuxOUT);
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DCFP0 : entity work.DC_FRAME_PLACER
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generic map(WordSize,WordCnt,MinFCount)
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port map(
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clk => Sclk,
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Wcount => WordCount,
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MinFCnt => MinFCnt,
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Flag => FramePlacerFlags(0),
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AMR1X => AMR1X,
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AMR1Y => AMR1Y,
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AMR1Z => AMR1Z,
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AMR2X => AMR2X,
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AMR2Y => AMR2Y,
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AMR2Z => AMR2Z,
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AMR3X => AMR3X,
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AMR3Y => AMR3Y,
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AMR3Z => AMR3Z,
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AMR4X => AMR4X,
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AMR4Y => AMR4Y,
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AMR4Z => AMR4Z,
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Temp1 => Temp1,
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Temp2 => Temp2,
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Temp3 => Temp3,
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Temp4 => Temp4,
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WordOut => MuxIN(7 downto 0));
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LFP0 : entity work.LF_FRAME_PLACER
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generic map(WordSize,WordCnt,MinFCount)
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port map(
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clk => Sclk,
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Wcount => WordCount,
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Flag => FramePlacerFlags(1),
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LF1 => LF1,
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LF2 => LF2,
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LF3 => LF3,
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WordOut => MuxIN(15 downto 8));
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process(clk)
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variable SelVar : integer range 0 to 1;
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begin
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if clk'event and clk ='1' then
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Decoder: FOR i IN 0 to FramePlacerCount-1 loop
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if FramePlacerFlags(i) = '1' then
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SelVar := i;
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end if;
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END loop Decoder;
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Sel <= SelVar;
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end if;
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end process;
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end AR_TM_MODULE;
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