HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · designs/LFR-EQM-WFP_MS/Makefile

temp : update ADC driver...

temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)

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r594:a9702b7364d2 simu_with_Leon3


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simu_with_Leon3

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      #GRLIB=../..

      VHDLIB=../..

      SCRIPTSDIR=$(VHDLIB)/scripts/

      GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)

      TOP=LFR_EQM

      BOARD=LFR-EQM

      include $(VHDLIB)/boards/$(BOARD)/Makefile.inc

      DEVICE=$(PART)-$(PACKAGE)$(SPEED)

      UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf

      QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf

      EFFORT=high

      XSTOPT=

      SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"

      #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd

      #VHDLSYNFILES=config.vhd leon3mp.vhd

      VHDLSYNFILES=LFR-EQM.vhd

      VHDLSIMFILES=testbench.vhd

      #SIMTOP=testbench

      PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc

      #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc

      SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc

      BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut

      CLEAN=soft-clean

      TECHLIBS = proasic3e

      LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \

      	tmtc openchip hynix ihp gleichmann micron usbhc

      DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \

      	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \

      	./amba_lcd_16x2_ctrlr \

      	./general_purpose/lpp_AMR \

      	./general_purpose/lpp_balise \

      	./general_purpose/lpp_delay \

      	./dsp/lpp_fft_rtax \

      	./lpp_uart \

      	./lpp_usb \

      	./lpp_sim/CY7C1061DV33 \

      FILESKIP = i2cmst.vhd \

      	APB_MULTI_DIODE.vhd \

      	APB_MULTI_DIODE.vhd \

      	Top_MatrixSpec.vhd \

      	APB_FFT.vhd\

      	CoreFFT_simu.vhd \

      	lpp_lfr_apbreg_simu.vhd

      include $(GRLIB)/bin/Makefile

      include $(GRLIB)/software/leon3/Makefile

      ##################  project specific targets ##########################

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				#GRLIB=../..
				VHDLIB=../..
				SCRIPTSDIR=$(VHDLIB)/scripts/
				GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
				TOP=LFR_EQM
				BOARD=LFR-EQM
				include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
				DEVICE=$(PART)-$(PACKAGE)$(SPEED)
				UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
				QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
				EFFORT=high
				XSTOPT=
				SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
				#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
				#VHDLSYNFILES=config.vhd leon3mp.vhd
				VHDLSYNFILES=LFR-EQM.vhd
				VHDLSIMFILES=testbench.vhd
				#SIMTOP=testbench
				PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
				#SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
				SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc

				BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
				CLEAN=soft-clean

				TECHLIBS = proasic3e

				LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
				tmtc openchip hynix ihp gleichmann micron usbhc

				DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
				pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
				./amba_lcd_16x2_ctrlr \
				./general_purpose/lpp_AMR \
				./general_purpose/lpp_balise \
				./general_purpose/lpp_delay \
				./dsp/lpp_fft_rtax \
				./lpp_uart \
				./lpp_usb \
				./lpp_sim/CY7C1061DV33 \

				FILESKIP = i2cmst.vhd \
				APB_MULTI_DIODE.vhd \
				APB_MULTI_DIODE.vhd \
				Top_MatrixSpec.vhd \
				APB_FFT.vhd\
				CoreFFT_simu.vhd \
				lpp_lfr_apbreg_simu.vhd

				include $(GRLIB)/bin/Makefile
				include $(GRLIB)/software/leon3/Makefile

				################## project specific targets ##########################