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##############################################################
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#
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# Xilinx Core Generator version 14.2
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# Date: Mon Apr 8 17:56:57 2013
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:mig:3.92
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc6slx45
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SET devicefamily = spartan6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = fgg484
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -3
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SET verilogsim = false
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92
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# END Select
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# BEGIN Parameters
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CSET component_name=mig_38
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CSET xml_input_file=./mig_38/user_design/mig.prj
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-07-21T06:31:03Z
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# END Extra information
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GENERATE
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# CRC: 62df7c4e
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