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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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library lpp;
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use lpp.general_purpose.all;
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--! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration
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entity ALU is
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generic(
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Arith_en : integer := 1;
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Logic_en : integer := 1;
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Input_SZ_1 : integer := 16;
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Input_SZ_2 : integer := 16);
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port(
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clk : in std_logic; --! Horloge du composant
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reset : in std_logic; --! Reset general du composant
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ctrl : in std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
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comp : in std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
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OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
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OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second Op�rande
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RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! R�sultat de l'op�ration
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);
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end ALU;
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--! @details S�lection grace a l'entr�e "ctrl" :
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--! Pause : IDLE = 000
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--! Multiplieur/Accumulateur : MAC = 001
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--! Multiplication : MULT = 010
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--! Addition : ADD = 011
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--! Reset du MAC : CLRMAC = 100
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architecture ar_ALU of ALU is
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begin
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arith : if Arith_en = 1 generate
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MACinst : MAC
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generic map(Input_SZ_1,Input_SZ_2)
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port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES);
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end generate;
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end architecture;
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