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KEY LIBERO "9.1"
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|
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KEY CAPTURE "9.1.0.18"
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KEY DEFAULT_IMPORT_LOC "D:\GRLIB_BusAMBA\VHD_Lib\lib\lpp\lpp_matrix"
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KEY DEFAULT_OPEN_LOC ""
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KEY ProjectID "c6f04fee-8968-4279-8a35-d5131f910fc8"
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KEY HDLTechnology "VHDL"
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KEY VendorTechnology_Family "ProASIC3"
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KEY VendorTechnology_Die "M7IS8X8M2"
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KEY VendorTechnology_Package "fg484"
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KEY ProjectLocation "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-LPP-M7A3P1000"
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KEY SimulationType "VHDL"
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KEY Vendor "Actel"
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KEY ActiveRoot "leon3mp::work"
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LIST REVISIONS
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VALUE="Impl1",NUM=1
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VALUE="Impl2",NUM=2
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CURREV=2
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ENDLIST
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LIST LIBRARIES
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grlib
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synplify
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|
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techmap
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|
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spw
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|
eth
|
|
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opencores
|
|
|
gaisler
|
|
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esa
|
|
|
fmf
|
|
|
spansion
|
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gsi
|
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|
lpp
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cypress
|
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ENDLIST
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|
LIST LIBRARY_grlib
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|
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ALIAS=grlib
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_synplify
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ALIAS=synplify
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_techmap
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ALIAS=techmap
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_spw
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ALIAS=spw
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_eth
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ALIAS=eth
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_opencores
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ALIAS=opencores
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_gaisler
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ALIAS=gaisler
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_esa
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ALIAS=esa
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_fmf
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ALIAS=fmf
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_spansion
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ALIAS=spansion
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_gsi
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ALIAS=gsi
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_lpp
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ALIAS=lpp
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_cypress
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ALIAS=cypress
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST FileManager
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VALUE "<project>\..\..\boards\Projet-Blanc-LPP-M7A3P1000\Projet-Blanc-LPP-M7A3P1000.pdc,pdc"
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ENDFILE
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ENDFILE
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ENDFILE
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ENDFILE
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ENDFILE
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ENDFILE
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ENDFILE
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ENDFILE
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ENDFILE
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VALUE "<project>\..\..\lib\fmf\fifo\idt7202.vhd,hdl"
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STATE="utd"
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ENDFILE
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VALUE "<project>\..\..\lib\fmf\flash\flash.vhd,hdl"
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VALUE "<project>\..\..\lib\gaisler\ambatest\ahbtbp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\ambatest\ahbtbm.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\i2c_slave_model.v,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\sim.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\sram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\ata_device.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\sram16.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\phy.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\ahbrep.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\delay_wire.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\spi_flash.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\pwm_check.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\usbsim.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\grusbdcsim.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\grusb_dclsim.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\jtag\jtagtst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\utilities\conversions.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\utilities\gen_utils.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\flash\flash.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\flash\s25fl064a.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\flash\m25p80.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\fifo\idt7202.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gsi\ssram\functions.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gsi\ssram\core_burst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gsi\ssram\g880e18bt.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\cypress\ssram\components.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\cypress\ssram\package_utility.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\cypress\ssram\cy7c1354b.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\cypress\ssram\cy7c1380d.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\work\debug\debug.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\work\debug\grtestmod.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\work\debug\cpu_disas.vhd,hdl"
|
|
|
VALUE "<project>\config.vhd,hdl"
|
|
|
VALUE "<project>\ahbrom.vhd,hdl"
|
|
|
VALUE "<project>\leon3mp.vhd,hdl"
|
|
|
VALUE "<project>\testbench.vhd,hdl"
|
|
|
ENDLIST
|
|
|
LIST ProjectState5.1
|
|
|
LIST Impl1
|
|
|
LiberoState=Post_Synthesis
|
|
|
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateSuccess
|
|
|
LIST FlowOptions
|
|
|
UsePhySynth=FALSE
|
|
|
UseSynth=TRUE
|
|
|
ENDLIST
|
|
|
Used_File_List
|
|
|
ENDUsed_File_List
|
|
|
ENDLIST
|
|
|
LIST Impl2
|
|
|
LiberoState=Post_Layout
|
|
|
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateSuccess
|
|
|
ideDESIGNER(<project>\designer\impl2\leon3mp.adb,adb)=StateSuccess
|
|
|
LIST FlowOptions
|
|
|
UsePhySynth=FALSE
|
|
|
UseSynth=TRUE
|
|
|
ENDLIST
|
|
|
Used_File_List
|
|
|
ENDUsed_File_List
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
LIST AssociatedStimulus
|
|
|
ENDLIST
|
|
|
LIST Other_Association
|
|
|
ENDLIST
|
|
|
LIST SimulationOptions
|
|
|
UseAutomaticDoFile=true
|
|
|
IncludeWaveDo=false
|
|
|
Type=max
|
|
|
RunTime=1000ns
|
|
|
Resolution=1ps
|
|
|
VsimOpt=
|
|
|
EntityName=testbench
|
|
|
TopInstanceName=<top>_0
|
|
|
DoFileName=
|
|
|
DoFileName2=wave.do
|
|
|
DoFileParams=
|
|
|
DisplayDUTWave=false
|
|
|
LogAllSignals=false
|
|
|
DumpVCD=false
|
|
|
VCDFileName=power.vcd
|
|
|
ENDLIST
|
|
|
LIST ModelSimLibPath
|
|
|
UseCustomPath=FALSE
|
|
|
LibraryPath=
|
|
|
ENDLIST
|
|
|
LIST GlobalFlowOptions
|
|
|
GenerateHDLAfterSynthesis=FALSE
|
|
|
GenerateHDLAfterPhySynthesis=FALSE
|
|
|
RunDRCAfterSynthesis=FALSE
|
|
|
AutoCheckConstraints=TRUE
|
|
|
UpdateViewDrawIni=TRUE
|
|
|
UpdateModelSimIni=TRUE
|
|
|
NoIOMode=FALSE
|
|
|
GenerateHDLFromSchematic=TRUE
|
|
|
FlashProInputFile=pdb
|
|
|
SmartGenCompileReport=T
|
|
|
ENDLIST
|
|
|
LIST PhySynthesisOptions
|
|
|
ENDLIST
|
|
|
LIST Profiles
|
|
|
NAME="Synplify AE"
|
|
|
FUNCTION="Synthesis"
|
|
|
TOOL="Synplify"
|
|
|
LOCATION="C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\bin\synplify_pro.exe"
|
|
|
PARAM=""
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
NAME="ModelSim AE"
|
|
|
FUNCTION="Simulation"
|
|
|
TOOL="ModelSim"
|
|
|
LOCATION="C:\Actel\Libero_v9.1\Model\win32acoem\modelsim.exe"
|
|
|
PARAM=""
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
NAME="WFL"
|
|
|
FUNCTION="Stimulus"
|
|
|
TOOL="WFL"
|
|
|
LOCATION="syncad.exe"
|
|
|
PARAM="-pwflite"
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
NAME="FlashPro"
|
|
|
FUNCTION="Program"
|
|
|
TOOL="FlashPro"
|
|
|
LOCATION="C:\Actel\Libero_v9.1\Designer\bin\FlashPro.exe"
|
|
|
PARAM=""
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
ENDLIST
|
|
|
LIST ProjectState5.1
|
|
|
LIST "leon3mp::work"
|
|
|
LIST Impl1
|
|
|
LiberoState=Post_Synthesis
|
|
|
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateSuccess
|
|
|
LIST FlowOptions
|
|
|
UsePhySynth=FALSE
|
|
|
UseSynth=TRUE
|
|
|
ENDLIST
|
|
|
Used_File_List
|
|
|
ENDUsed_File_List
|
|
|
ENDLIST
|
|
|
LIST Impl2
|
|
|
LiberoState=Post_Layout
|
|
|
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateSuccess
|
|
|
ideDESIGNER(<project>\designer\impl2\leon3mp.adb,adb)=StateSuccess
|
|
|
LIST FlowOptions
|
|
|
UsePhySynth=FALSE
|
|
|
UseSynth=TRUE
|
|
|
ENDLIST
|
|
|
Used_File_List
|
|
|
ENDUsed_File_List
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
LIST ExcludePackageForSimulation
|
|
|
ENDLIST
|
|
|
LIST ExcludePackageForSynthesis
|
|
|
LIST leon3mp
|
|
|
VALUE "<project>\..\..\lib\grlib\stdlib\stdio.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\grlib\stdlib\testlib.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\grlib\util\util.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\grlib\sparc\sparc_disas.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\grlib\sparc\cpu_disas.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\grlib\amba\amba_tp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\synplify\sim\synplify.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\synplify\sim\synattr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\ambatest\ahbtbp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\ambatest\ahbtbm.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\i2c_slave_model.v,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\sim.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\sram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\ata_device.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\sram16.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\phy.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\ahbrep.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\delay_wire.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\spi_flash.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\pwm_check.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\usbsim.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\grusbdcsim.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\sim\grusb_dclsim.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gaisler\jtag\jtagtst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\utilities\conversions.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\utilities\gen_utils.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\flash\flash.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\flash\s25fl064a.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\flash\m25p80.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\fmf\fifo\idt7202.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gsi\ssram\functions.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gsi\ssram\core_burst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\gsi\ssram\g880e18bt.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\cypress\ssram\components.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\cypress\ssram\package_utility.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\cypress\ssram\cy7c1354b.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\cypress\ssram\cy7c1380d.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\work\debug\debug.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\work\debug\grtestmod.vhd,hdl"
|
|
|
VALUE "<project>\..\..\lib\work\debug\cpu_disas.vhd,hdl"
|
|
|
VALUE "<project>\config.vhd,hdl"
|
|
|
VALUE "<project>\ahbrom.vhd,hdl"
|
|
|
VALUE "<project>\leon3mp.vhd,hdl"
|
|
|
VALUE "<project>\testbench.vhd,hdl"
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
LIST IncludeModuleForSimulation
|
|
|
ENDLIST
|
|
|
LIST CDBOrder
|
|
|
ENDLIST
|
|
|
LIST UserCustomizedFileList
|
|
|
ENDLIST
|
|
|
LIST OpenedFileList
|
|
|
DESIGNFLOW:
|
|
|
FILE:<project>\leon3mp.vhd,hdl
|
|
|
FILE:<project>\config.vhd,hdl
|
|
|
ACTIVE_VIEW:1
|
|
|
ENDLIST
|
|
|
|
