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LEON3 on Actel CoreMP7 board, README file v1.0
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==============================================
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* Clocking
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The leon3 design uses the Proasic3 PLL to divide the 48 MHz
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clock to a lower frequency. For this to work, jumper JP42
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must be set to enable the power to the VCCPLF. The board
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is shipped with this jumper in 'off' mode, thereby inhibiting
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the PLL.
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Some useful PLL parameters:
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FREQ MUL DIV ODIV
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20 15 9 4
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25 25 12 4
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30 45 9 8
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32 6 9 1
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34 51 9 8
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35 35 12 4
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* Serial ports
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The DSU UART is connected to serial port 1 (P3 connector)
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while the console UART (APB) is connected to P2.
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* SSRAM
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The SSRAM can be interfaced with the SSRCTRL sync-ram controller,
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or the leon2 async-sram MCTRL memory controller. If SSRCTRL is
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used, the J49 must be open to run the SSRAM in pipeline mode.
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If the MCTRL is used, J49 should be closed and zero-waitstates
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should be used in MCTRL.
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* Synthesis
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Synthesis has been done with Synplify-9.2. It is IMPERATIVE
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that retiming is NOT enabled, or a corrupt netlist will be created.
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Maximum frequency is in the range of 30 - 35 MHz, depending on
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the processor configuartion (using STD device timing).
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* Simulation
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It is not possible to simulate the test bench since the GSI SSRAM models
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do not support data pre-loading.
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