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#GRLIB=../..
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VHDLIB=../..
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SCRIPTSDIR=$(VHDLIB)/scripts/
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GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
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TOP=leon3mp
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BOARD=em-LeonLPP-A3PE3kL-v3-core1
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include $(GRLIB)/boards/$(BOARD)/Makefile.inc
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DEVICE=$(PART)-$(PACKAGE)$(SPEED)
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UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
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QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
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EFFORT=high
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XSTOPT=
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SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
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#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
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VHDLSYNFILES=
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VHDLSIMFILES= FIFO_Verif.vhd tb.vhd
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SIMTOP=testbench
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#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
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#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
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PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
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BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
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CLEAN=soft-clean
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TECHLIBS = proasic3e
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LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
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tmtc openchip hynix ihp gleichmann micron usbhc
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DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
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pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
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./amba_lcd_16x2_ctrlr \
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./general_purpose/lpp_AMR \
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./general_purpose/lpp_balise \
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./general_purpose/lpp_delay \
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./lpp_bootloader \
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./lpp_cna \
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./lpp_uart \
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./lpp_usb \
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./dsp/lpp_fft_rtax \
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FILESKIP = i2cmst.vhd \
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APB_MULTI_DIODE.vhd \
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APB_MULTI_DIODE.vhd \
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Top_MatrixSpec.vhd \
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APB_FFT.vhd \
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lpp_lfr_apbreg.vhd \
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CoreFFT.vhd
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include $(GRLIB)/bin/Makefile
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include $(GRLIB)/software/leon3/Makefile
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################## project specific targets ##########################
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