HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · boards/ICI4-3DCAM/ICI4-Main-BD.ucf

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				NET "CLK" LOC = "B10";
				NET "RESET" LOC = "A5" \| IOSTANDARD = LVTTL;
				NET "SCLK" LOC = "V22" \| IOSTANDARD = LVTTL;
				NET "GATE" LOC = "T22" \| IOSTANDARD = LVTTL;
				NET "MINF" LOC = "T21" \| IOSTANDARD = LVTTL;
				NET "MAJF" LOC = "U22" \| IOSTANDARD = LVTTL;
				NET "DATA" LOC = "V21";
				NET "DC_ADC_SCLK" LOC = "AB17";
				NET "DC_ADC_IN(0)" LOC = "AB19" \| IOSTANDARD = LVTTL;
				NET "DC_ADC_IN(1)" LOC = "AA18" \| IOSTANDARD = LVTTL;
				NET "DC_ADC_FSynch" LOC = "AB18";

				NET "CLK" LOC = "B10";
				NET "RESET" LOC = "A5" \| IOSTANDARD = LVTTL;
				NET "SCLK" LOC = "V22" \| IOSTANDARD = LVTTL;
				NET "GATE" LOC = "T22" \| IOSTANDARD = LVTTL;
				NET "MINF" LOC = "T21" \| IOSTANDARD = LVTTL;
				NET "MAJF" LOC = "U22" \| IOSTANDARD = LVTTL;
				NET "DATA" LOC = "V21";
				NET "DC_ADC_SCLK" LOC = "AB17";
				NET "DC_ADC_IN(0)" LOC = "AB19" \| IOSTANDARD = LVTTL;
				NET "DC_ADC_IN(1)" LOC = "AA18" \| IOSTANDARD = LVTTL;
				NET "DC_ADC_FSynch" LOC = "AB18";

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