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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity HeaderBuilder is
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generic(
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Data_sz : integer := 32);
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port(
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clkm : in std_logic;
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rstn : in std_logic;
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Statu : in std_logic_vector(3 downto 0);
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Matrix_Type : in std_logic_vector(1 downto 0);
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Matrix_Write : in std_logic;
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Valid : out std_logic;
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dataIN : in std_logic_vector((2*Data_sz)-1 downto 0);
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emptyIN : in std_logic_vector(1 downto 0);
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RenOUT : out std_logic_vector(1 downto 0);
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dataOUT : out std_logic_vector(Data_sz-1 downto 0);
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emptyOUT : out std_logic;
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RenIN : in std_logic;
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header : out std_logic_vector(Data_sz-1 DOWNTO 0);
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header_val : out std_logic;
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header_ack : in std_logic
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);
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end entity;
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architecture ar_HeaderBuilder of HeaderBuilder is
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signal Matrix_Param : std_logic_vector(3 downto 0);
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signal Write_reg : std_logic;
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signal Data_cpt : integer;
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signal MAX : integer;
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type etat is (idle0,idle1,pong0,pong1);
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signal ect : etat;
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begin
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process (clkm,rstn)
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begin
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if(rstn='0')then
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ect <= idle0;
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Valid <= '0';
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header_val <= '0';
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header(5 downto 0) <= (others => '0');
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Write_reg <= '0';
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Data_cpt <= 0;
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MAX <= 128;
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elsif(clkm' event and clkm='1')then
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Write_reg <= Matrix_Write;
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if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
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MAX <= 128;
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else
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MAX <= 256;
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end if;
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if(Write_reg = '0' and Matrix_Write = '1')then
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Data_cpt <= Data_cpt + 1;
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Valid <= '0';
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elsif(Data_cpt = MAX)then
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Data_cpt <= 0;
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Valid <= '1';
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header_val <= '1';
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else
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Valid <= '0';
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end if;
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case ect is
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when idle0 =>
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if(header_ack = '1')then
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header_val <= '0';
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ect <= pong0;
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end if;
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when pong0 =>
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header(1 downto 0) <= Matrix_Type;
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header(5 downto 2) <= Matrix_Param;
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if(emptyIN(0) = '1')then
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ect <= idle1;
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end if;
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when idle1 =>
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if(header_ack = '1')then
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header_val <= '0';
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ect <= pong1;
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end if;
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when pong1 =>
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header(1 downto 0) <= Matrix_Type;
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header(5 downto 2) <= Matrix_Param;
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if(emptyIN(1) = '1')then
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ect <= idle0;
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end if;
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end case;
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end if;
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end process;
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Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
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header(31 downto 6) <= (others => '0');
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with ect select
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dataOUT <= dataIN(Data_sz-1 downto 0) when pong0,
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dataIN(Data_sz-1 downto 0) when idle0,
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dataIN((2*Data_sz)-1 downto Data_sz) when pong1,
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dataIN((2*Data_sz)-1 downto Data_sz) when idle1,
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(others => '0') when others;
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with ect select
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emptyOUT <= emptyIN(0) when pong0,
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emptyIN(0) when idle0,
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emptyIN(1) when pong1,
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emptyIN(1) when idle1,
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'1' when others;
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with ect select
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RenOUT <= '1' & RenIN when pong0,
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'1' & RenIN when idle0,
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RenIN & '1' when pong1,
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RenIN & '1' when idle1,
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"11" when others;
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end architecture;
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