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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_waveform_pkg.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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USE lpp.lpp_top_lfr_pkg.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.general_purpose.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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ENTITY lpp_lfr IS
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GENERIC (
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Mem_use : INTEGER := use_RAM;
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tech : INTEGER := inferred;
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nb_data_by_buffer_size : INTEGER := 32;
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nb_snapshot_param_size : INTEGER := 32;
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delta_vector_size : INTEGER := 32;
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delta_vector_size_f0_2 : INTEGER := 7;
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pindex : INTEGER := 15;
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paddr : INTEGER := 15;
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pmask : INTEGER := 16#fff#;
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pirq_ms : INTEGER := 6;
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pirq_wfp : INTEGER := 14;
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hindex : INTEGER := 2;
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top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
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DEBUG_FORCE_DATA_DMA : INTEGER := 0;
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RTL_DESIGN_LIGHT : INTEGER := 0;
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WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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-- SAMPLE
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sample_B : IN Samples(2 DOWNTO 0);
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sample_E : IN Samples(4 DOWNTO 0);
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sample_val : IN STD_LOGIC;
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-- APB
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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-- AHB
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ahbi : IN AHB_Mst_In_Type;
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ahbo : OUT AHB_Mst_Out_Type;
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-- TIME
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coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
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fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
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--
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data_shaping_BW : OUT STD_LOGIC;
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--
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debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
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debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
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);
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END lpp_lfr;
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ARCHITECTURE beh OF lpp_lfr IS
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SIGNAL sample_s : Samples(7 DOWNTO 0);
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--
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SIGNAL data_shaping_SP0 : STD_LOGIC;
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SIGNAL data_shaping_SP1 : STD_LOGIC;
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SIGNAL data_shaping_R0 : STD_LOGIC;
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SIGNAL data_shaping_R1 : STD_LOGIC;
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SIGNAL data_shaping_R2 : STD_LOGIC;
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--
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SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
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--
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SIGNAL sample_f0_val : STD_LOGIC;
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SIGNAL sample_f1_val : STD_LOGIC;
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SIGNAL sample_f2_val : STD_LOGIC;
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SIGNAL sample_f3_val : STD_LOGIC;
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--
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SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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--
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SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0);
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SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0);
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SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0);
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SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0);
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--
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SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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-- SM
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SIGNAL ready_matrix_f0 : STD_LOGIC;
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-- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL ready_matrix_f1 : STD_LOGIC;
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SIGNAL ready_matrix_f2 : STD_LOGIC;
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SIGNAL status_ready_matrix_f0 : STD_LOGIC;
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-- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f2 : STD_LOGIC;
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SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
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SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
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SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
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-- WFP
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SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
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SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
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SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
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SIGNAL enable_f0 : STD_LOGIC;
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SIGNAL enable_f1 : STD_LOGIC;
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SIGNAL enable_f2 : STD_LOGIC;
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SIGNAL enable_f3 : STD_LOGIC;
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SIGNAL burst_f0 : STD_LOGIC;
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SIGNAL burst_f1 : STD_LOGIC;
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SIGNAL burst_f2 : STD_LOGIC;
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--SIGNAL run : STD_LOGIC;
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SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
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SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
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SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
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SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL error_buffer_full : STD_LOGIC;
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SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
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SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015
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SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
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SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
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SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
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SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
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SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL dma_grant_error : STD_LOGIC;
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SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
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BEGIN
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-----------------------------------------------------------------------------
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sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
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sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
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sample_time <= coarse_time & fine_time;
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-----------------------------------------------------------------------------
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lpp_lfr_filter_1 : lpp_lfr_filter
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GENERIC MAP (
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Mem_use => Mem_use,
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RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT)
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PORT MAP (
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sample => sample_s,
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sample_val => sample_val,
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sample_time => sample_time,
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clk => clk,
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rstn => rstn,
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data_shaping_SP0 => data_shaping_SP0,
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data_shaping_SP1 => data_shaping_SP1,
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data_shaping_R0 => data_shaping_R0,
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data_shaping_R1 => data_shaping_R1,
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data_shaping_R2 => data_shaping_R2,
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sample_f0_val => sample_f0_val,
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sample_f1_val => sample_f1_val,
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sample_f2_val => sample_f2_val,
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sample_f3_val => sample_f3_val,
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sample_f0_wdata => sample_f0_data,
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sample_f1_wdata => sample_f1_data,
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sample_f2_wdata => sample_f2_data,
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sample_f3_wdata => sample_f3_data,
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sample_f0_time => sample_f0_time,
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sample_f1_time => sample_f1_time,
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sample_f2_time => sample_f2_time,
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sample_f3_time => sample_f3_time
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);
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-----------------------------------------------------------------------------
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lpp_lfr_apbreg_1 : lpp_lfr_apbreg
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GENERIC MAP (
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nb_data_by_buffer_size => nb_data_by_buffer_size,
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nb_snapshot_param_size => nb_snapshot_param_size,
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delta_vector_size => delta_vector_size,
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delta_vector_size_f0_2 => delta_vector_size_f0_2,
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pindex => pindex,
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paddr => paddr,
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pmask => pmask,
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pirq_ms => pirq_ms,
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pirq_wfp => pirq_wfp,
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top_lfr_version => top_lfr_version)
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PORT MAP (
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HCLK => clk,
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HRESETn => rstn,
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apbi => apbi,
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apbo => apbo,
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-- run_ms => OPEN,--run_ms,
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ready_matrix_f0 => ready_matrix_f0,
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ready_matrix_f1 => ready_matrix_f1,
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ready_matrix_f2 => ready_matrix_f2,
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error_buffer_full => error_buffer_full,
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error_input_fifo_write => error_input_fifo_write,
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status_ready_matrix_f0 => status_ready_matrix_f0,
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status_ready_matrix_f1 => status_ready_matrix_f1,
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status_ready_matrix_f2 => status_ready_matrix_f2,
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matrix_time_f0 => matrix_time_f0,
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matrix_time_f1 => matrix_time_f1,
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matrix_time_f2 => matrix_time_f2,
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addr_matrix_f0 => addr_matrix_f0,
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addr_matrix_f1 => addr_matrix_f1,
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addr_matrix_f2 => addr_matrix_f2,
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length_matrix_f0 => length_matrix_f0,
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length_matrix_f1 => length_matrix_f1,
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length_matrix_f2 => length_matrix_f2,
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status_new_err => status_new_err,
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data_shaping_BW => data_shaping_BW,
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data_shaping_SP0 => data_shaping_SP0,
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data_shaping_SP1 => data_shaping_SP1,
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data_shaping_R0 => data_shaping_R0,
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data_shaping_R1 => data_shaping_R1,
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data_shaping_R2 => data_shaping_R2,
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delta_snapshot => delta_snapshot,
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delta_f0 => delta_f0,
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delta_f0_2 => delta_f0_2,
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delta_f1 => delta_f1,
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delta_f2 => delta_f2,
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nb_data_by_buffer => nb_data_by_buffer,
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nb_snapshot_param => nb_snapshot_param,
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enable_f0 => enable_f0,
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enable_f1 => enable_f1,
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enable_f2 => enable_f2,
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enable_f3 => enable_f3,
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burst_f0 => burst_f0,
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burst_f1 => burst_f1,
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burst_f2 => burst_f2,
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run => OPEN,
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start_date => start_date,
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wfp_status_buffer_ready => wfp_status_buffer_ready,
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wfp_addr_buffer => wfp_addr_buffer,
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wfp_length_buffer => wfp_length_buffer,
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wfp_ready_buffer => wfp_ready_buffer,
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wfp_buffer_time => wfp_buffer_time,
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wfp_error_buffer_full => wfp_error_buffer_full,
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-------------------------------------------------------------------------
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sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
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sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
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sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
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sample_f3_valid => sample_f3_val,
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debug_vector => apb_reg_debug_vector
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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lpp_waveform_1 : lpp_waveform
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GENERIC MAP (
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tech => tech,
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data_size => 6*16,
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nb_data_by_buffer_size => nb_data_by_buffer_size,
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nb_snapshot_param_size => nb_snapshot_param_size,
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delta_vector_size => delta_vector_size,
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delta_vector_size_f0_2 => delta_vector_size_f0_2
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)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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reg_run => '1',--run,
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reg_start_date => start_date,
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reg_delta_snapshot => delta_snapshot,
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reg_delta_f0 => delta_f0,
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reg_delta_f0_2 => delta_f0_2,
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reg_delta_f1 => delta_f1,
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reg_delta_f2 => delta_f2,
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enable_f0 => enable_f0,
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enable_f1 => enable_f1,
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enable_f2 => enable_f2,
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enable_f3 => enable_f3,
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burst_f0 => burst_f0,
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burst_f1 => burst_f1,
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burst_f2 => burst_f2,
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nb_data_by_buffer => nb_data_by_buffer,
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nb_snapshot_param => nb_snapshot_param,
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status_new_err => status_new_err,
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status_buffer_ready => wfp_status_buffer_ready,
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addr_buffer => wfp_addr_buffer,
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length_buffer => wfp_length_buffer,
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ready_buffer => wfp_ready_buffer,
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buffer_time => wfp_buffer_time,
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error_buffer_full => wfp_error_buffer_full,
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coarse_time => coarse_time,
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-- fine_time => fine_time,
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--f0
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data_f0_in_valid => sample_f0_val,
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data_f0_in => sample_f0_data,
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data_f0_time => sample_f0_time,
|
|
|
--f1
|
|
|
data_f1_in_valid => sample_f1_val,
|
|
|
data_f1_in => sample_f1_data,
|
|
|
data_f1_time => sample_f1_time,
|
|
|
--f2
|
|
|
data_f2_in_valid => sample_f2_val,
|
|
|
data_f2_in => sample_f2_data,
|
|
|
data_f2_time => sample_f2_time,
|
|
|
--f3
|
|
|
data_f3_in_valid => sample_f3_val,
|
|
|
data_f3_in => sample_f3_data,
|
|
|
data_f3_time => sample_f3_time,
|
|
|
-- OUTPUT -- DMA interface
|
|
|
|
|
|
dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
|
|
|
dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
|
|
|
dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
|
|
|
dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
|
|
|
dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
|
|
|
dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
|
|
|
dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
|
|
|
dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
|
|
|
|
|
|
);
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- Matrix Spectral
|
|
|
-----------------------------------------------------------------------------
|
|
|
sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
|
|
|
NOT(sample_f0_val) & NOT(sample_f0_val);
|
|
|
sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
|
|
|
NOT(sample_f1_val) & NOT(sample_f1_val);
|
|
|
sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
|
|
|
NOT(sample_f2_val) & NOT(sample_f2_val);
|
|
|
|
|
|
|
|
|
sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
|
|
|
sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
|
|
|
sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
lpp_lfr_ms_1 : lpp_lfr_ms
|
|
|
GENERIC MAP (
|
|
|
Mem_use => Mem_use,
|
|
|
WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
|
|
|
run => '1',--run_ms,
|
|
|
|
|
|
start_date => start_date,
|
|
|
|
|
|
coarse_time => coarse_time,
|
|
|
|
|
|
sample_f0_wen => sample_f0_wen,
|
|
|
sample_f0_wdata => sample_f0_wdata,
|
|
|
sample_f0_time => sample_f0_time,
|
|
|
sample_f1_wen => sample_f1_wen,
|
|
|
sample_f1_wdata => sample_f1_wdata,
|
|
|
sample_f1_time => sample_f1_time,
|
|
|
sample_f2_wen => sample_f2_wen,
|
|
|
sample_f2_wdata => sample_f2_wdata,
|
|
|
sample_f2_time => sample_f2_time,
|
|
|
|
|
|
--DMA
|
|
|
dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
|
|
|
dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
|
|
|
dma_fifo_ren => dma_fifo_ren(4), -- IN
|
|
|
dma_buffer_new => dma_buffer_new(4), -- OUT
|
|
|
dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
|
|
|
dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
|
|
|
dma_buffer_full => dma_buffer_full(4), -- IN
|
|
|
dma_buffer_full_err => dma_buffer_full_err(4), -- IN
|
|
|
|
|
|
|
|
|
|
|
|
--REG
|
|
|
ready_matrix_f0 => ready_matrix_f0,
|
|
|
ready_matrix_f1 => ready_matrix_f1,
|
|
|
ready_matrix_f2 => ready_matrix_f2,
|
|
|
error_buffer_full => error_buffer_full,
|
|
|
error_input_fifo_write => error_input_fifo_write,
|
|
|
|
|
|
status_ready_matrix_f0 => status_ready_matrix_f0,
|
|
|
status_ready_matrix_f1 => status_ready_matrix_f1,
|
|
|
status_ready_matrix_f2 => status_ready_matrix_f2,
|
|
|
addr_matrix_f0 => addr_matrix_f0,
|
|
|
addr_matrix_f1 => addr_matrix_f1,
|
|
|
addr_matrix_f2 => addr_matrix_f2,
|
|
|
|
|
|
length_matrix_f0 => length_matrix_f0,
|
|
|
length_matrix_f1 => length_matrix_f1,
|
|
|
length_matrix_f2 => length_matrix_f2,
|
|
|
|
|
|
matrix_time_f0 => matrix_time_f0,
|
|
|
matrix_time_f1 => matrix_time_f1,
|
|
|
matrix_time_f2 => matrix_time_f2,
|
|
|
|
|
|
debug_vector => debug_vector_ms);
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
PROCESS (clk, rstn)
|
|
|
BEGIN
|
|
|
IF rstn = '0' THEN
|
|
|
dma_fifo_data_forced_gen <= X"00040003";
|
|
|
ELSIF clk'event AND clk = '1' THEN
|
|
|
IF dma_fifo_ren(0) = '0' THEN
|
|
|
CASE dma_fifo_data_forced_gen IS
|
|
|
WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
|
|
|
WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
|
|
|
WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
|
|
|
WHEN OTHERS => NULL;
|
|
|
END CASE;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
|
|
|
dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
|
|
|
dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
|
|
|
dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
|
|
|
dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
|
|
|
|
|
|
dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
|
|
|
|
|
|
DMA_SubSystem_1 : DMA_SubSystem
|
|
|
GENERIC MAP (
|
|
|
hindex => hindex,
|
|
|
CUSTOM_DMA => 1)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
run => '1',--run_dma,
|
|
|
ahbi => ahbi,
|
|
|
ahbo => ahbo,
|
|
|
|
|
|
fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
|
|
|
fifo_data => dma_fifo_data_debug, --fifo_data,
|
|
|
fifo_ren => dma_fifo_ren, --fifo_ren,
|
|
|
|
|
|
buffer_new => dma_buffer_new, --buffer_new,
|
|
|
buffer_addr => dma_buffer_addr, --buffer_addr,
|
|
|
buffer_length => dma_buffer_length, --buffer_length,
|
|
|
buffer_full => dma_buffer_full, --buffer_full,
|
|
|
buffer_full_err => dma_buffer_full_err, --buffer_full_err,
|
|
|
grant_error => dma_grant_error,
|
|
|
debug_vector => debug_vector(8 DOWNTO 0)
|
|
|
); --grant_error);
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- OBSERVATION for SIMULATION
|
|
|
all_channel_sim: FOR I IN 0 TO 5 GENERATE
|
|
|
PROCESS (clk, rstn)
|
|
|
BEGIN -- PROCESS
|
|
|
IF rstn = '0' THEN -- asynchronous reset (active low)
|
|
|
sample_f0_data_sim(I) <= (OTHERS => '0');
|
|
|
sample_f1_data_sim(I) <= (OTHERS => '0');
|
|
|
sample_f2_data_sim(I) <= (OTHERS => '0');
|
|
|
sample_f3_data_sim(I) <= (OTHERS => '0');
|
|
|
ELSIF clk'event AND clk = '1' THEN -- rising clock edge
|
|
|
IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
|
|
|
IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
|
|
|
IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
|
|
|
IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
END GENERATE all_channel_sim;
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
END beh;
|
|
|
|