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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:16:12 03/29/2011
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-- Design Name:
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-- Module Name: top - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library grlib;
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use grlib.amba.all;
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use work.config.all;
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library gaisler;
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use gaisler.uart.all;
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use gaisler.misc.all;
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use gaisler.leon3.all;
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library techmap;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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library lpp;
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use lpp.general_purpose.all;
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use lpp.lpp_uart.all;
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entity top is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW);
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Port ( clk50MHz : in STD_LOGIC;
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reset : in STD_LOGIC;
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led : out std_logic_vector(1 downto 0);
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--
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ahbrxd : in std_ulogic;
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ahbtxd : out std_ulogic;
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urxd1 : in std_ulogic;
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utxd1 : out std_ulogic
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);
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end top;
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architecture Behavioral of top is
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--- AHB / APB
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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-- AHBUART
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signal ahbuarti: uart_in_type;
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signal ahbuarto: uart_out_type;
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signal apbuarti: uart_in_type;
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signal apbuarto: uart_out_type;
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signal rxd2 : std_ulogic;
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signal rxd1 : std_ulogic;
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signal txd1 : std_ulogic;
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signal vcc : std_logic_vector(4 downto 0);
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signal gnd : std_logic_vector(4 downto 0);
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--signal LED_rotary : std_logic_vector(7 downto 0);
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signal clkm : std_ulogic;
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signal lclk : std_ulogic;
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signal rstn : std_ulogic;
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signal clk2x : std_ulogic;
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signal rstraw : std_logic;
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signal rstneg : std_logic;
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signal lock : std_logic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
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begin
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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vcc <= (others => '1'); gnd <= (others => '0');
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
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rstneg <= reset;
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rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
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lock <= cgo.clklock;
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clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk);
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clkgen0 : clkgen -- clock generator MUL 4, DIV 5
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generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
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port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
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--------------------------------------
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--- CLK_DIVIDER ----------------------
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--------------------------------------
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clk_divider0 : Clk_divider
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generic map (OSC_freqHz => 50000000, TargetFreq_Hz => 5)
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Port map( clkm, rstn, led(1));
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-------------------------------
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--- AHB CONTROLLER ------------
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-------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
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nahbm => CFG_NCPU+CFG_AHB_UART,
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nahbs => 2)
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port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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-------------------------------
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--- AHBUART -------------------
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-------------------------------
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dcom0 : ahbuart -- AMBA AHB Serial Debug Interface
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generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
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port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
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dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, rxd2);
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dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
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ahbuarti.rxd <= rxd2;
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----------------------------------------------------------------------
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--- APB Bridge and various periherals --------------------------------
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----------------------------------------------------------------------
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apb0 : apbctrl -- AHB/APB bridge
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generic map (hindex => 1, haddr => CFG_APBADDR,nslaves => 1)
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port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
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uart1 : APB_UART
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generic map(
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pindex => 0,
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paddr => 0)
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port map(
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clk => clkm, --! Horloge du composant
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rst => rstn, --! Reset general du composant
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apbi => apbi, --! Registre de gestion des entr�es du bus
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apbo => apbo(0), --! Registre de gestion des sorties du bus
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TXD => utxd1, --! Transmission s�rie, c�t� composant
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RXD => urxd1 --! Reception s�rie, c�t� composant
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);
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----------------------------------
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--- LED --------------------------
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----------------------------------
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led(0) <= not rxd1;
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end Behavioral;
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