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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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------------------------------------------------------------------------------
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--
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-- This module implements the SyncSignal generator explained in:
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-- Data Transfer between Asynchronous Clock Domains without Pain
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-- from Markus Schutti, Markus Pfaff, Richard Hagelauer
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-- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf
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-- see page 4
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--
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity CrossDomainSyncGen is
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Port (
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reset : in STD_LOGIC;
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ClockS : in STD_LOGIC;
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ClockF : in STD_LOGIC;
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SyncSignal : out STD_LOGIC
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);
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end CrossDomainSyncGen;
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architecture AR_CrossDomainSyncGen of CrossDomainSyncGen is
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signal FFSYNC : std_logic_vector(2 downto 0);
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begin
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SyncSignal <= FFSYNC(2);
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process(reset,ClockF)
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begin
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if reset = '0' then
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FFSYNC <= (others => '0');
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elsif ClockF'event and ClockF = '1' then
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FFSYNC(0) <= ClockS;
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FFSYNC(1) <= FFSYNC(0);
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FFSYNC(2) <= FFSYNC(1);
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end if;
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end process;
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end AR_CrossDomainSyncGen;
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