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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity SPI_DAC_DRIVER is
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Generic(
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datawidth : INTEGER := 16;
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MSBFIRST : INTEGER := 1
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);
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Port (
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clk : in STD_LOGIC;
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rstn : in STD_LOGIC;
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DATA : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
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SMP_CLK : in STD_LOGIC;
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SYNC : out STD_LOGIC;
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DOUT : out STD_LOGIC;
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SCLK : out STD_LOGIC
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);
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end entity SPI_DAC_DRIVER;
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architecture behav of SPI_DAC_DRIVER is
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signal SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 downto 0):=(others=>'0');
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signal INPUTREG : STD_LOGIC_VECTOR(datawidth-1 downto 0):=(others=>'0');
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signal SMP_CLK_R : STD_LOGIC:='0';
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signal shiftcnt : INTEGER:=0;
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signal shifting : STD_LOGIC:='0';
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signal shifting_R : STD_LOGIC:='0';
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begin
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DOUT <= SHIFTREG(datawidth-1);
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MSB:IF MSBFIRST=1 GENERATE
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INPUTREG <= DATA;
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END GENERATE;
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LSB:IF MSBFIRST=0 GENERATE
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INPUTREG(datawidth-1 downto 0) <= DATA(0 to datawidth-1);
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END GENERATE;
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SCLK <= clk;
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process(clk,rstn)
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begin
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if rstn='0' then
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shifting_R <= '0';
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SMP_CLK_R <= '0';
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elsif clk'event and clk='1' then
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SMP_CLK_R <= SMP_CLK;
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shifting_R <= shifting;
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end if;
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end process;
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process(clk,rstn)
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begin
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if rstn='0' then
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shifting <= '0';
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SHIFTREG <= (others=>'0');
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SYNC <= '0';
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shiftcnt <= 0;
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elsif clk'event and clk='1' then
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if(SMP_CLK='1' and SMP_CLK_R='0') then
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SYNC <= '1';
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shifting <= '1';
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else
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SYNC <= '0';
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if shiftcnt = datawidth-1 then
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shifting <= '0';
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end if;
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end if;
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if shifting_R='1' then
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shiftcnt <= shiftcnt + 1;
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SHIFTREG <= SHIFTREG (datawidth-2 downto 0) & '0';
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else
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SHIFTREG <= INPUTREG;
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shiftcnt <= 0;
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end if;
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end if;
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end process;
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end architecture behav;
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