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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_waveform_pkg.ALL;
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USE lpp.lpp_top_lfr_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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ENTITY top_wf_picker IS
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GENERIC (
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hindex : INTEGER := 2;
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pindex : INTEGER := 15;
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paddr : INTEGER := 15;
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pmask : INTEGER := 16#fff#;
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pirq : INTEGER := 15;
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tech : INTEGER := 0;
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nb_burst_available_size : INTEGER := 11;
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nb_snapshot_param_size : INTEGER := 11;
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delta_snapshot_size : INTEGER := 16;
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delta_f2_f0_size : INTEGER := 10;
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delta_f2_f1_size : INTEGER := 10;
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ENABLE_FILTER : STD_LOGIC := '1'
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);
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PORT (
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cnv_clk : IN STD_LOGIC;
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cnv_rstn : IN STD_LOGIC;
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--
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sample : IN Samples14v(7 DOWNTO 0);
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sample_val : IN STD_LOGIC;
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-- AMBA AHB system signals
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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-- AMBA APB Slave Interface
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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-- AMBA AHB Master Interface
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AHB_Master_In : IN AHB_Mst_In_Type;
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AHB_Master_Out : OUT AHB_Mst_Out_Type;
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--
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coarse_time_0 : IN STD_LOGIC;
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--
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data_shaping_BW : OUT STD_LOGIC
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);
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END top_wf_picker;
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ARCHITECTURE tb OF top_wf_picker IS
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SIGNAL ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL ready_matrix_f1 : STD_LOGIC;
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SIGNAL ready_matrix_f2 : STD_LOGIC;
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SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL error_bad_component_error : STD_LOGIC;
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SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f2 : STD_LOGIC;
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SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL status_error_bad_component_error : STD_LOGIC;
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SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
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SIGNAL config_active_interruption_onError : STD_LOGIC;
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SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL data_shaping_SP0 : STD_LOGIC;
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SIGNAL data_shaping_SP1 : STD_LOGIC;
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SIGNAL data_shaping_R0 : STD_LOGIC;
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SIGNAL data_shaping_R1 : STD_LOGIC;
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SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
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SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
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SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
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SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
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SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
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SIGNAL enable_f0 : STD_LOGIC;
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SIGNAL enable_f1 : STD_LOGIC;
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SIGNAL enable_f2 : STD_LOGIC;
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SIGNAL enable_f3 : STD_LOGIC;
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SIGNAL burst_f0 : STD_LOGIC;
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SIGNAL burst_f1 : STD_LOGIC;
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SIGNAL burst_f2 : STD_LOGIC;
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SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
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SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
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SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
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SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
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SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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CONSTANT ChanelCount : INTEGER := 8;
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CONSTANT ncycle_cnv_high : INTEGER := 40;
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CONSTANT ncycle_cnv : INTEGER := 250;
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SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0);
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BEGIN
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ready_matrix_f0_0 <= '0';
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ready_matrix_f0_1 <= '0';
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ready_matrix_f1 <= '0';
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ready_matrix_f2 <= '0';
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error_anticipating_empty_fifo <= '0';
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error_bad_component_error <= '0';
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debug_reg <= (OTHERS => '0');
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lpp_top_apbreg_1 : lpp_top_apbreg
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GENERIC MAP (
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nb_burst_available_size => nb_burst_available_size,
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nb_snapshot_param_size => nb_snapshot_param_size,
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delta_snapshot_size => delta_snapshot_size,
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delta_f2_f0_size => delta_f2_f0_size,
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delta_f2_f1_size => delta_f2_f1_size,
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pindex => pindex,
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paddr => paddr,
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pmask => pmask,
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pirq => pirq)
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PORT MAP (
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HCLK => HCLK,
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HRESETn => HRESETn,
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apbi => apbi,
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apbo => apbo,
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ready_matrix_f0_0 => ready_matrix_f0_0,
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ready_matrix_f0_1 => ready_matrix_f0_1,
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ready_matrix_f1 => ready_matrix_f1,
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ready_matrix_f2 => ready_matrix_f2,
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error_anticipating_empty_fifo => error_anticipating_empty_fifo,
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error_bad_component_error => error_bad_component_error,
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debug_reg => debug_reg,
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status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
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status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
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status_ready_matrix_f1 => status_ready_matrix_f1,
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status_ready_matrix_f2 => status_ready_matrix_f2,
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status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
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status_error_bad_component_error => status_error_bad_component_error,
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config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
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config_active_interruption_onError => config_active_interruption_onError,
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addr_matrix_f0_0 => addr_matrix_f0_0,
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addr_matrix_f0_1 => addr_matrix_f0_1,
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addr_matrix_f1 => addr_matrix_f1,
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addr_matrix_f2 => addr_matrix_f2,
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status_full => status_full,
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status_full_ack => status_full_ack,
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status_full_err => status_full_err,
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status_new_err => status_new_err,
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data_shaping_BW => data_shaping_BW,
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data_shaping_SP0 => data_shaping_SP0,
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data_shaping_SP1 => data_shaping_SP1,
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data_shaping_R0 => data_shaping_R0,
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data_shaping_R1 => data_shaping_R1,
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delta_snapshot => delta_snapshot,
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delta_f2_f1 => delta_f2_f1,
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delta_f2_f0 => delta_f2_f0,
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nb_burst_available => nb_burst_available,
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nb_snapshot_param => nb_snapshot_param,
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enable_f0 => enable_f0,
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enable_f1 => enable_f1,
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enable_f2 => enable_f2,
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enable_f3 => enable_f3,
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burst_f0 => burst_f0,
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burst_f1 => burst_f1,
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burst_f2 => burst_f2,
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addr_data_f0 => addr_data_f0,
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addr_data_f1 => addr_data_f1,
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addr_data_f2 => addr_data_f2,
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addr_data_f3 => addr_data_f3);
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--DIGITAL_acquisition : AD7688_drvr_sync
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-- GENERIC MAP (
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-- ChanelCount => ChanelCount,
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-- ncycle_cnv_high => ncycle_cnv_high,
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-- ncycle_cnv => ncycle_cnv)
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-- PORT MAP (
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-- cnv_clk => cnv_clk, --
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-- cnv_rstn => cnv_rstn, --
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-- cnv_run => cnv_run, --
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-- cnv => cnv, --
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-- sck => sck, --
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-- sdo => sdo(ChanelCount-1 DOWNTO 0), --
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-- sample => sample,
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-- sample_val => sample_val);
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all_channel: FOR i IN 7 DOWNTO 0 GENERATE
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sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
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END GENERATE all_channel;
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wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
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lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
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GENERIC MAP (
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hindex => hindex,
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nb_burst_available_size => nb_burst_available_size,
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nb_snapshot_param_size => nb_snapshot_param_size,
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delta_snapshot_size => delta_snapshot_size,
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delta_f2_f0_size => delta_f2_f0_size,
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delta_f2_f1_size => delta_f2_f1_size,
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tech => tech,
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Mem_use => use_RAM
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)
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PORT MAP (
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sample => sample_s,
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sample_val => sample_val,
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cnv_clk => HCLK,--cnv_clk,
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cnv_rstn => HRESETn,--cnv_rstn,
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clk => HCLK,
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rstn => HRESETn,
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sample_f0_wen => sample_f0_wen,
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sample_f0_wdata => sample_f0_wdata,
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sample_f1_wen => sample_f1_wen,
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sample_f1_wdata => sample_f1_wdata,
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sample_f2_wen => sample_f2_wen,
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sample_f2_wdata => sample_f2_wdata,
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sample_f3_wen => sample_f3_wen,
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sample_f3_wdata => sample_f3_wdata,
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AHB_Master_In => AHB_Master_In,
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AHB_Master_Out => AHB_Master_Out,
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coarse_time_0 => coarse_time_0,
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data_shaping_SP0 => data_shaping_SP0,
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data_shaping_SP1 => data_shaping_SP1,
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data_shaping_R0 => data_shaping_R0,
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data_shaping_R1 => data_shaping_R1,
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delta_snapshot => delta_snapshot,
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delta_f2_f1 => delta_f2_f1,
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delta_f2_f0 => delta_f2_f0,
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enable_f0 => enable_f0,
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enable_f1 => enable_f1,
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enable_f2 => enable_f2,
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enable_f3 => enable_f3,
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burst_f0 => burst_f0,
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burst_f1 => burst_f1,
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burst_f2 => burst_f2,
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nb_burst_available => nb_burst_available,
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nb_snapshot_param => nb_snapshot_param,
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status_full => status_full,
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status_full_ack => status_full_ack,
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status_full_err => status_full_err,
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status_new_err => status_new_err,
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addr_data_f0 => addr_data_f0,
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addr_data_f1 => addr_data_f1,
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addr_data_f2 => addr_data_f2,
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addr_data_f3 => addr_data_f3);
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END GENERATE wf_picker_with_filter;
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wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
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lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
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GENERIC MAP (
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hindex => hindex,
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nb_burst_available_size => nb_burst_available_size,
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nb_snapshot_param_size => nb_snapshot_param_size,
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delta_snapshot_size => delta_snapshot_size,
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delta_f2_f0_size => delta_f2_f0_size,
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delta_f2_f1_size => delta_f2_f1_size,
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tech => tech
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)
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PORT MAP (
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sample => sample_s,
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sample_val => sample_val,
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cnv_clk => cnv_clk,
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cnv_rstn => cnv_rstn,
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clk => HCLK,
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rstn => HRESETn,
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sample_f0_wen => sample_f0_wen,
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sample_f0_wdata => sample_f0_wdata,
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sample_f1_wen => sample_f1_wen,
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sample_f1_wdata => sample_f1_wdata,
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sample_f2_wen => sample_f2_wen,
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sample_f2_wdata => sample_f2_wdata,
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sample_f3_wen => sample_f3_wen,
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sample_f3_wdata => sample_f3_wdata,
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AHB_Master_In => AHB_Master_In,
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AHB_Master_Out => AHB_Master_Out,
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coarse_time_0 => coarse_time_0,
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data_shaping_SP0 => data_shaping_SP0,
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data_shaping_SP1 => data_shaping_SP1,
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data_shaping_R0 => data_shaping_R0,
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data_shaping_R1 => data_shaping_R1,
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delta_snapshot => delta_snapshot,
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delta_f2_f1 => delta_f2_f1,
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delta_f2_f0 => delta_f2_f0,
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enable_f0 => enable_f0,
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enable_f1 => enable_f1,
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enable_f2 => enable_f2,
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enable_f3 => enable_f3,
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burst_f0 => burst_f0,
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burst_f1 => burst_f1,
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burst_f2 => burst_f2,
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nb_burst_available => nb_burst_available,
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nb_snapshot_param => nb_snapshot_param,
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status_full => status_full,
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status_full_ack => status_full_ack,
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status_full_err => status_full_err,
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status_new_err => status_new_err,
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addr_data_f0 => addr_data_f0,
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addr_data_f1 => addr_data_f1,
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addr_data_f2 => addr_data_f2,
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addr_data_f3 => addr_data_f3);
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END GENERATE wf_picker_without_filter;
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END tb;
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