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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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library lpp;
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use lpp.lpp_uart.all;
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--! \brief A general purpose UART with automatic baudrate
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--!
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--! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
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entity UART is
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generic(Data_sz : integer := 8); --! Data width
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port(
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clk : in std_logic; --! System clock
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reset : in std_logic; --! System reset
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TXD : out std_logic; --! UART Transmission pin
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RXD : in std_logic; --! UART Reception pin
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Capture : in std_logic; --! Automatic baudrate module reset
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NwDat : out std_logic; --! New data flag, means that a new data have been received by the UART
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ACK : in std_logic; --! Acknowledge flag to clear NwDat flag
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Send : in std_logic; --! To send a data you have to set this flag
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Sended : out std_logic; --! When this flag is set you can sed a new data
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BTrigger : out std_logic_vector(11 downto 0); --! Baudrate generator current value, could be usefull if you whant to know the current value of the baudrate or of the oscillator (it suppose that you know baudrate)
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RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Current read word
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WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Put here the word you whant to send
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);
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end entity;
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architecture ar_UART of UART is
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signal Bclk : std_logic;
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signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
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signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
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signal Take : std_logic;
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signal Taken : std_logic;
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signal Taken_reg : std_logic;
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constant Dummy : std_logic_vector(Data_sz+1 downto 0) := (others => '1');
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begin
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NwDat <= '0' when (ack = '1') else '1' when (Taken_reg='0' and Taken='1');
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WDATA_int <= '1' & WDATA & '0';
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BaudGenerator : BaudGen
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port map(clk,reset,Capture,Bclk,RXD,BTrigger);
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RX_REG : Shift_Reg
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generic map(Data_sz+2)
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port map(Bclk,RXD,open,Take,Taken,Dummy,RDATA_int);
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TX_REG : Shift_Reg
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generic map(Data_sz+2)
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port map(Bclk,Dummy(0),TXD,Send,Sended,WDATA_int,open);
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process(clk,reset)
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begin
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if(reset ='0')then
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Take <= '0';
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elsif(clk'event and clk ='1')then
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Taken_reg <= Taken;
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if(RXD ='0' and Taken ='1')then
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Take <= '1';
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elsif(Taken ='0')then
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Take <= '0';
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end if;
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if (Taken_reg ='0' and Taken ='1') then
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RDATA <= RDATA_int(8 downto 1);
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end if;
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end if;
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end process;
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end architecture;
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