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new_design -name "leon3mp" -family "Spartan3E"
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set_device -die "xc3s1600e" -package " " -speed "-4" -voltage "1.5" -iostd "LVTTL" -jtag "yes" -probe "yes" -trst "yes" -temprange "" -voltrange ""
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if {[file exist leon3mp.pdc]} {
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import_source -format "edif" -edif_flavor "GENERIC" -merge_physical "no" -merge_timing "no" {synplify/leon3mp.edf} -format "pdc" -abort_on_error "no" {leon3mp.pdc}
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} else {
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import_source -format "edif" -edif_flavor "GENERIC" -merge_physical "no" -merge_timing "no" {synplify/leon3mp.edf}
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}
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compile -combine_register 1
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if {[file exist ]} {
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import_aux -format "pdc" -abort_on_error "no" {}
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pin_commit
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} else {
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puts "WARNING: No PDC file imported."
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}
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if {[file exist ]} {
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import_aux -format "sdc" -merge_timing "no" {}
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} else {
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puts "WARNING: No SDC file imported."
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}
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save_design {leon3mp.adb}
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report -type status {./actel/report_status_pre.log}
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layout -timing_driven -incremental "OFF"
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save_design {leon3mp.adb}
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backannotate -dir {./actel} -name "leon3mp" -format "SDF" -language "VHDL93" -netlist
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report -type "timer" -analysis "max" -print_summary "yes" -use_slack_threshold "no" -print_paths "yes" -max_paths 100 -max_expanded_paths 5 -include_user_sets "yes" -include_pin_to_pin "yes" -select_clock_domains "no" {./actel/report_timer_max.txt}
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report -type "timer" -analysis "min" -print_summary "yes" -use_slack_threshold "no" -print_paths "yes" -max_paths 100 -max_expanded_paths 5 -include_user_sets "yes" -include_pin_to_pin "yes" -select_clock_domains "no" {./actel/report_timer_min.txt}
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report -type "pin" -listby "name" {./actel/report_pin_name.log}
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report -type "pin" -listby "number" {./actel/report_pin_number.log}
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report -type "datasheet" {./actel/report_datasheet.txt}
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export -format "pdb" -feature "prog_fpga" -io_state "Tri-State" {./actel/leon3mp.pdb}
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export -format log -diagnostic {./actel/report_log.log}
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report -type status {./actel/report_status_post.log}
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save_design {leon3mp.adb}
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