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# GRLIB Makefile generated settings
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set design leon3mp
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set pnc
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set device
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set package
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set top_hdl
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### Project Settings
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#
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# The parameters in this section are for documentation purposes mostly
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# and can be changed by the user without affecting synthesis results
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# Multi-word strings (e.g. eASIC Corp) must be enwrapped in double
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# quotes, so "eASIC Corp."
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# project: string; Project name
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set project "leon3"
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# company: string; Company name
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set company "gaisler"
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# designer: string; Designer name
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set designer ""
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# email: string; Designer's email address
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set email "${designer}@${company}.com"
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# email_notification: enumerated [on,off]
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# When 'on' CDB sends an email to the designer's email address
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# with the status of the last run and the log file attached
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set email_notification off
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### Design
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#
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# The parameters in this section define the eASIC Structured ASIC
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# the design will be implemented on
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# pnc: number; Part Number Code, unique project identifier
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# provided by eASIC
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#set pnc 50123
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# design: string; Top Level name
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#set design leon3mp
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# device: enumerated [NX750,NX1500,NX2500,NX4000,NX5000]
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# Device selects the eASIC Structured ASIC platform
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#set device NX1500
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# package: string; package for selected device
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#
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#set package FC480
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# device_type: enumerated [sl,vl]
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# sl: SRAM configured Lookup table device
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# vl: Via configured Lookup table device
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set device_type sl
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# technology; enumerated [std,hp]
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# std: 1.2V standard device
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# hp : 1.3V high performance device
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set technology std
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### Flow
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#
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# The parameters in this section provide various options
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# to guide the synthesis flow
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# fsm_optimization: enumerated [on,off]
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# fsm_encoding : enumerated [auto,binary,gray,one_hot]
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# These parameters turn on/off Finite State Machine recoding with the
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# method defined by 'fsm_encoding'.
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# Turning on this option can result in smaller and/or faster FSM
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# implementations, but may lead to formal verification errors
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set fsm_optimization off
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set fsm_encoding auto
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# boolean_mapper: enumerated [on,off]
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# Turn on/off Magma boolean mapper technology
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# Turning on this option generally yields a smaller and faster design
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set boolean_mapper on
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# use_rtbuf: enumerated [on,off]
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# Turn on/off long net buffering using high-drive buffers (rtbuf)
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# Setting use_rtbuf to 'off' disables 'fix fj90 rtbuf'
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set use_rtbuf on
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# effort: enumerated [low,medium,high]; (area) synthesis effort
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set effort medium
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# timing_effort: enumerated [low,medium,high]; timing effort
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set timing_effort medium
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# timing_slack: real; initial positive timing slack target
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set timing_slack 1n
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# clock_effort: enumerated [low,high]
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# Should be set to 'low' for 2008 Magma releases, can be set to 'high' for older releases
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set clock_effort low
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# utilization: real; area utilization
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# Maximum area utilization during placement. Typical values range
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# from 0.7 to 1.0. Lower values may improve timing or relax placement
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# effort, but lead to less area efficient implementations.
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set utilization 0.8
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# clone_ff: enumerated [on,off]
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# Turn on/off replication of flipflops to drive large loads.
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# It is recommended to set this parameter to 'on'.
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# Set it to 'off' if encountering formal verification issues.
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set clone_ff on
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# fanout_limit: integer;
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# fanout_strict: enumerated [strict,noworse]
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# Sets the maximum fanout per cell (fanout_limit) and how the
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# synthesis tool resolves the fanout; always buffer if the load is
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# higher than the fanout (strict), or only buffer if the load is
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# higher than the fanout AND buffering doesn't affect timing (noworse)
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set fanout_limit 10
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set fanout_strict strict
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# timing_paths: integer
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# Sets the number of timing paths reported during the various timing
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# analysis reports
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set timing_paths 10
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### Directories
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#
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# The parameters in this section set multiple directories.
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# There should be no need to change any of the following parameters
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# proj_rootdir: string
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# Sets the path to the project root, as seen from the 'run' directory
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set proj_rootdir ../../..
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# srcdir: string
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# Sets the directory containing user files (e.g. design and constraints)
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# This typically points to 'src'
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set srcdir $proj_rootdir/src
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# rtldir: string
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# Sets the directory containing RTL files
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# This typically points to 'src/rtl'
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set rtldir $srcdir/rtl
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# constraintsdir: string
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# Sets the directory containing design constraints (.sdc, .pad) files
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# This typically points to 'src/constraints'
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set constraintsdir $srcdir/constraints
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# snap: enumerated [on|off]
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# Enables or disabled Magma synthesis snap-shot generation.
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# snap must be on if the CDB 'start_at' option is to be used.
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set snap on
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# volcano_compression: enumerated [none,min,med,max]
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# Sets the Magma library volcano compression level
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set volcano_compression none
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### Constraints
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#
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# The parameters in this section set/point to synthesis constraints
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# pad_file: string
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# Points to an eWizard generated file containing pad and macro placement commands
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# Typically points to 'src/constraints/<design>.pad
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set pad_file $constraintsdir/${design}.pad
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# sdc_file: string
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# Points to a user generated file containing timing constraints in
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# Synopsys Design Constraints (sdc) format.
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# Typically points to 'src/constraints/<design>.sdc
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set sdc_file $constraintsdir/${design}.sdc
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# verilog2k: enumerated [on|off]
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# Enables/disabled Verilog2001 support
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set verilog2k on
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# undriven: enumerated [0,1,X,U,reset]
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# Sets the physical synthesis tool's behaviour with regards to undriven
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# pins. By default this is set to 'U', meaning leave undriven pins
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# floating so they can be detected and fixed in RTL.
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set undriven U
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# topfile: string
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# The name of the file containing the top level RTL module
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#set topfile $rtldir/<top file>
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#if {[regexp {\.v$} $topfile]} {set top_hdl verilog} else {set top_hdl vhdl}
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### Design files
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#
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set includeList {}
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set defineList {}
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set netlistList {}
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set vhdllibList {}
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set read_netlist {}
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set read_rtl {}
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set read_plan {}
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# GRLIB Makefile generated HDL list
|
|
|
set vhdlList {
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{grlib ../../../../../../lib/grlib/stdlib/version.vhd ../../../../../../lib/grlib/stdlib/config.vhd ../../../../../../lib/grlib/stdlib/stdlib.vhd ../../../../../../lib/grlib/sparc/sparc.vhd ../../../../../../lib/grlib/sparc/sparc_disas.vhd ../../../../../../lib/grlib/sparc/cpu_disas.vhd ../../../../../../lib/grlib/modgen/multlib.vhd ../../../../../../lib/grlib/modgen/leaves.vhd ../../../../../../lib/grlib/amba/amba.vhd ../../../../../../lib/grlib/amba/devices.vhd ../../../../../../lib/grlib/amba/defmst.vhd ../../../../../../lib/grlib/amba/apbctrl.vhd ../../../../../../lib/grlib/amba/ahbctrl.vhd ../../../../../../lib/grlib/amba/dma2ahb_pkg.vhd ../../../../../../lib/grlib/amba/dma2ahb.vhd}
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|
|
{techmap ../../../../../../lib/techmap/gencomp/gencomp.vhd ../../../../../../lib/techmap/gencomp/netcomp.vhd ../../../../../../lib/techmap/inferred/memory_inferred.vhd ../../../../../../lib/techmap/inferred/ddr_inferred.vhd ../../../../../../lib/techmap/inferred/mul_inferred.vhd ../../../../../../lib/techmap/inferred/ddr_phy_inferred.vhd ../../../../../../lib/techmap/dw02/mul_dw_gen.vhd ../../../../../../lib/techmap/maps/allclkgen.vhd ../../../../../../lib/techmap/maps/allddr.vhd ../../../../../../lib/techmap/maps/allmem.vhd ../../../../../../lib/techmap/maps/allpads.vhd ../../../../../../lib/techmap/maps/alltap.vhd ../../../../../../lib/techmap/maps/clkgen.vhd ../../../../../../lib/techmap/maps/clkmux.vhd ../../../../../../lib/techmap/maps/clkand.vhd ../../../../../../lib/techmap/maps/ddr_ireg.vhd ../../../../../../lib/techmap/maps/ddr_oreg.vhd ../../../../../../lib/techmap/maps/ddrphy.vhd ../../../../../../lib/techmap/maps/syncram.vhd ../../../../../../lib/techmap/maps/syncram64.vhd ../../../../../../lib/techmap/maps/syncram_2p.vhd ../../../../../../lib/techmap/maps/syncram_dp.vhd ../../../../../../lib/techmap/maps/syncfifo.vhd ../../../../../../lib/techmap/maps/regfile_3p.vhd ../../../../../../lib/techmap/maps/tap.vhd ../../../../../../lib/techmap/maps/techbuf.vhd ../../../../../../lib/techmap/maps/nandtree.vhd ../../../../../../lib/techmap/maps/clkpad.vhd ../../../../../../lib/techmap/maps/clkpad_ds.vhd ../../../../../../lib/techmap/maps/inpad.vhd ../../../../../../lib/techmap/maps/inpad_ds.vhd ../../../../../../lib/techmap/maps/iodpad.vhd ../../../../../../lib/techmap/maps/iopad.vhd ../../../../../../lib/techmap/maps/iopad_ds.vhd ../../../../../../lib/techmap/maps/lvds_combo.vhd ../../../../../../lib/techmap/maps/odpad.vhd ../../../../../../lib/techmap/maps/outpad.vhd ../../../../../../lib/techmap/maps/outpad_ds.vhd ../../../../../../lib/techmap/maps/toutpad.vhd ../../../../../../lib/techmap/maps/skew_outpad.vhd ../../../../../../lib/techmap/maps/grspwc_net.vhd ../../../../../../lib/techmap/maps/grspwc2_net.vhd ../../../../../../lib/techmap/maps/grlfpw_net.vhd ../../../../../../lib/techmap/maps/grfpw_net.vhd ../../../../../../lib/techmap/maps/mul_61x61.vhd ../../../../../../lib/techmap/maps/cpu_disas_net.vhd ../../../../../../lib/techmap/maps/ringosc.vhd ../../../../../../lib/techmap/maps/system_monitor.vhd ../../../../../../lib/techmap/maps/grgates.vhd ../../../../../../lib/techmap/maps/inpad_ddr.vhd ../../../../../../lib/techmap/maps/outpad_ddr.vhd ../../../../../../lib/techmap/maps/iopad_ddr.vhd ../../../../../../lib/techmap/maps/syncram128bw.vhd ../../../../../../lib/techmap/maps/syncram128.vhd ../../../../../../lib/techmap/maps/syncram156bw.vhd}
|
|
|
{eth ../../../../../../lib/eth/comp/ethcomp.vhd ../../../../../../lib/eth/core/greth_pkg.vhd ../../../../../../lib/eth/core/eth_rstgen.vhd ../../../../../../lib/eth/core/eth_ahb_mst.vhd ../../../../../../lib/eth/core/greth_tx.vhd ../../../../../../lib/eth/core/greth_rx.vhd ../../../../../../lib/eth/core/grethc.vhd ../../../../../../lib/eth/wrapper/greth_gen.vhd ../../../../../../lib/eth/wrapper/greth_gbit_gen.vhd}
|
|
|
{gaisler ../../../../../../lib/gaisler/arith/arith.vhd ../../../../../../lib/gaisler/arith/mul32.vhd ../../../../../../lib/gaisler/arith/div32.vhd ../../../../../../lib/gaisler/memctrl/memctrl.vhd ../../../../../../lib/gaisler/memctrl/sdctrl.vhd ../../../../../../lib/gaisler/memctrl/sdctrl64.vhd ../../../../../../lib/gaisler/memctrl/sdmctrl.vhd ../../../../../../lib/gaisler/memctrl/srctrl.vhd ../../../../../../lib/gaisler/memctrl/spimctrl.vhd ../../../../../../lib/gaisler/leon3/leon3.vhd ../../../../../../lib/gaisler/leon3/mmuconfig.vhd ../../../../../../lib/gaisler/leon3/mmuiface.vhd ../../../../../../lib/gaisler/leon3/libmmu.vhd ../../../../../../lib/gaisler/leon3/libiu.vhd ../../../../../../lib/gaisler/leon3/libcache.vhd ../../../../../../lib/gaisler/leon3/libproc3.vhd ../../../../../../lib/gaisler/leon3/cachemem.vhd ../../../../../../lib/gaisler/leon3/mmu_icache.vhd ../../../../../../lib/gaisler/leon3/mmu_dcache.vhd ../../../../../../lib/gaisler/leon3/mmu_acache.vhd ../../../../../../lib/gaisler/leon3/mmutlbcam.vhd ../../../../../../lib/gaisler/leon3/mmulrue.vhd ../../../../../../lib/gaisler/leon3/mmulru.vhd ../../../../../../lib/gaisler/leon3/mmutlb.vhd ../../../../../../lib/gaisler/leon3/mmutw.vhd ../../../../../../lib/gaisler/leon3/mmu.vhd ../../../../../../lib/gaisler/leon3/mmu_cache.vhd ../../../../../../lib/gaisler/leon3/cpu_disasx.vhd ../../../../../../lib/gaisler/leon3/iu3.vhd ../../../../../../lib/gaisler/leon3/grfpwx.vhd ../../../../../../lib/gaisler/leon3/mfpwx.vhd ../../../../../../lib/gaisler/leon3/grlfpwx.vhd ../../../../../../lib/gaisler/leon3/tbufmem.vhd ../../../../../../lib/gaisler/leon3/dsu3x.vhd ../../../../../../lib/gaisler/leon3/dsu3.vhd ../../../../../../lib/gaisler/leon3/proc3.vhd ../../../../../../lib/gaisler/leon3/leon3s.vhd ../../../../../../lib/gaisler/leon3/leon3cg.vhd ../../../../../../lib/gaisler/leon3/irqmp.vhd ../../../../../../lib/gaisler/leon3/grfpwxsh.vhd ../../../../../../lib/gaisler/leon3/grfpushwx.vhd ../../../../../../lib/gaisler/leon3/leon3sh.vhd ../../../../../../lib/gaisler/misc/misc.vhd ../../../../../../lib/gaisler/misc/rstgen.vhd ../../../../../../lib/gaisler/misc/gptimer.vhd ../../../../../../lib/gaisler/misc/ahbram.vhd ../../../../../../lib/gaisler/misc/ahbdpram.vhd ../../../../../../lib/gaisler/misc/ahbtrace.vhd ../../../../../../lib/gaisler/misc/ahbtrace_mb.vhd ../../../../../../lib/gaisler/misc/ahbmst.vhd ../../../../../../lib/gaisler/misc/grgpio.vhd ../../../../../../lib/gaisler/misc/ahbstat.vhd ../../../../../../lib/gaisler/misc/logan.vhd ../../../../../../lib/gaisler/misc/apbps2.vhd ../../../../../../lib/gaisler/misc/charrom_package.vhd ../../../../../../lib/gaisler/misc/charrom.vhd ../../../../../../lib/gaisler/misc/apbvga.vhd ../../../../../../lib/gaisler/misc/svgactrl.vhd ../../../../../../lib/gaisler/misc/i2cmst_gen.vhd ../../../../../../lib/gaisler/misc/spictrl.vhd ../../../../../../lib/gaisler/misc/i2cslv.vhd ../../../../../../lib/gaisler/misc/wild.vhd ../../../../../../lib/gaisler/misc/wild2ahb.vhd ../../../../../../lib/gaisler/misc/grsysmon.vhd ../../../../../../lib/gaisler/misc/gracectrl.vhd ../../../../../../lib/gaisler/misc/grgpreg.vhd ../../../../../../lib/gaisler/misc/ahbmst2.vhd ../../../../../../lib/gaisler/misc/ahb_mst_iface.vhd ../../../../../../lib/gaisler/net/net.vhd ../../../../../../lib/gaisler/uart/uart.vhd ../../../../../../lib/gaisler/uart/libdcom.vhd ../../../../../../lib/gaisler/uart/apbuart.vhd ../../../../../../lib/gaisler/uart/dcom.vhd ../../../../../../lib/gaisler/uart/dcom_uart.vhd ../../../../../../lib/gaisler/uart/ahbuart.vhd ../../../../../../lib/gaisler/jtag/jtag.vhd ../../../../../../lib/gaisler/jtag/libjtagcom.vhd ../../../../../../lib/gaisler/jtag/jtagcom.vhd ../../../../../../lib/gaisler/jtag/ahbjtag.vhd ../../../../../../lib/gaisler/jtag/ahbjtag_bsd.vhd ../../../../../../lib/gaisler/greth/ethernet_mac.vhd ../../../../../../lib/gaisler/greth/greth.vhd ../../../../../../lib/gaisler/greth/greth_gbit.vhd ../../../../../../lib/gaisler/greth/grethm.vhd ../../../../../../lib/gaisler/ddr/ddr_phy.vhd ../../../../../../lib/gaisler/ddr/ddrsp16a.vhd ../../../../../../lib/gaisler/ddr/ddrsp32a.vhd ../../../../../../lib/gaisler/ddr/ddrsp64a.vhd ../../../../../../lib/gaisler/ddr/ddrspa.vhd ../../../../../../lib/gaisler/ddr/ddr2spa.vhd ../../../../../../lib/gaisler/ddr/ddr2buf.vhd ../../../../../../lib/gaisler/ddr/ddr2spax.vhd ../../../../../../lib/gaisler/ddr/ddr2spax_ahb.vhd ../../../../../../lib/gaisler/ddr/ddr2spax_ddr.vhd}
|
|
|
{esa ../../../../../../lib/esa/memoryctrl/memoryctrl.vhd ../../../../../../lib/esa/memoryctrl/mctrl.vhd}
|
|
|
{lpp ../../../../../../lib/lpp/./general_purpose/Adder.vhd ../../../../../../lib/lpp/./general_purpose/ADDRcntr.vhd ../../../../../../lib/lpp/./general_purpose/ALU.vhd ../../../../../../lib/lpp/./general_purpose/Clk_divider.vhd ../../../../../../lib/lpp/./general_purpose/general_purpose.vhd ../../../../../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd ../../../../../../lib/lpp/./general_purpose/MAC_MUX2.vhd ../../../../../../lib/lpp/./general_purpose/MAC_MUX.vhd ../../../../../../lib/lpp/./general_purpose/MAC_REG.vhd ../../../../../../lib/lpp/./general_purpose/MAC.vhd ../../../../../../lib/lpp/./general_purpose/Multiplier.vhd ../../../../../../lib/lpp/./general_purpose/MUX2.vhd ../../../../../../lib/lpp/./general_purpose/REG.vhd ../../../../../../lib/lpp/./general_purpose/Shifter.vhd ../../../../../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd ../../../../../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd ../../../../../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd ../../../../../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd ../../../../../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd ../../../../../../lib/lpp/./lpp_CNA_amba/APB_CNA.vhd ../../../../../../lib/lpp/./lpp_CNA_amba/clock.vhd ../../../../../../lib/lpp/./lpp_CNA_amba/CNA_TabloC.vhd ../../../../../../lib/lpp/./lpp_CNA_amba/Convertisseur_config.vhd ../../../../../../lib/lpp/./lpp_CNA_amba/GeneSYNC_flag.vhd ../../../../../../lib/lpp/./lpp_CNA_amba/lpp_CNA_amba.vhd ../../../../../../lib/lpp/./lpp_CNA_amba/Serialize.vhd ../../../../../../lib/lpp/./lpp_uart/APB_UART.vhd ../../../../../../lib/lpp/./lpp_uart/BaudGen.vhd ../../../../../../lib/lpp/./lpp_uart/lpp_uart.vhd ../../../../../../lib/lpp/./lpp_uart/Shift_REG.vhd ../../../../../../lib/lpp/./lpp_uart/UART.vhd ../../../../../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd ../../../../../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd ../../../../../../lib/lpp/./lpp_amba/lpp_amba.vhd ../../../../../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd ../../../../../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd ../../../../../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd ../../../../../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd ../../../../../../lib/lpp/./dsp/iir_filter/FILTER.vhd ../../../../../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd ../../../../../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd ../../../../../../lib/lpp/./dsp/iir_filter/iir_filter.vhd ../../../../../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd ../../../../../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd ../../../../../../lib/lpp/./dsp/iir_filter/RAM.vhd ../../../../../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd ../../../../../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd ../../../../../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd ../../../../../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd ../../../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd ../../../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd ../../../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd ../../../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd ../../../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd ../../../../../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd}
|
|
|
{work ../../../../config.vhd ../../../../ahbrom.vhd ../../../../leon3mp.vhd}
|
|
|
}
|
|
|
set verilogList {
|
|
|
}
|
|
|
|
