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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- IIR_CEL_CTRLR.vhd
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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library lpp;
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use lpp.iir_filter.all;
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use lpp.FILTERcfg.all;
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use lpp.general_purpose.all;
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--TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
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entity IIR_CEL_CTRLR is
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generic(Sample_SZ : integer := 16);
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port(
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reset : in std_logic;
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clk : in std_logic;
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sample_clk : in std_logic;
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sample_in : in samplT;
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sample_out : out samplT;
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virg_pos : in integer;
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coefs : in coefs_celsT
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);
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end IIR_CEL_CTRLR;
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architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
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signal smpl_clk_old : std_logic := '0';
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signal WD_sel : std_logic := '0';
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signal Read : std_logic := '0';
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signal SVG_ADDR : std_logic := '0';
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signal count : std_logic := '0';
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signal Write : std_logic := '0';
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signal WADDR_sel : std_logic := '0';
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signal GO_0 : std_logic := '0';
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signal RAM_sample_in : std_logic_vector(Sample_SZ-1 downto 0);
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signal RAM_sample_in_bk: std_logic_vector(Sample_SZ-1 downto 0);
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signal RAM_sample_out : std_logic_vector(Sample_SZ-1 downto 0);
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signal ALU_ctrl : std_logic_vector(3 downto 0);
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signal ALU_sample_in : std_logic_vector(Sample_SZ-1 downto 0);
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signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
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signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
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signal curentCel : integer range 0 to Cels_count-1 := 0;
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signal curentChan : integer range 0 to ChanelsCNT-1 := 0;
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signal sample_in_BUFF : samplT;
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signal sample_out_BUFF : samplT;
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type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
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signal IIR_CEL_STATE : fsmIIR_CEL_T;
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begin
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RAM_CTRLR2inst : RAM_CTRLR2
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generic map(Input_SZ_1 => Sample_SZ)
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port map(
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reset => reset,
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clk => clk,
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WD_sel => WD_sel,
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Read => Read,
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WADDR_sel => WADDR_sel,
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count => count,
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SVG_ADDR => SVG_ADDR,
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Write => Write,
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GO_0 => GO_0,
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sample_in => RAM_sample_in,
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sample_out => RAM_sample_out
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);
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ALU_inst :ALU
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generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
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port map(
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clk => clk,
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reset => reset,
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ctrl => ALU_ctrl,
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OP1 => ALU_sample_in,
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OP2 => ALU_coef_in,
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RES => ALU_out
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);
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WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
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Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
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WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
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count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
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SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
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--Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
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Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
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GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
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process(clk,reset)
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variable result : std_logic_vector(Sample_SZ-1 downto 0);
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begin
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if reset = '0' then
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smpl_clk_old <= '0';
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RAM_sample_in <= (others=> '0');
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ALU_ctrl <= IDLE;
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ALU_sample_in <= (others=> '0');
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ALU_Coef_in <= (others=> '0');
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RAM_sample_in_bk<= (others=> '0');
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curentCel <= 0;
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curentChan <= 0;
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IIR_CEL_STATE <= waiting;
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reset : for i in 0 to ChanelsCNT-1 loop
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sample_in_BUFF(i) <= (others => '0');
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sample_out_BUFF(i) <= (others => '0');
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sample_out(i) <= (others => '0');
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end loop;
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elsif clk'event and clk = '1' then
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smpl_clk_old <= sample_clk;
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case IIR_CEL_STATE is
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when waiting =>
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if sample_clk = '1' and smpl_clk_old = '0' then
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IIR_CEL_STATE <= pipe1;
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RAM_sample_in <= sample_in_BUFF(0);
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ALU_sample_in <= sample_in_BUFF(0);
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else
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ALU_ctrl <= IDLE;
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sample_in_BUFF <= sample_in;
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sample_out <= sample_out_BUFF;
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end if;
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curentCel <= 0;
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curentChan <= 0;
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when pipe1 =>
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IIR_CEL_STATE <= computeb1;
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ALU_ctrl <= MAC_op;
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ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(0));
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when computeb1 =>
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ALU_ctrl <= MAC_op;
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ALU_sample_in <= RAM_sample_out;
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ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(1));
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IIR_CEL_STATE <= computeb2;
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RAM_sample_in <= RAM_sample_in_bk;
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when computeb2 =>
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ALU_sample_in <= RAM_sample_out;
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ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(2));
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IIR_CEL_STATE <= computea1;
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when computea1 =>
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ALU_sample_in <= RAM_sample_out;
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ALU_Coef_in <= std_logic_vector(coefs.DenCoefs(curentCel)(1));
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IIR_CEL_STATE <= computea2;
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when computea2 =>
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ALU_sample_in <= RAM_sample_out;
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ALU_Coef_in <= std_logic_vector(coefs.DenCoefs(curentCel)(2));
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IIR_CEL_STATE <= next_cel;
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when next_cel =>
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ALU_ctrl <= clr_mac;
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IIR_CEL_STATE <= pipe2;
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when pipe2 =>
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IIR_CEL_STATE <= pipe3;
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when pipe3 =>
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result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
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sample_out_BUFF(0) <= result;
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RAM_sample_in_bk <= result;
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RAM_sample_in <= result;
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if curentCel = Cels_count-1 then
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IIR_CEL_STATE <= next_chan;
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curentCel <= 0;
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else
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curentCel <= curentCel + 1;
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IIR_CEL_STATE <= pipe1;
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ALU_sample_in <= result;
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end if;
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when next_chan =>
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rotate : for i in 0 to ChanelsCNT-2 loop
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sample_in_BUFF(i) <= sample_in_BUFF(i+1);
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sample_out_BUFF(i) <= sample_out_BUFF(i+1);
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end loop;
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sample_in_BUFF(ChanelsCNT-1) <= sample_in_BUFF(0);
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sample_out_BUFF(ChanelsCNT-1)<= sample_out_BUFF(0);
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if curentChan = (ChanelsCNT-1) then
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IIR_CEL_STATE <= waiting;
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ALU_ctrl <= clr_mac;
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else
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curentChan <= curentChan + 1;
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IIR_CEL_STATE <= pipe1;
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ALU_sample_in <= sample_in_BUFF(1);
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RAM_sample_in <= sample_in_BUFF(1);
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end if;
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end case;
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end if;
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end process;
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end ar_IIR_CEL_CTRLR;
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